science and technology memory leak in ncsim By community.cadence.com Published On :: Fri, 16 Aug 2013 06:32:51 GMT ncsim will consume an increasing ammount of memory when a function has an output port that return an associative array which was not initialized. My simulator version is 12.10-s011.Below is a code example to reproduce the failure. The code is inside a class (uvm_object): function void a_function(output bit ret_val[int]); // empty endfunction : get_coveach time the call is done a small ammount of memory is allocated. I n my case I call this function several (millions of) times during simulation and then I can see the memory leaking. Full Article
science and technology Specman Mode for Emacs By community.cadence.com Published On :: Tue, 11 Feb 2014 13:16:39 GMT Attached is the latest emacs mode for e/Specman - version 1.23 Please follow the install instructions in the top section of the actual file (after unzipping it) to install/load this package with your emacs. Full Article
science and technology help with automating adding CLP files to DRA files By community.cadence.com Published On :: Thu, 12 Jun 2014 16:50:37 GMT Question for forum: I’m currently working on a code to automatically add CLP files to DRA files and then add two classes called “APPROVED” and “CLP”. To do this manually you have to open a DRA file, click file import subdrawing and choose the clp file with the same name as dra. (path already set). You then set the clp to position x 0 0. And then click on Set Up > Subclasses > Package geometry and type in “Approved” and “Clp.” So far we’ve recorded the macros in Allegro for all of these actions. The macros correspond to one specific file name and we want to apply this to numerous files. To do this we created a python program that locates all of the specified CLP and DRA files, and if they have a matching name, runs a for loop that puts each file name into a stored variable that runs a loop for each file. We converted this script into batch and then added a function that we thought would run Allegro macros from batch. In order to get the script working, we need to have an allegro batch command that will run the script without opening the Allegro start popup, or closing the popup when it appears. We need to do this to run any script from starting Allegro. I’ve done another similar program in batch where I made a for loop for each dra file and within the loop there was a batch a2dxf command that converted all dra files to dxf files. Is there a similar batch command for adding clp files to position 0 0 and/ or adding classes? If anyone has done something similar please let me know! Thank you very much for the help. Jen Full Article
science and technology help for $sscanf By community.cadence.com Published On :: Fri, 22 Apr 2016 04:03:22 GMT Can anyone tell me how i can supress few strings or integers while reading with $sscanf. I read a line from a file into a string. there are few strings and integers seperated by white spaces in the line. I am interested in one string which comes at postion 5 in the line. how can i suppress all other strings and integers with $scanf. i tried the following syntax but it dint work. $sscanf(line,"* * * * %s",string_arg); i am tring to supress first 4 integers/strings in the line. Full Article
science and technology Creating cover items for sparse values/queue or define in specman By community.cadence.com Published On :: Fri, 12 Jul 2019 17:51:31 GMT Hello, I have a question I want to create a cover that consists a sparse values, pre-computed (a list or define) for example l = {1; 4; 7; 9; 2048; 700} I'd like to cover that data a (uint(bits:16)) had those values, Any suggestion on how to achieve this, I'd prefer to stay away from macros, and avoid to write a lot of code struct inst { data :uint(bits:16); opcode :uint(bits:16); !valid_data : list of uint(bits:16) = {0; 12; 10; 700; 890; 293;}; event data_e; event opcode_e; cover data_e is { item data using radix = HEX, ranges = { //I dont want to write all of this range([0], "My range1"); range([10], "My range2"); //... many values in between range([700], "My rangen"); }; item opcode; cross data, opcode; }; post_generate() is also { emit data_e; };}; Full Article
science and technology How to transfer trained an artificial neural network to Verilog-A By community.cadence.com Published On :: Mon, 17 Oct 2022 11:58:59 GMT Hi all, I've trained a device model with the approach of an artificial neural network, and it shows well fit. May I know how to transfer the trained model to Verilog-A, so that, we can use this model to do circuit simulation? And I've searched for some lectures that provide the Verilog-A code in the appendix, but I'm freshman in the field of Verilog-A, could anyone tell me each statement? such as real hlayer-w[0:(NI*NNHL)-1 Full Article
science and technology e-code: Shareware RAM By community.cadence.com Published On :: Thu, 20 Apr 2023 02:17:26 GMT Modified version of shr_ram from erm_lib to support mvl_valuesregards: snaptube Full Article
science and technology SI/PI Simulation and Measurement Correlation Forum By community.cadence.com Published On :: Thu, 28 Jul 2022 04:13:00 GMT Join this insightful on-demand webinar event "SI/PI Simulation and Measurement Correlation Forum" available through Signal Integrity Journal that features industry expert presentations ranging from chip to package to complex board designs.(read more) Full Article electromagnetics Power Integrity in-design analysis Signal Integrity
science and technology X-FAB's Innovative Communication and Automotive Designs: Powered by Cadence EMX Planar 3D Solver By community.cadence.com Published On :: Sun, 31 Jul 2022 17:01:00 GMT Using the EMX solver, X-FAB design engineers can efficiently develop next-generation RF technology for the latest communication standards (including sub-6GHz 5G, mmWave, UWB, etc.), which are enabling technologies for communications and electric vehicle (EV) wireless applications. (read more) Full Article EM Analysis electromagnetics in-design analysis reference design Electromagnetic analysis PDK foundry
science and technology Cadence at IMS 2022 By community.cadence.com Published On :: Tue, 02 Aug 2022 01:49:00 GMT RF Design Solutions for Next-Generation Products The International Microwave Symposium (IMS2022), otherwise known as Microwave Week, was recently held (June 19-24) at the Denver Convention center, returning to its long-standing g...(read more) Full Article 5G RF IMS in-design analysis Electromagnetic analysis microwave design microwave office thermal
science and technology This Month in IDA By community.cadence.com Published On :: Mon, 08 Aug 2022 02:55:00 GMT IDA activities in July included an endorsement from X-Fab for EMX as well as multiple multiphysics blog posts spanning SI, PI, thermal, EM and microwave analysis domains.(read more) Full Article ims2022 Power Integrity in-design analysis oncloud shift left Signal Integrity electromagnetic multiphysics
science and technology Overcoming Thermal Challenges in Modern Electronic Design By community.cadence.com Published On :: Tue, 09 Aug 2022 14:24:00 GMT Melika Roshandell talks with David Malinak in a Microwaves & RF QuickChat video about the thermal challenges in today’s complex electronic designs and how the Celsius solver uniquely addresses them.(read more) Full Article 3D-IC in-design analysis Thermal Integrity Thermal Analysis electronic systems
science and technology Japan Aviation Electronics is First to Support IP Protected Models for Cadence Clarity 3D Solver By community.cadence.com Published On :: Tue, 16 Aug 2022 04:08:00 GMT With the latest release (Sigrity and Systems Analysis 2022.1 HF2) of Clarity 3D Solver, support for encrypted component models is now available. With this functionality, vendors that supply 3D components, such as connectors, can now merge their...(read more) Full Article connector EM Clarity 3D Solver Systems Analysis JAE
science and technology BoardSurfers: Training Insights: User Interface Enhancements for Allegro Layout Editors By community.cadence.com Published On :: Fri, 19 Aug 2022 12:03:00 GMT If you have seen any images or demonstrations of the 17.4-2019 release, the GUI may look ...(read more) Full Article digital badge 17.4 BoardSurfers 17.4-2019 Training Insights Allegro PCB Editor online training Allegro
science and technology Clarity Encrypted Connectors! By community.cadence.com Published On :: Mon, 22 Aug 2022 00:25:00 GMT Cadence Clarity 3D Solver supports encrypted component models! Using this functionality, vendors can supply their 3D components, such as connectors, to end customers without revealing the physical IP of these designs. The first connector vendor to take advantage of this functionality is Japan Aviation Electronics (JAE),(read more) Full Article encryption in-design analysis connectors Electromagnetic analysis
science and technology Sigrity and Systems Analysis 2022.1 HF2 Release Now Available By community.cadence.com Published On :: Tue, 23 Aug 2022 17:45:00 GMT The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2022.1 HF2 release is now available for download at Cadence Downloads. For the list of CCRs fixed in the 2022.1 HF2 release, see the README.txt file in the installation hierarchy.(read more) Full Article Sigrity and Systems Analysis Celsius Thermal Solver Sigrity XcitePI Sigrity PowerSI Sigrity Broadband SPICE Sigrity XtractIM Sigrity PowerDC EM Clarity 3D Solver T2B Clarity 3D Workbench JAE
science and technology BoardSurfers: Managing Silkscreen Data Using Allegro 3D Canvas By community.cadence.com Published On :: Wed, 24 Aug 2022 13:30:00 GMT The silkscreen layer plays a crucial role in the assembly, repair, and testing of a PCB. You can add a variety of information to this layer, such as the location of the components, polarity, component orientation, on-off switches, LEDs, and testpoint...(read more) Full Article 17.4 BoardSurfers 3D Canvas 17.4-2019 Allegro PCB Editor silkscreen Allegro
science and technology Quickchat Video Interview: Introducing Cadence Optimality and OnCloud for Systems Analysis and Signoff By community.cadence.com Published On :: Tue, 30 Aug 2022 15:05:00 GMT Microwaves & RF's David Maliniak interviews Sherry Hess of Cadence about recently announced products of Optimality and OnCloud.(read more) Full Article SaaS in-design analysis optimization multiphysics
science and technology This Month in IDA By community.cadence.com Published On :: Tue, 06 Sep 2022 15:17:00 GMT IDA activities in August showcased two video interviews with David Maliniak of Microwaves & RF magazine. New posts, datasheets, application notes and white papers highlight multiphysics analysis spanning SI, PI, thermal, EM and microwave analysis domains are also featured.(read more) Full Article encryption in-design analysis optimization Signal Integrity electromagnetic Thermal Analysis microwave design multiphysics
science and technology BoardSurfers: Managing Design Constraints Efficiently Using Constraint Sets By community.cadence.com Published On :: Wed, 07 Sep 2022 13:44:00 GMT A constraint is a user-defined property, or a rule, applied to a physical object, such as a net, pin, or via in a design. There are a number of constraints that can be applied to an object based on its type and behavior. For example, you can define t...(read more) Full Article PCB 17.4 BoardSurfers PCB Editor Constraint Manager 17.4-2019 PCB design Constraints Allegro PCB Editor Constraint Set Allegro
science and technology Modern Thermal Analysis Overcomes Complex Electronic Design Issues By community.cadence.com Published On :: Tue, 13 Sep 2022 14:53:00 GMT By combining finite element analysis with computational fluid dynamics, designers can perform complete thermal system analysis using a single tool.(read more) Full Article in-design analysis Thermal Analysis electronic cooling
science and technology BoardSurfers: Training Insights: What’s New in the Allegro PCB Editor Basic Techniques Course By community.cadence.com Published On :: Tue, 20 Sep 2022 14:32:00 GMT The Allegro PCB Editor Basic Techniques course provides all the essential training required to start working with Allegro® PCB Editor. The course covers all the design tasks, including padstack and symbol creation, logic import, constraints setup...(read more) Full Article digital badge 17.4 BoardSurfers symbol editor 3D Canvas 17.4-2019 PCB design Training Insights Allegro PCB Editor online training Allegro
science and technology Plot on Smith Chart from HB Simulation By community.cadence.com Published On :: Tue, 30 Jan 2024 14:32:07 GMT Dear All, To design an outphasing combiner, I need to extract the input impedances when the circuit is driven by two sources concurrently with a varying phase-shift and plot them on a Smith Chart. However, I can't find a way to display the simulated S-parameters on a Smith Chart. The testbench, shown below, consists of two sources set to 50 Ohm with variable phase (PORT0: theta, PORT1: -theta) swept from -90° to 90°. The NPORTs are couplers used to isolate the forward and reflected power at each source, i.e. the S-parameters are: S13 = S31 = 1; through path S21 = S41 = 1; forward and reflected power All other are zero The testbench is simulated with an "hb" analysis instead of "sp", as the two sources have to be excited simultaneously with varying phase-shift to see their load-modulation effect. The sweep is setup in the "Choosing Analysis" window. The powers of the forward (pXa) and reflected (pXb) waves are found through the "Direct Plot" window, e.g. pvr('hb "/p1a" 0 50.0 '(1)) as the power for p1a, and named P1A_Watt. The S-parameters are then calculated as the reflected power w.r.t. the forward power P1B_Watt/P1A_Watt. This approach is based on a Hot S-parameter testbench from ADS. At this point I would like to display these S-parameters on a Smith Chart. However, this seemed more challenging than expected. One straightforward method would seem to create an empty Smith Chart window in the Display Window and dragging the S-parameters from the rectangular plot on it, but this just deletes them from the Display Window. Hence my question: How can I display these S-parameters on a Smith Chart? Full Article
science and technology EMX - Localised back etching By community.cadence.com Published On :: Wed, 07 Feb 2024 10:40:26 GMT Do you know if it is possible to define localized back etching (LBE) in EMX? It should be associated to a layer which defines the holes done in the substrate. I've not found any reference for this in the .proc syntax. --> Answer found. This is not possible because EMX considers the same dielectric in all x-y plane Full Article
science and technology EMX - 3D view + 3D view unavailable By community.cadence.com Published On :: Wed, 07 Feb 2024 19:14:47 GMT Hi! I'm using EMX with 2 design kits. In one works fine. With another, I do not see the mesh or current view. The menu item is not shown. This happens only with one DK. With the other one I'm able to run Paraview without any issue. Besides, I would like to know if there is any way to see the 3D view without mesh and current. Just a nice 3D view. I've also tried to install the latest version (EMX2023_2) but nothing changes. Full Article
science and technology Error with launching Python Script Via AWRDE VBA Script By community.cadence.com Published On :: Sun, 11 Feb 2024 03:23:21 GMT Hello Team,I am currently following this AWR script posted on them, to run a python script directly from inside AWR using VBA script. Launching Python from AWRDE VBA Script - AWR Scripts - AWR Knowledgebase Following all the basic steps with no changes to the code. I have Vscode and python-3.12.2 installed in my system. This is the error I am getting while running this code. Thank you for your help Best Regards SID Full Article
science and technology Strmount failed in streaming out cell By community.cadence.com Published On :: Thu, 15 Feb 2024 12:22:58 GMT Hi, I would be grateful if you can help me with this error which I get after trying to run an EMX simulation on a PCELL. I've found very limited information in this forum. Thanks Full Article
science and technology CPW ports By community.cadence.com Published On :: Sat, 17 Feb 2024 09:35:07 GMT Hi, in EMX I'm trying to define the ports of a CPW line as suggested in one document of the support area (i.e. P1:Gright,Gleft). The EMX simulation works fine. When I generate the schematic, I get this: Basically, the two ground ports of each end of the CPW are properly defined as a unique node (e.g. G2_1, G2_2). However, when I try a simulation I get this error: I hope you can help me. Thanks. Full Article
science and technology Harmonic Balance (HB) Large-Signal S-Parameter (LSSP) simulation By community.cadence.com Published On :: Fri, 08 Mar 2024 12:07:53 GMT Dear all, Hi! I'm trying to do a Harmonic Balance (HB) Large-Signal S-Parameter (LSSP) simulation to figure out the input impedance of a nonlinear circuit. Through this simulation, what I want to know is the large-signal S11 only (not S12, S21 and S22). So, I have simulated with only single port (PORT0) at input, but LSSP simulation is terminated and output log shows following text. " Analysis `hb' was terminated prematurely due to an error " The LSSP simulation does not proceed without second port. Should I use floating second port (which is not necessary for my circuit) to succeed the LSSP simulation? Does the LSSP simulation really need two ports? Below figure is my HB LSSP simulation setup. Additionally, Periodic S-Parameter (PSP) simulation using HB is succeeded with only single port. What is the difference between PSP and LSSP simulations? Full Article
science and technology Error when trying to generate SUL license (-8) By community.cadence.com Published On :: Tue, 09 Apr 2024 15:08:36 GMT Hi, newbie here. We are using AWR Design Enviroment in our university and so I have to install it (OS: Arch Linux)I installed it in a Windows 10 VM without problems. When I try to start it prompts "Failed to connect to license server", I guess thats the first problem. After that when trying to generate my SUL License it will prompt Internal Error -8 (see Image) I can't find something on Error -8 :/ and overall the available data to the license topic is quit low :/If someone has a solution for that I would gladly hear about it :) Full Article
science and technology VAR("") does not work within some expressions By community.cadence.com Published On :: Mon, 22 Apr 2024 20:47:33 GMT Hi, My Virtuoso and Spectre Version: ICADVM20.1-64b.NYISR30.2 I have an expression where the EvalType is "sweeps". Here is the expression (I also attached the snapshot): (peakToPeak(leafValue(swapSweep(delay(?wf1 clip((VT("/clk0") - VT("/clk180")) (VAR("mt_stop") - (4.0 / VAR("datarate"))) VAR("mt_stop")) ?value1 0 ?edge1 "rising" ?nth1 1 ?td1 0 ?tol1 nil ?wf2 clip((VT("/tx_padp") - VT("/tx_padn")) (VAR("mt_stop") - (4.0 / VAR("datarate"))) VAR("mt_stop")) ?value2 0 ?edge2 "rising" ?nth2 1 ?tol2 nil ?td2 nil ?stop nil ?multiple nil) "VDD_FIXED_NOISE") "VREGLN_cmode" 0.85 "VREGDRV_novn" 0.4 "datarate" 1.658e+10) ?overall t) / 10.0) What this expression does is that it compares the delay between the output data with respect to a reference clock. I then get this information for two conditions (VDD_FIXED_NOISE = 0 or 10mV) to get the effect of the supply-induced jitter. In the expression, I need to give the value of each parameter in different modes to distinguish them from each other. Now I want to sweep the base supply values and see the supply variation effects. For example, I want to change VREGLN_cmode from 0.85 to 0.81 and see how my supply-induced jitter changes. For that, the hard way is to copy the expression and change that value accordingly (e.g. "VREGLN_cmode" 0.81). I'm looking for an easier way to use a variable in the expression. Something like VAR("VREGLN_Sweep"). But I see it doesn't work in my expression and it gives an eVal error. I tested this before in other expressions (not sweep type) and it always worked. I have only one test and these variables are all Design Variables and not Global variables.I want to know what mistake am I doing here and is there a way to make this work. Sorry that if I could not explain better my inquiry. Thank you. Full Article
science and technology Crystal Oscillators By community.cadence.com Published On :: Thu, 23 May 2024 22:58:45 GMT Hello, Currently i am designing a 96MHZ crystal oscillator using pierce topology and also I use for amplitude gain control circuit for regulation. The problem is when i run a PSS + Pnoise i get these warnings : WARNING (CMI-2375): M2: Vgs has exceeded the oxide breakdown voltage of `vbox' = 6 V. WARNING (CMI-2375): M4: Vgs has exceeded the oxide breakdown voltage of `vbox' = 6 V. WARNING (CMI-2377): M4: Vgd has exceeded the oxide breakdown voltage of `vbox' = 6 V. WARNING (CMI-2377): M3: Vgd has exceeded the oxide breakdown voltage of `vbox' = 6.6 V. and also WARNING (CMI-2682): M5: The bulk-drain junction forward bias voltage (1.38154 V) exceeds VjdmFwd'=851.514mV ,The results are now incorrect because the junction current model has been linearized Note : i am using Supply 1.2 V hence it is not possible to exceed the oxide breakdown. So i am asking why i am getting these warnings , it could be a convergence problem and the Results computed are not corrected. Also when running DC and transient , i don't get these warnings. Full Article
science and technology Error in cds_srr (line 20) By community.cadence.com Published On :: Sun, 26 May 2024 17:33:36 GMT Hi, In the MATLAB, I am using cds_srr and cds_innersrr commands. Although I set the path to the spectre root, I face this error: One or more output arguments not assigned during call to "cds_innersrr". Error in cds_srr (line 20) sig = cds_innersrr(dirname, dataset, signame, verbose); Error in techsweep_spectre_run (line 64) struct_n = cds_srr(c.outfile, c.sweep, params_n{1}); I would highly appreciate it if you could help me. Full Article
science and technology Measuring DDJ (data dependent jitter). Cross function on eye-diagram By community.cadence.com Published On :: Fri, 31 May 2024 14:18:07 GMT Hi,My Virtuoso and Spectre Version: ICADVM20.1-64b.NYISR30.2I plot an eye diagram using a built in function. I want to see the data-dependent jitter. I want to measure the eye diagram edges at zero crossing (width of that diamond part) shown in the pic by vertical and horizontal markers. I can put a marker and read the numbers there and get what I want. But now I want to run Monte Carlo and I can't do this for all samples. I wish I could write an expression for this. Unfortunately, I see that the function "cross" is not working on the eye diagram. Basically, when I send the eye diagram data to a table, I see that it actually is just the prbs data and not the eye diagram data. Is there a hack that can help me achieve my goal which is: having an expression to measure the edges of the eye diagram at zero crossing?There is a script that Andrew wrote (https://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin%3AViewSolution%3BsolutionNumber%3D11395772). This is a good script but it puts all edges on top of each other. I want to distinguish the two edges. In the attached pic (two-period eye diagram) you can see what I mean by the two edges (diamond shapes). I want to measure each of the two and take the maximum. Having all the edges on top of each other won't give me what I want. All edges together will lso include DCD. I purely want to measure DDJ. DCD is measured separately. I have very little experience with writing scripts and could not modify Andrew's script.Your help is much appreciated. Thank you. Full Article
science and technology EVM and constellation of mixer By community.cadence.com Published On :: Wed, 05 Jun 2024 15:03:31 GMT Hello,I am trying to design an RF mixer for a TX.Assume my input IF signal is at 1 GHz, my LO at 2 GHz and I want my RF at 3 GHz, and assume that the mixer fully works after testing it with HB.How to simply set the envelope analysis to check the EVM ?I read through the documentation but I couldn't get it (I couldn't fully understand the settings of the source, probe, analysis.)Which source and probe to use? I want custom modulation with custom bandwidth and center frequency.Is there some examples for the ENVLP analysis ?I am using IC23.1 and spectre 20.1.354. Full Article
science and technology nport device S-parameter data file relative path By community.cadence.com Published On :: Fri, 21 Jun 2024 09:34:54 GMT Hi, In our design team, we're looking for a strategy to make all cell views self-contained. We are struggling to do so when nport devices are involved. The nport file requires a full path, whereas what we need is a relative path to the current path of the cell in which we're using the nport. I have browsed through the forums & cadence support pages, but could not find a solution. 1) There is a proposal from Andrew to add the file directory in ADE option "Simulation Files." :https://community.cadence.com/cadence_technology_forums/f/rf-design/27167/s-parameter-datafile-path-in-nport . This, however, is not suitable, because the cell is not self contained. 2) The new cadence version off DataSource "cellView" in nport options: This however is not suitable for us due to two reasons: i- Somehow we don't get this option in the nport cell (perhaps some custom modification from our PDK team) ii- Even if we had this option, it requires to select the library, which again makes it unsuitable: We often copy design libraries for derivative products using "Hierarchical Copy" feature. And when the library is copied, the nport will still be pointing to the old library. Thus, it is still not self-contained. In principle, it should not be difficult (technically) to point to a text file relative to the cell directory (f.ex we can make a folder under the same cell with name "sparFiles" & place all spar files under this folder), however it does not seem to be possible. Could you perhaps recommend us a work-around to achieve our goal: making the cells which contain nport devices self-contained so that when we copy a cell, we do not have to update all the nport file destinations ? Thanks in advance. My Cadence Version: IC23.1-64b.ISR4.51 My Spectre version: 23.1.0.362.isr5 Full Article
science and technology unbound variable freq By community.cadence.com Published On :: Sun, 30 Jun 2024 07:07:05 GMT I want to plot the inductance through formula L1=(imag(Z(1,1))/(2*pi*freq)), but the system tells me that the freq is unbound variable? What can I do? Full Article
science and technology IIP3 of Gilbert cell mixer By community.cadence.com Published On :: Thu, 01 Aug 2024 22:42:48 GMT Hi I'm learning Hb analysis for the IIP3 simulation of a gilbert mixer. My f_RF=5GHz, f_LO=4GHz and f_IF=1GHz . I'm a bit confused about setting the 1st order and 3rd order harmonic at the Direct plot form. I have set 1st order harmonic = 1GHz and 3rd order harminic = 2*f_LO-f_RF = 3GHz and it gives me the following results. This is my 1dB compression point result Hb analysis window Direct plot window Please let me know if my harmonic selection is correct and whether I'm getting a correct IIP3 and P1db curve Full Article
science and technology PSS Shooting - High Q crystal oscillator - Simulator by mistake detects a frequency divider By community.cadence.com Published On :: Wed, 07 Aug 2024 12:58:28 GMT Hi *, I am simulating a 32kHz high Q crystal oscillator with a pulse shaping circuit. I set up a PSS analysis using the Shooting Newton engine. I set a beat frequency of 32k and used the crystal output and ground as reference nodes. After the initial transient the amplitude growth was already pretty much settled such that the shooting iterations could continue the job. My problem is: In 5...10% of my PVT runs the simulator detects a frequency divider in the initial transient simulation. The output log says: Frequency divided by 3 at node <xxx> The Estimated oscillating frequency from Tstab Tran is = 11.0193 kHz . However, the mentioned node is only part of the control logic and is always constant (but it has some ripples and glitches which are all less than 30uV). These glitches spoil my fundamental frequency (11kHz instead of 32kHz). Sometimes the simulator detects a frequency division by 2 or 3 and the mentioned node <xxx> is different depending on PVT - but the node is always a genuine high or low signal inside my control logic. How can I tell the simulator that there is no frequency divider and it should only observe the given node pair in the PSS analysis setup to estimate the fundamental frequency? I have tried the following workarounds but none of them worked reliably: - extended/reduced the initial transient simulation time - decreased accuracy - preset override with Euler integration method for the initial transient to damp glitches - tried different initial conditions - specified various oscillator nodes in the analysis setup form By the way, I am using Spectre X (version 21.1.0.389.ISR8) with CX accuracy. Thanks for your support and best regards Stephan Full Article
science and technology HB: duplicated frequencies in 3-tone simulation By community.cadence.com Published On :: Fri, 09 Aug 2024 11:51:48 GMT I get multiple results at the same frequency in a 3-tone simulation. I try to determine the IP3 of a mixer. I have 3 large signal tones: 0.75 GHz, 1.25 GHz and 1.26 GHz. At the IM3 frequency of 490 MHz I observe 4 results, see also the screenshot of the table output. The frequencies are exactly the same (even when I subtract 490 MHz by using xval() ). Which of the values do I have to use to determine the correct IP3? Is there an option to merge these results? Full Article
science and technology Colpitts Oscillator output power simulation By community.cadence.com Published On :: Thu, 22 Aug 2024 08:44:20 GMT Hello everybody, As you can find in the attached image, I am trying to simulate a Colpitts oscillator. However, using pss analysis it shows a high output power. My question is where is the problem of my structure or simulation setup? Best, Full Article
science and technology Load Pull transistor simulation By community.cadence.com Published On :: Tue, 10 Sep 2024 08:11:18 GMT Hello everyone, I am trying to perform a load pull simulation of a transistor to verify some gain calculations I made using its S-parameters. Specifically, I have calculated the optimal conjugate impedances for the input and output to later calculate the power dissipated and transmitted in each stage of the transistor. Then, I only varied the output impedance and recalculated these powers, noticing that the power delivered to the load is lower. Now, what I want to do is simulate this behavior using the Load Pull simulation. I have taken the model shown in the image, but I believe it is a linear model. My question is: if the chosen model is linear, is the load pull simulation accurate? In the calculations I made, nonlinearities are not considered. I don’t want to take nonlinearities into account. In short, do you have any ideas on how to verify the calculations made with the transistor’s S-parameters through a load pull simulation? Can you recommend any transistor model that is nonlinear and also has an S-parameter file? Thank you very much in advance. Full Article
science and technology Getting error while adding element in AWR software By community.cadence.com Published On :: Tue, 17 Sep 2024 13:23:10 GMT While adding an element created from a netlist file in AWR, I am getting the error 'The element type being dropped is not compatible with the window it is being dropped into'. The netlist file in AWR has the following contents: .subckt BFG520W base collector emitter npn.model BFG520W NPN(IS=1.016E-15 NF=1.000 BF=220.1 IKF=510E-3 VAF=48.06+ ISE=2.83E-13 NE=2.035 NR=0.988 BR=100.7 IKR=2.352E-3 + VAR=1.692 ISC=24.48E-18 NC=1.022 RB=10.00 RE=0.7753+ RC=2.21 CJC=447.6E-15 MJC=0.07 VJC=0.1892 + CJE=1.245E-12 TF=8.616E-12 TR=5.437E-12 mfg=NXP) I have attached screenshots of the element BFG520W2 created due to the above netlist and the error I am getting while adding this element. Full Article
science and technology Cross-coupled oscillator Stability simulation By community.cadence.com Published On :: Thu, 10 Oct 2024 10:21:33 GMT Hello everyone, For my cross-coupled oscillator design, I have a problem with stability analysis. Based on my achieved results which are attached, where is my design problem? Best, https://ibb.co/bgKFP4N https://ibb.co/3FGRLmV https://ibb.co/pwSZDSF Full Article
science and technology EMX - EM simulation for large CMOS chip By community.cadence.com Published On :: Tue, 22 Oct 2024 11:05:16 GMT Hi everyone, I'm currently working on my thesis, which involves a beamformer system using CMOS 65nm technology. I'm trying to use the EMX tool for EM simulation but have encountered a few problems. Before diving into my questions about EMX, let me briefly explain how I conduct EM simulations with other software (ADS). In ADS, I use the EM simulator with the Momentum microwave engine. However, my EM layout is quite large, and the mesh generated is extremely detailed, making it difficult to simulate the entire system. As a workaround, I divide the system into smaller parts and simulate each one individually. I've attached a snapshot of my setup, which includes an amplifier and a 1-to-2 Wilkinson power divider. I've separated these circuits and placed pins to facilitate EM simulations for each. I also placed ground pins at the boundaries of each circuit to connect them to the ground plane. Here’s the link to the image (I'm unable to upload it due to an error): https://drive.google.com/file/d/13Qn4-DvMBj_K1JQLXrTWaWZ8uaLJr15u/view?usp=sharing Now, moving on to EMX (version 6.3). For a maximum frequency of 31 GHz, I set the edge mesh = thickness = 0.4 µm (approximately the skin depth). However, when I simulate the circuit (amplifier + divider), the mesh on the ground plane becomes very dense, which makes running the simulation impossible due to excessive memory requirements. I reverted to my ADS approach and divided the circuit into two parts, placing ports to connect them. Unfortunately, EMX doesn't allow me to place multiple edge ports on the same edge for the ground plane, which has left me confused. Here are a couple of questions I have: Is breaking the circuit into smaller parts a valid approach? Given the large ground plane, the mesh size for the ground is significant, making simulations challenging. Are there any methods to manage this issue? Regarding the ground pins, why can't I place multiple edge ports to connect the ground planes of both circuits as I did in ADS? If this approach is incorrect, could you suggest alternative methods for simulating individual circuits and connecting them to estimate system performance? Any insights would be greatly appreciated. Thank you in advance for your help! Full Article
science and technology Figures missing in the RF Design Blogs article of "Measuring Fmax for MOS Transistors" By community.cadence.com Published On :: Wed, 30 Oct 2024 16:18:37 GMT Hi I noticed that some figures from the old posts in the cadence blogs have been missing. I think this problem happened before and Andrew Beckett asked the original author to fix the issue: Figures missing in the RF Design Blogs article of "Measuring Fmax for MOS Transistors" Some of these posts are quite valuable, and would be nice to have access to the figures, which are a very important part of some posts, Thanks Leandro Full Article
science and technology Transient Simulation waveform abnormal By community.cadence.com Published On :: Sat, 02 Nov 2024 14:37:09 GMT Hello Everybody Recently, I want to design a high output Power Amplifier at 2.4GHz using TSMC 1P6M CMOS Bulk Process. I use its nmos_rf_25_6t transistor model to determine the approximate mosfet size I use the most common Common-Source Differential Amplifier topology with neutralizing capacitor to improve its stability and power gain performance Because I want to output large power, the size of mosfet is very large, the gate width is about 2mm, when I perform harmonic balance analysis, everything is alright, the OP1dB is about 28dBm (0.63Watt) But When I perform Transient simulation, the magnitude of voltage and current waveform at the saturation point is too small, for voltgae, Vpeaking is about 50mV, for current, Ipeaking is about 5mA I assume some reasons: the bsim4 model is not complete/ the virtuoso version is wrong (My virtuoso version is IC6.1.7-64b.500.21)/the spectre version is wrong (spectre version is 15.1.0 32bit)/the MMSIM version is wrong/Transient Simulation setting is wrong (the algorithm is select gear2only, but when I select other, like: trap, the results have no difference), the maxstep I set 5ps, minstep I set 2ps to improve simulation speed, I think this step is much smaller than the fundamental period (1/2.4e9≈416ps) I have no idea how to solve this problem, please help me! Thank you very very much! Full Article
science and technology Virtuosity: Reliability Analysis Report-Reliable Results Made Interactive By community.cadence.com Published On :: Thu, 09 Jun 2022 07:47:00 GMT Read through this blog to know more about the new Reliability Report view in Virtuoso ADE Assembler and Virtuoso ADE Explorer.(read more) Full Article SQLite Stress Analysis Analog Design Environment ADE Explorer Reliability Report Virtuoso Analog Design Environment Virtuoso Spectre Virtuosity ISR21 Virtuoso Video Diary ICADVM20.1 SQLite Operator aging ISR26 reliability analysis custom reliability data filter Custom IC IC6.1.8 ADE Assembler
science and technology Virtuoso Meets Maxwell: Getting Your Existing SiP File Into Virtuoso RF Solution By community.cadence.com Published On :: Tue, 21 Jun 2022 13:44:00 GMT I have been involved in the Virtuoso RF Solution for the last four years. Most of the customers I work with have a SiP package already in progress. They often ask "How do I get my SiP design into Virtuoso RF Solution?" I am excited about new functionality in the latest ICADVM20.1 ISR25 release. It is a new GUI under the Tools menu called Enablement. (read more) Full Article SiP Enablement GUI Virtuoso Meets Maxwell Virtuoso RF Solution Virtuoso RF Allegro Package Designer Plus Assisted Export System Design Environment RF design SiP Layout Option Custom IC Design Assisted Flows Assisted Import Allegro
science and technology Spectre Tech Tips: Accuracy 101 By community.cadence.com Published On :: Thu, 30 Jun 2022 16:33:00 GMT In this post, we will learn about the most important parameters for the analog simulators that affect the accuracy of the simulation results. We will also understand how each parameter limits the accuracy of the measurements for the DC and transient analyses.(read more) Full Article Analog Simulation accuracy analog vabstol Spectre Simulators iabstol reltol spectre x Spectre X Simulator