1 Papua New Guinean Kina = 16.5657 Macedonian Denar

1 Papua New Guinean Kina = 5.198 Moldovan Leu

1 Papua New Guinean Kina = 2.8641 Moroccan Dirham

1 Papua New Guinean Kina = 0.1763 Latvian Lat

1 Papua New Guinean Kina = 0.8608 Lithuanian Lita

1 Papua New Guinean Kina = 54.3724 Sri Lanka Rupee

1 Papua New Guinean Kina = 440.989 Lebanese Pound

1 Papua New Guinean Kina = 123.0158 Kazakhstan Tenge

1 Papua New Guinean Kina = 0.243 Cayman Islands Dollar

1 Papua New Guinean Kina = 0.0902 Kuwaiti Dinar

1 Papua New Guinean Kina = 355.5874 South Korean Won

1 Papua New Guinean Kina = 30.9149 Kenyan Shilling

1 Papua New Guinean Kina = 31.0974 Japanese Yen

1 Papua New Guinean Kina = 0.2068 Jordanian Dinar

1 Papua New Guinean Kina = 42.6308 Icelandic Krona

1 Papua New Guinean Kina = 22.0104 Indian Rupee

1 Papua New Guinean Kina = 1.0222 Israeli New Sheqel

1 Papua New Guinean Kina = 4306.6366 Indonesian Rupiah

1 Papua New Guinean Kina = 94.1995 Hungarian Forint

1 Papua New Guinean Kina = 2.0227 Croatian Kuna

1 Papua New Guinean Kina = 7.2967 Honduran Lempira

1 Papua New Guinean Kina = 2.2642 Hong Kong Dollar

1 Papua New Guinean Kina = 0.235 British Pound Sterling

1 Papua New Guinean Kina = 0.6568 Fiji Dollar

1 Papua New Guinean Kina = 0.2657 Euro

1 Papua New Guinean Kina = 4.537 Egyptian Pound

1 Papua New Guinean Kina = 4.1577 Estonian Kroon

1 Papua New Guinean Kina = 37.4116 Algerian Dinar

1 Papua New Guinean Kina = 16.045 Dominican Peso

1 Papua New Guinean Kina = 2.0059 Danish Krone

1 Papua New Guinean Kina = 7.3265 Czech Republic Koruna

1 Papua New Guinean Kina = 165.8525 Costa Rican Colon

1 Papua New Guinean Kina = 1135.88 Colombian Peso

1 Papua New Guinean Kina = 2.0622 Chinese Yuan Renminbi

1 Papua New Guinean Kina = 240.7325 Chilean Peso

1 Papua New Guinean Kina = 0.2831 Swiss Franc

1 Papua New Guinean Kina = 0.4086 Canadian Dollar

1 Papua New Guinean Kina = 3.5402 Botswana Pula

1 Papua New Guinean Kina = 1.6711 Brazilian Real

1 Papua New Guinean Kina = 2.0102 Bolivian Boliviano

1 Papua New Guinean Kina = 0.412 Brunei Dollar

1 Papua New Guinean Kina = 0.1102 Bahraini Dinar

1 Papua New Guinean Kina = 0.5263 Bulgarian Lev

1 Papua New Guinean Kina = 24.777 Bangladeshi Taka

1 Papua New Guinean Kina = 0.4461 Australian Dollar

1 Papua New Guinean Kina = 19.3777 Argentine Peso

1 Papua New Guinean Kina = 0.5233 Netherlands Antillean Guilder

1 Papua New Guinean Kina = 1.0708 United Arab Emirates Dirham

Physical synthesis has been around in various forms for many years. The basic idea is to bring some awareness of physical layout into synthesis. This week (June 3, 2015) Cadence is rolling out the Genus™ Synthesis Solution, a next-generation RTL synthesis tool that takes physical awareness in some new directions.

Here are four important things to know about Genus technology:

• A massively parallel architecture improves turnaround time by up to 5X while maintaining quality of results
• The Genus solution synthesizes up to 10M+ instances flat without impacting power, performance and area (PPA)
• The Genus solution provides tight correlation with the Innovus Implementation System, using the same placement and routing algorithms
• Globally focused PPA optimization saves up to 20% datapath area and power

Compared to previous-generation products such as the Cadence Encounter RTL Compiler Advanced Physical Option, the Genus solution approaches physical synthesis in a different way. The Encounter solution applied physical optimization “at the tail end of synthesis,” said David Stratman, senior principal product manager at Cadence. “We were doing a final incremental push, but we could only do so much, since we had locked in a lot of the earlier steps from a logical-only synthesis perspective.”

Genus Synthesis Solution supports the physical synthesis features in the previous Encounter solution, but it also brings the full physical scope upstream to RTL logic designers. “It’s going to enable the unit-level RTL designer to gain the benefits of physical synthesis without having to understand it,” Stratman said. As an example, users can apply generic (unmapped) placement at the earliest stages of synthesis, using a lightweight version of the Innovus placement engine. The bottom line: “Genus is a full solution where every step of synthesis can be done physically.”

Getting Massively Parallel

If you bring physical data into synthesis, you need a way to improve capacity and runtimes, especially with today’s gigantic advance-node SoCs. That’s why a massively parallel architecture is the cornerstone of the Genus solution. In this way, the Genus solution is following in the footsteps of the Innovus Implementation System, which also provides a massively parallel architecture.

Both the Innovus and Genus solutions can handle blocks of 10M instances flat. Given that SoCs today may have up to 100M instances, and often up to 50-100 top-level blocks, this is an important capability. Many tools today will only handle blocks of 1M instances. As a result, design teams often have to constrain block sizes.

Genus technology offers timing-driven, multi-level design partitioning across multiple threads and machines. It enables a near-linear runtime scaling without impacting PPA. According to Stratman, the Genus solution will scale well beyond 64 CPUs for a large design, with a “sweet spot” around 8-20 CPUs for today’s typical block sizes. Runs that used to take days, he noted, can now be done in hours.

As shown below, Genus technology leverages parallelism at three levels. The Genus solution can distribute design partitions to multiple threads or CPUs, and also supports local algorithm-level multithreading on each machine with shared memory. An adaptive scheduler ensures the best use of the available CPUs.

Fig. 1 – Genus Synthesis Solution provides three levels of parallelism

With its massive parallelism, Stratman said, Genus technology can obtain production-level quality of results (QoR) in runtimes typically seen in “prototype-level” synthesis runs. The “secret sauce,” he said, is in the partitioning. Cadence has found a way to generate partitions in a way that “slices the design more intelligently, and takes advantage of the Genus database to merge partitions without losing timing, power, or area,” Stratman said.

Playing in the Sandbox

In the Genus Synthesis Solution, a process called “sandboxing” allows any subset or partition of a design to be extracted along with full timing and a physical context. Optimization algorithms will treat a sandbox as a complete design.

The “Clipper” flow clips out or extracts the context of the larger SoC blocks. “It’s kind of a skeleton floorplan but it has all the timing information,” Stratman said. These extracted contexts include all the critical physical information to make the right RTL synthesis choices at the unit level. This information is used to streamline the handoffs between unit-level RTL designers, integration engineers, and implementation engineers. It’s a way for logic designers to gain some physical knowledge without having to be a physical synthesis expert, or without having to run a full top-level synthesis.

Fig. 2 – Clipper flow provides context for unit-level blocks

Correlation with Innovus Implementation System

Although Genus technology can work with third-party IC implementation systems, it shares algorithms and engines with Innovus Implementation System, as well as a common user interface. As shown below, both the Genus and Innovus solutions use a table-based Quantus QRC parasitic extraction, effective current source model (ECSM) and composite current source (CCS) delay calculations, and a unified global routing engine. Timing and wire length claim a 5% correlation.

Fig. 3 – Genus Synthesis Solution offers tight correlation with Innovus Implementation System

Genus technology doesn’t model everything to the same level of accuracy as the Innovus solution, however. “We chose to be lighter weight and more nimble to get expected runtimes,” Stratman said. A tight correlation is possible because the Genus and Innovus solutions use a similar code base. This correlation will be tighter than that between Encounter RTL Compiler Advanced Physical Option and the Encounter Digital Implementation System today.

Genus Synthesis Solution uses a new Hybrid Global Router that provides the ability to resolve congestion and construct layer-aware, timing-driven wire topologies. This accelerates analysis and debug, and reduces iterations. Users can avoid blockages and see a full Manhattan route as opposed to “flight lines.” Layer awareness is particularly important, given the large RC variations within the metal stack at advanced process nodes.

A version of the Innovus GigaPlace engine is available within the Genus solution. Here, users can do an RTL-level generic gate placement early in the synthesis flow (“generic gate” means there is no mapping into standard cell libraries, but there’s still an area estimate). This helps designers understand PPA tradeoffs earlier.

While users can go all the way to a design-rule “legal” placement with Genus Synthesis Solution, this isn’t generally recommended. “You can do a placement and use the same algorithms as GigaPlace and get a nice correlation without all the runtimes and additional steps of doing a fully legal placement,” Stratman said.

So where does Genus technology end and Innovus technology begin? That’s up to the user. You could use the Genus solution for logical synthesis and run all physical implementation in the Innovus system. If you run physical synthesis within the Genus solution, there’s more work earlier in the flow, but you get better insights into downstream problems and reduce iterations.

“Physical synthesis should be no more than 2X [runtime] of logic synthesis,” Stratman said. “All of the runtime that moves up should be shaved off of the place-and-route stages, because now you can do lightweight incremental optimization and incremental placement. The overall flow should be runtime neutral or better.”

Be Globally Aware

Finally, Genus Synthesis Solution offers a globally focused early PPA optimization across the whole datapath, delivering up to a 20% area reduction in the datapath. Stratman noted that this capability is a follow-on to an RCP feature called “globally focused mapping” that can determine the best cells to use in a library. What’s new with the Genus solution is that this concept has been applied at the arithmetic level.

For example, there are many ways to configure a multiplier – you may want to prioritize speed, power, or size. In the past, Stratman noted, synthesis tools have not been very good at globally optimizing the architecture selection for PPA optimization. “We can [now] find the most efficient global datapath implementation for a given region,” he said.

For further information about the Cadence Genus Synthesis Solution, including a datasheet and technical product brief, see this landing page.

Richard Goering

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One reason for attending the upcoming Design Automation Conference (DAC 2015) is to learn about challenges other engineers have faced, and hear about their solutions. And the best place to do that is the Cadence Theater, located at the Cadence booth (#3515). The Theater will host continuous half-hour customer and partner presentations from 10:00 am Monday, June 8, to 5:30 pm Wednesday June 4.

As of this writing, 43 presentations are scheduled. This includes 17 customer presentations, 23 partner presentations, and 3 Cadence presentations, The presentations are open to all DAC attendees and no reservations are required.

Cadence customers who will be speaking include engineers from AMD, ams, Allegro Micro, Broadcom, IBM, Netspeed, NVidia, Renesas, Socionet, and STMicroelectronics. Partner presentations will be provided by ARM, Cliosoft, Dini Group, GLOBALFOUNDRIES, Methodics, Methods2Business, National Instruments, Samsung, TowerJazz, TSMC, and X-Fab.

These informal presentations are given in an interactive setting with an opportunity for questions and answers. Audio recordings with slides will be available at the Cadence web site after DAC. To access recordings of the 2014 DAC Theater presentations, click here.

This Cadence DAC Theater presentation drew a large audience at DAC 2015

Here’s a listing of the currently scheduled Cadence DAC Theater presentations. The latest schedule is available at the Cadence DAC 2015 site.

Monday, June 8

Tuesday, June 9

Wednesday, June 10

In a Wednesday session (June 10, 10:00 am) at the theater, the Cadence Academic Network will sponsor three talks on academic/industry collaboration models. Speakers are Dr. Zhou Li, architect, Cadence; Prof. Xin Li, Carnegie-Mellon University; and Prof. Laleh Behjat, University of Calgary.

As shown above, there will be a giveaways for a set of Bose noise-cancelling headphones, an iPad Mini, and a GoPro Hero3 video camera.

See the Cadence Theater schedule for further details. And be sure to view our Multimedia Site for live blogging and photos and videos from DAC. For a complete overview of Cadence activities at DAC, see our DAC microsite.

Richard Goering

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