A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.

A relationship between distance from a back bias control section which outputs a control signal for controlling a back bias of a transistor and an amount of noise in the control signal outputted from the back bias control section is found. An increase of jitter corresponding to the amount of the noise in a clock transmitted on a clock path connected to a circuit section (IP macro) is found on the basis of the relationship between the distance from the back bias control section and the amount of the noise. The circuit section and the clock path are placed on the basis of the increase of the jitter and an allowable jitter value for the circuit section.

A method includes providing a design of a semiconductor device such as a stacked CMOS device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based on at least one predetermined criterion. Each respective one of the at least one first type of circuit element is to be assigned to a respective designated one of the plurality of tiers. The method further includes dividing the remainder of the plurality of circuit elements into at least two groups of circuit elements based on circuit density, and assigning the at least one first type of circuit element and the at least two groups of circuit elements to respectively different ones of the plurality of tiers of the semiconductor device.

A method for designing a transformer in an integrated circuit includes receiving one or more desired characteristics of the transformer from user input and iteratively determining a design solution for the transformer through one or more simulations and modifications using a rule-set. The method combines the one or more desired characteristics with other preset characteristics of the transformer or the integrated circuit. A first model of the transformer is defined with typical load impedances and simulated having the combined characteristics to determine performance. Results of the simulation are processed to calculate performance with the load impedances specified by the user. The results are further processed to obtain a mathematical model that includes tuning capacitors. The first and subsequent models are modified by drawing on a rule-set of expert knowledge relating to general dependency of at least one design criterion, such as a physical, geometrical or performance characteristic, with another design criterion.

In a method for fracturing or mask data preparation or mask process correction for charged particle beam lithography, a plurality of shots are determined that will form a pattern on a surface, where shots are determined so as to reduce sensitivity of the resulting pattern to changes in beam blur (βf). In some embodiments, the sensitivity to changes in βf is reduced by varying the charged particle surface dosage for a portion of the pattern. Methods for forming patterns on a surface, and for manufacturing an integrated circuit are also disclosed, in which pattern sensitivity to changes in βf is reduced.

A via disposition information acquiring unit acquires via disposition information indicating a disposition of the plurality of first vias (212). A second conductor information acquiring unit acquires second conductor information indicating disposition positions of a plurality of second conductors (232) repeatedly disposed in the second conductor layer (230). A via extracting unit extracts an extraction via with respect to each of the plurality of second conductors (232). The extraction via is each of the first vias (212) overlapping the second conductor (232). A via selecting unit selects a selection via with respect to each of the plurality of second conductors (232). The selection via is each of first vias (212) selected in a predetermined number from the extraction vias. An opening introducing unit introduces a first opening (234) to each of the plurality of second conductors (232). The first opening (234) overlaps the extraction via not selected by the via selecting unit in plan view.

A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.

A method for mask data preparation or mask process correction is disclosed in which a set of charged particle beam shots is determined which is capable of forming a pattern on a surface, wherein critical dimension uniformity (CDU) of the pattern is optimized. In some embodiments the CDU is optimized by varying at least two factors. In other embodiments, model-based techniques are used. In yet other embodiments, the surface is a reticle to be used in an optical lithographic process to form a pattern on a wafer, and CDU on the wafer is optimized.

A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least partly on the generated signal behaviour description, and performing gate-level simulation using the generated gate-level stimuli to generate gate-level activity data for the IC design. In one embodiment, generating the signal behaviour description includes performing Register Transfer Level (RTL) simulation of the IC design, and generating the gate-level netlist includes performing RTL synthesis. The RTL simulation and RTL synthesis are performed on RTL data for the IC design.

A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.

A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits reference a top-level circuit or subcircuits (by name or by specific instance), and the simulator automatically binds vunit contents appropriately during circuit hierarchy expansion. Vunits may be re-used for other design cells, and may be easily processed by text-based design tools. Vunits may be provided via vunit_include statements in a control netlist file, command line arguments, or by directly placing a vunit block into a netlist. Vunits may also contain instance statements to monitor or process signals, such as those needed by assertions.

A method of forming a magnetic tunnel junction (MTJ) device includes forming a first MTJ cap layer on a MTJ structure. The first MTJ cap layer includes a first non-nitrified metal. The method also includes forming a second MTJ cap layer over the first MTJ cap layer. The second MTJ cap layer includes a second non-nitrified metal. The method further includes forming a top electrode layer over the second MTJ cap layer. The second MTJ cap layer is conductive and configured to reduce or prevent oxidation.

A method and system for optical proximity correction (OPC) is disclosed in which a set of shaped beam shots is determined which, when used in a shaped beam charged particle beam writer, will form a pattern on a reticle, where some of the shots overlap, where the pattern on the reticle is an OPC-corrected version of an input pattern, and where the sensitivity of the pattern on the reticle to manufacturing variation is reduced. A method for fracturing or mask data preparation is also disclosed.

A circuit-design support method includes obtaining information for a circuit having a logic circuit in which signal lines are connected to input terminals, signals of the signal lines being output via the logic circuit; obtaining information concerning a control circuit that has a first flip-flop for scanning and that can control a value of a given signal line by a value set by the first flip-flop; selecting, based on the circuit information, a second flip-flop at an output destination of a signal from the logic circuit, among second flip-flops of the circuit; and generating, based on the control circuit information, information indicating a serial connection of the control circuit between an output source of the signal of the given signal line and the given signal line and a connection of a data input terminal of the first flip-flop and an output terminal of the selected second flip-flop.

Disclosed are methods, systems, and articles of manufactures for implementing physical designs by using multiple force models to iteratively morph a layout decomposition. In addition to attractive force model(s) or repulsive force model(s), the physical implementation also uses a containment force model for grouping multiple design blocks or for confining a node of a cell within the boundary of a container. Another aspect is directed at deriving a first force model at the first hierarchical level from a second force model at the second hierarchical level by directly modifying the second model based at least in part on characteristic(s) of the first hierarchical level and of the second hierarchical level. In a design with multiple hierarchies, a cell-based force model is also used to ensure child nodes of a parent cell stay within a close proximity of the parent node of the parent cell.

The present invention is directed to provide a resist remover composition for semiconductor substrate which enables to remove a resist simply and easily in the photolithography process in the semiconductor field, and a method for removing a resist comprising that the composition is used. The present invention relates to a resist remover composition for semiconductor substrate, comprising [I] a carbon radical generating agent, [II] an acid, [III] a reducing agent, and [IV] an organic solvent, and having pH of lower than 7, and a method for removing a resist, comprising that the composition is used.

A cleaning composition for sanitizing and/or disinfecting hard surfaces, comprising: a cationic biocide, surfactant and low levels of VOC solvents. The cleaning composition is adapted to clean a variety of hard surfaces without leaving behind a visible residue and creates low levels of streaking and filming on the treated surface. The cleaning composition contains less than 5% by weight of VOCs. The cleaning composition may be used alone as a liquid or spray formulation or in combination with a substrate, for example, a pre-loaded cleaning wipe.

A cleansing composition for cosmetic or household use may include an ampholytic polymer; a crosslinked cationic polymer; a surfactant component selected from the group consisting of anionic surfactants, amphoteric surfactants, cationic surfactants, nonionic surfactants, and zwitterionic surfactants; and an aqueous and/or organic carrier.

A new general purpose foaming agent having application as drilling fluid foaming agents or as any foaming agent needed an a wide variety of applications is disclosed, where the agent includes at least one anionic surfactant, at least one cationic surfactant, and mixtures thereof and one or more zwitterionic compounds. A method for using the foaming agent in capillary coiled tubing application is also disclosed. The foaming agents can also include additive to augment the properties of the foaming agent for a given application.

The invention relates to compositions including a hypohalite or hypochlorous acid and a soluble salt of 2,4,6 mesitylene sulfonate. The compositions may include a surfactant, a buffer, or combinations thereof. Other adjuvants may also be present. Such compositions do not require the inclusion of high concentrations of sodium hydroxide or other soluble hydroxide salts to drastically increase pH (and thus stability), although such hydroxides may be present if desired.

A method for softening laundry employs a softening composition, which includes at least one thickener containing a cationic polymer obtained by polymerization: of a cationic monomer;of a monomer with a hydrophobic nature, of formula (I): wherein R1=H or CH3 R2=alkyl chain having at least 16 carbon atomsX═O, m≧5, y=z=0, orX═NH, m≧z≧5, y=0, orX═NH, m≧y≧5, z=0, of a nonionic monomer.

A rinse-off composition, such as a shampoo, hair conditioner or shower gel, comprising a rinse-off composition base, lactoyl ethanolamine and at least one compound selected from the group consisting of N-(4-cyanomethylphenyl) p-menthanecarboxamide and N-(2-pyridin-2-ylethyl) p-menthanecarboxamide. The compositions provide a pleasant, long-lasting cooling sensation.

A process for preparing a particle defoamer. The particle defoamer of 55%-75% of a carrier, 15%-35% of a silicone emulsion, 3%-10% of a texturing agent and 2%-10% of a solvent, based on the total weight of the particle defoamer; the process for preparing the particle defoamer is: (1)first adding a carrier A1 into a mixer, and then adding thereto a silicone emulsion B1, and stirring uniformly; (2)adding a carrier component A2 to the mixture obtained in (1), and stirring uniformly; (3)adding a silicone emulsion B2 to the mixture obtained in (2), and, after uniformly stirring, adding the solvent thereto and stirring uniformly; and (4)pelleting and drying by baking the mixture obtained in(3), so as to produce the product.

Gemini surfactants of bis-N-alkyl polyether, bis-N-alkenyl polyether, bis-N-cycloalkyl polyether, bis-N-aryl polyether bis-beta or alpha-amino acids or their salts, are produced for use as multifunctional corrosion inhibitors, which protect and prevent corrosion of ferrous metals exposed to acidic, basic and neutral liquids when transporting or storing crude oil and liquid fuels. The surfactants are also used to inhibit corrosion of equipment and pipes used in cooling systems in petroleum and petrochemical equipment. The Gemini surfactants have the structural formula:

The present invention is directed to provide a semiconductor surface treating agent; composition which is capable of stripping an anti-reflection coating layer, a resist layer, and a cured resist layer in the production process of a semiconductor device and the like easily and in a short time, as well as a method for treating a semiconductor surface, comprising that the composition is used. The present invention relates to a semiconductor surface treating agent; composition, comprising [I] a compound generating a fluorine ion in water, [II] a carbon radical generating agent; , [III] water, [IV] an organic solvent, and [V] at least one kind of compound selected from a group consisting of hydroxylamine and a hydroxylamine derivative represented by the general formula [1], as well as a method for treating the semiconductor surface, comprising that the composition is used: (wherein R1 represents a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups; R2 represents a hydrogen atom, a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups).

Compositions and methods for treating biofilm formation and growth on a substrate are provided. The composition comprises 1 ppb to 1,000 ppm of at least one D-amino acid and 1 ppm to 60,000 ppm of at least one biocide. The method comprises contacting the substrate with 1 ppb to 1,000 ppm of at least one D-amino acid and 1 ppm to 60,000 ppm of at least one biocide. The compositions and methods are effective for preventing, reducing or eliminating biofilm formation or biofilm growth or both, as well as eradicating established, recalcitrant biofilms, particularly biofilms comprising sulfate reducing bacteria that are known to cause microbiologically influenced corrosion, biofouling, or both.

A cleansing composition for cleansing skin, especially for removing grease from skin. A cleaning composition of the present invention may also be used in ready-to-use (or in-use) kits, such as two component kits, suitable for cleansing skin.

A granulated foam control composition comprises a foam control agent based on a polydiorganosiloxane fluid, an organic additive of melting point 45″17C to 100° C. comprising a polyol ester, a water-soluble particulate inorganic carrier and a polymer having a net cationic charge. The mean number of carbon atoms in the organo groups of the polydiorganosiloxane fluid is at least 1.3. The foam control agent includes a hydrophobic filler dispersed in the polydiorganosiloxane fluid, and optionally an organosilicone resin. The polyol ester is miscible with the polydiorganosiloxane fluid.

The invention relates to compositions, methods of use, and methods of manufacture for an intercalated bleach compound and compositions thereof. The intercalated bleach compound has the formula Mx(OCl)y(O)m(OH)n where M is an alkaline earth metal such as magnesium, calcium or mixture thereof. The values of x and y independently equal any number greater than or equal to 1 (e.g., 1, 2, 3, 4, etc.), and m and n independently equal any number greater than or equal to 0 (e.g., 0, 1, 2, 3, 4, etc.), but m and n are not both 0. In addition, the molar ratio of the alkaline earth metal (e.g., magnesium or calcium) to hypochlorite is at least 3:1. In other words, x is ≧3y. The compounds exhibit excellent stability, little or no chlorine bleach odor, exhibit excellent pH buffering characteristics, and less reactivity with organic materials as compared to alternative chlorine bleach products.

A mixture of surfactants from alkylene oxide adducts with different degrees of alkoxylation is used in a urea solution to be added to an exhaust stream for reduction of nitrous gases.

An apparatus and method for moving a wire along its own axis against a high resistance to its motion causing a substantial uniaxial compression stress in the wire without allowing it to buckle. The apparatus consists of a wire gripping and moving drive wheel and guide rollers for transporting the moving wire away from the drive wheel. Wire is pressed into a peripheral groove in a relatively large diameter, rotating drive wheel by a set of small diameter rollers arranged along part of the periphery causing the wire to be gripped by the groove.

The present disclosure relates to a superconducting rotating electrical machine and a manufacturing method for a high temperature superconducting film thereof. The superconducting rotating electrical machine includes a stator, and a rotor rotatable with respect to the stator, the rotor having a rotary shaft and a rotor winding. Here, the rotor winding includes tubes disposed on a circumference of the rotary shaft and each forming a passage for a cooling fluid therein, superconducting wires accommodated within the tubes, and a cooling fluid flowing through the inside of the tubes. This configuration may allow for direct heat exchange between the superconducting wires and a refrigerant, resulting in improvement of heat exchange efficiencies of the superconducting wires.

Disclosed are an oxide superconductor tape and a method of manufacturing the oxide superconductor tape capable of improving the length and characteristics of superconductor tape and obtaining stabilized characteristics across the entire length thereof. A Y-class superconductor tape (10), as an oxide superconductor tape, comprises a tape (13) further comprising a tape-shaped non-oriented metallic substrate (11), and a first buffer layer (sheet layer) (12) that is formed by IBAD upon the tape-shaped non-oriented metallic substrate (11); and a second buffer layer (gap layer) (14), further comprising a lateral face portion (14a) that is extended to the lateral faces of the first buffer layer (sheet layer) (12) upon the tape (13) by RTR RF-magnetron sputtering.

A method for manufacturing a base material 2 for a superconductive conductor which includes: a conductive bed layer forming process of forming a non-oriented bed layer 24 having conductivity on a substrate 10; and a biaxially oriented layer forming process of forming a biaxially oriented layer 26 on the bed layer 24.

A superconducting magnet device is configured to include: a refrigerant circulation flowpath in which a refrigerant (R) circulates; a refrigerator for cooling vapor of the refrigerant (R) in the refrigerant circulation flowpath; a superconducting coil cooled by the circulating refrigerant (R); a protective resistor thermally contacting the superconducting coil and having an internal space (S); a high-boiling-point refrigerant supply section for supplying a high-boiling-point refrigerant having a higher boiling point than the refrigerant (R) and frozen by the refrigerant (R) to the internal space (S) in the protective resistor; and a vacuum insulating container for at least accommodating the refrigerant circulation flowpath, the superconducting coil, and the protective resistor.

Provided are a substrate for a superconducting compound and a method for manufacturing the substrate which can realize the excellent adhesive strength simultaneously with high orientation of copper. An absorbed material on a surface of a copper foil to which rolling is applied at a draft of 90% or more is removed by applying sputter etching to the surface of the copper foil, sputter etching is applied to a nonmagnetic metal sheet, the copper foil and the metal sheet are bonded to each other by applying a pressure to the copper foil and the metal sheet using reduction rolls, crystals of the copper in the copper foil are oriented by heating a laminated body formed by such bonding, copper is diffused into the metal sheet by heating with a copper diffusion distance of 10 nm or more, and a protective layer is laminated to a surface of the copper foil of the laminated body.

Disclosed is a splicing method of two second-generation ReBCO high temperature superconductor coated conductors (2G ReBCO HTS CCs), in which, with stabilizing layers removed from the two strands of 2G ReBCO HTS CCs through chemical wet etching or plasma dry etching, surfaces of the two high temperature superconducting layers are brought into direct contact with each other and heated in a splicing furnace in a vacuum for micro-melting portions of the surfaces of the high temperature superconducting layers to permit inter-diffusion of ReBCO atoms such that the surfaces of the two superconducting layers can be spliced to each other and oxygenation annealing for recovery of superconductivity which was lost during splicing.

A superconducting magnet device and a magnetic resonance imaging system not only avoid the need for costly aluminum alloy formers but also lower quench pressure effectively, have a baffle covering the former and the coil, with a gap between the baffle and the coil.

A tape-shaped superconducting film-forming substrate is disclosed, which includes a film-forming face for forming a laminate including a superconducting layer thereon, a rear face that is a face at a side opposite to the film-forming face, a pair of end faces connected to the film-forming face and the rear face, and a pair of side faces connected to the film-forming face, the rear face, and the pair of end faces, in which each of the pair of side faces includes a spreading face that spreads toward an outer side in an in-plane direction of the film-forming face from an edge part of the film-forming face toward the rear face side. A superconducting wire and a superconducting wire manufacturing method are also disclosed.

An electrochemical finishing system for super conducting radio frequency (SCRF) cavities including a low viscosity electrolyte solution that is free of hydrofluoric acid, an electrode in contact with the electrolyte solution, the SCRF cavity being spaced apart from the electrode and in contact with the electrolyte solution and a power source including a first electrical lead electrically coupled to the electrode and a second electrical lead electrically coupled to the cavity, the power source being configured to pass an electric current between the electrode and the workpiece, wherein the electric current includes anodic pulses and cathodic pulses, and wherein the cathodic pulses are interposed between at least some of the anodic pulses. The SCRF cavity may be vertically oriented during the finishing process.

A superconductive cable which has a cryostat with two concentric metal pipes where the cryostat has at least a first axial section with a first axial spring constant, and at least a second axial section which has a second axial spring constant which at most is 20%, more preferred at most 10%, of the axial spring constant of the first section.

A ceramic substrate includes a substrate body formed of ceramic and having a pair of surfaces each assuming a rectangular shape as viewed in plane, and a metallization layer formed on the surface of the substrate body and adapted to braze a metal frame thereon. A composite material layer is disposed between the surface of the substrate body and the metallization layer and is formed such that a ceramic portion, a metal portion 10m formed of a metal similar to a metal component of the metallization layer or a metal which, together with a metal component of the metallization layer, forms an all proportional solid solution, and a glass portion exist together. The thickness of the composite material layer is thinner than that of the metallization layer. A plating layer is deposited on the surface of the metallization layer.

In a terminal structure of a superconducting cable conductor, a terminal portion of the superconducting cable conductor is connected with a terminal member of a good conductor. The terminal portion includes a superconducting layer disposed on an outer periphery of a central support; and an insulating layer surrounding the superconducting layer. The insulating layer and the superconducting layer are partially removed to expose the central support and the superconducting layer in this order from an end of the superconducting cable conductor. The terminal member includes a metal sleeve which includes a first cylindrical portion whose inner surface is in close contact with an exposed portion of the central support; a second cylindrical portion which is soldered around an exposed portion of the superconducting layer; and a third cylindrical portion into which the insulating layer is inserted.

A device for the high pressure densification of superconducting wire from compacted superconductor material or superconductor precursor powder particles, has four hard metal anvils (5, 6, 7, 8) with a total length (L2) parallel to the superconducting wire, the hard metal anvils borne in external independent pressure blocks (9, 10, 11), which are in turn either fixed or connected to high pressure devices, preferably hydraulic presses. At least one of the hard metal anvils is a free moving anvil (6) having clearances of at least 0.01 mm up to 0.2 mm towards the neighboring hard metal anvils (5, 8), so that no wall friction occurs between the free moving anvil and the neighboring anvils. This allows for high critical current densities Jc at reduced pressure applied to the hard metal anvils.

Provided are a three-phase coaxial superconducting power cable and a structure thereof. A certain space is formed between adjacent superconducting wires of a superconducting layer (disposed at an outer portion) having more superconducting wires among a plurality of superconducting layers, and another wire is disposed in the space, or the superconducting wires of the respective superconducting layers are disposed to have different critical currents. Accordingly, a waste of superconducting wires is prevented, and the optimized three-phase coaxial superconducting power cable is provided.

In order to store excess kinetic energy, an energy storage device and an operating method are described, in which the kinetic energy can be partially converted into electrical energy by a first electric machine using at least two electric machines arranged on a shaft and can be partially converted into additional kinetic energy, such as rotational energy, by a second electric machine. The method for energy storage of excess kinetic energy provides for converting kinetic energy partially into electric energy and partially into additional kinetic energy, such as rotational energy.

A method for producing a superconductive conductor includes: a base material preparation process of preparing a base material having a groove formed on at least one face thereof; a superconducting layer formation process of forming a superconducting layer on a surface of the base material at a side at which the groove is formed; and a cutting process of cutting completely through the base material along the groove.

A cryocooler system and a superconducting magnet apparatus having the cryocooler system include a cryocooler having a cool stage that cools a heat shielding unit and a thermal inertia that thermally contacts the cool stage of the cryocooler and has a high heat capacity. The cryocooler system reduces a temperature-increasing rate in a current lead by using the thermal inertia member when the temperature in the current lead is increased due to heat generated when an electrical current applied to a superconducting coil is ramped-up or ramped-down.

Quantum annealing may include applying and gradually removing disorder terms to qubits of a quantum processor, for example superconducting flux qubits of a superconducting quantum processor. A problem Hamiltonian may be established by applying control signals to the qubits, an evolution Hamiltonian established by applying disorder terms, and annealing by gradually removing the disorder terms. Change in persistent current in the qubits may be compensated. Multipliers may mediate coupling between various qubits and a global signal line, for example by applying respective scaling factors. Two global signal lines may be arranged in an interdigitated pattern to couple to respective qubits of a communicatively coupled pair of qubits. Pairs of qubits may be communicatively isolated and used to measure a response of one another to defined signals.

According to one embodiment, an oxide superconductor includes an oriented superconductor layer and an oxide layer. The oriented superconductor layer contains fluorine at 2.0×1016-5.0×1019 atoms/cc and carbon at 1.0×1018-5.0×1020 atoms/cc. The superconductor layer contains in 90% or more a portion oriented along c-axis with an in-plane orientation degree (Δφ) of 10 degrees or less, and contains a LnBa2Cu3O7-x superconductor material (Ln being yttrium or a lanthanoid except cerium, praseodymium, promethium, and lutetium). The oxide layer is provided in contact with a lower surface of the superconductor layer and oriented with an in-plane orientation degree (Δφ) of 10 degrees or less with respect to one crystal axis of the superconductor layer. Area of a portion of the lower surface of the superconductor layer in contact with the oxide layer is 0.3 or less of area of a region directly below the superconductor layer.