or How to add custom indicators to Dynamic Display measuring HUD By community.cadence.com Published On :: Wed, 23 Oct 2024 20:31:55 GMT I am attempting to use dbGetNeighbor() function inside the dynamic display HUD so that the distance to the next metal on that layer could be viewed. Think of another line in this dynamic table here... My SKILL code is essentially the following: procedure(getNearestNeighborOnMetal(cv) let((direction tmpBoundingBox) direction = internal_function() tmpBoundingBox = dbCreateRect(geGetEditCellView() "tmp" list(hiGetCommandPoint() hiGetCommandPoint())) car(dbGetNeighbor(geGetEditCellView() tmpBoundingBox direction)) )) this returns the distance to the closest metal based on some tests. Next, I try to register this function to work in the Dynamic Display / Info Balloon world by executing odcRegisterCustomFunc() for each and every object type (I know, absurd, but trying to debug) In the dynamic display menu, I toggle the "Custom SKILL Function" check in layoutXL, then hit apply, then OK. After this I find I am unable to view the changes reflected in any info balloons or in the drawing HUD (above) for this wire. I have tried replacing my function with the sample "customFunc" from the odcRegisterCustomFunc() documentation and was still unable to produce any new output. Any help diagnosing the use of this feature would be very much appreciated Full Article
or Virtuoso Fluid Guard Ring Layout error "do_something=nil" By community.cadence.com Published On :: Thu, 24 Oct 2024 07:22:30 GMT Hello, When I draw a Fluid Guard Ring in Virtuoso, the layout is not visible, and instead, "do_something=nil" appears. When I check the details with Q, it shows the same information as a regular NFGR guard ring, and Ctrl+F also displays the instance name, just like with a regular NFGR. Additionally, the Pcells of Fluid Guard Rings from previous projects appear broken. The version I’m currently using is not different from the one used in the past. Even when I access the same version as the one used during the project, the Pcells still appear broken. These two issues are occurring, and I’m not sure what to check. I would greatly appreciate it if you could assist me in resolving this issue. // Reinstalling the PDK resolved the issue! I’m not exactly sure what the problem was, but I suspect there might have been an internal issue with permissions or the PDK path. Full Article
or Refer instances and vias to technology library during importing By community.cadence.com Published On :: Sun, 27 Oct 2024 04:30:15 GMT Hi, My query is regarding importing of layout. After importing, we see that the imported transistor instances and vias are all referring to the library in which they are imported, instead of referring to the technology library. Please let me know how we can refer them to the technology library. Will surely provide more details if my query is unclear. Thanks, Mallikarjun. Full Article
or How to create draw region button like the one used in the Area and Density calculator By community.cadence.com Published On :: Mon, 28 Oct 2024 23:47:16 GMT Hello, I would like to create a button for my form that prompts the user to click on a cellview and draw a rectangle bounding box, exactly like the one used in the Area and Density Calculator. Can someone please help me with this? Thanks! Beto Full Article
or Error ASSEMBLER-1600 when running script with two different MC simulations By community.cadence.com Published On :: Tue, 29 Oct 2024 08:59:49 GMT Hello Community, I have encountered an issue that is a mystery to me and hope somebody could give me a clue about what is happening in Cadence and maybe even a solution? I am running a test scripted in a SKILL file that sequentially opens two different projects with MC analyses and in between I get an error message box and also multiple logs in CIW with exactly the same text. Both projects run a simulation with a call like this: historyName = maeRunSimulation(?session sessionName ?waitUntilDone t) After this the script closes the current project, opens the next project and executes the same line with maeRunSimulation() for the second project. Then immediately this error message happens, and also is logged repeatedly in the CIW window The message box looks like this: The logs I get in CIW: nilhiCancelProgressBox(_axlNetlistCreateProgressBar)nilhiCancelProgressBox(_axlUILoadForm)nilwhen(dwindow('axlDataViewessWindow1) hiMapWindow(dwindow('axlDataViewessWindow1)))twhen(dwindow('axlRunSummaryessWindow1) hiMapWindow(dwindow('axlRunSummaryessWindow1)))tERROR (ASSEMBLER-1600): Cannot find an active session named fnxSession0.You can only modify an ADE Assembler session that is active.Perhaps the session name was misspelled or has not yet been created. Verify the session name matches an existing ADE Assembler session. 1> ERROR (ASSEMBLER-1600): Cannot find an active session named fnxSession0.You can only modify an ADE Assembler session that is active.Perhaps the session name was misspelled or has not yet been created. Verify the session name matches an existing ADE Assembler session. *WARNING* hiDisplayAppDBox: modal dbox 'adexlMessageDialog' is already displayed!ERROR (ASSEMBLER-1600): Cannot find an active session named fnxSession0.You can only modify an ADE Assembler session that is active.Perhaps the session name was misspelled or has not yet been created. Verify the session name matches an existing ADE Assembler session. *WARNING* hiDisplayAppDBox: modal dbox 'adexlMessageDialog' is already displayed!ERROR (ASSEMBLER-1600): Cannot find an active session named fnxSession0.You can only modify an ADE Assembler session that is active.Perhaps the session name was misspelled or has not yet been created. Verify the session name matches an existing ADE Assembler session. Full Article
or Disappearing toolbar or docked menu By community.cadence.com Published On :: Wed, 06 Nov 2024 20:47:05 GMT Disappearing toolbar or docked menu Is there a way for the toolbar or floating menu from disappearing when a cells tab is added to a window? I have created a skill toolbar and it disappeared when I add another cell or tab to a window. The only toolbars that stay are the ones I have defined in the Layout.toolbar file. Do I have to add a trigger to keep the toolbars visible or not disappearing from the window? Cadence version IC23.1-64b.ISR7.27 Paul Full Article
or Destructive form of "cons" - efficiently prepending an item to a procedure's argument which is a list By community.cadence.com Published On :: Tue, 12 Nov 2024 18:20:40 GMT Hello, I was looking to destructively and efficiently modify a list that was passed in as an argument to a procedure, by prepending an item to the list. I noticed that cons lets you do this efficiently, but the operation is non-destructive. Hence this wouldn't work if you are trying to modify a function's list parameter in place. Here is an example of trying to add "0" to the front of a list: procedure( attempt_to_prepend_list(l elem) l = cons(elem l) ) a = list(1 2 3) ==> (1 2 3)attempt_to_prepend_list(a 0)==> (0 1 2 3)a==> (1 2 3) As we can see, the original list is not prepended. Here is a function though which achieves the desired result while being efficient. Namely, the following function does not create any new lists and only uses fast methods like cons, rplacd, and rplaca procedure( prepend_list(l elem) ; cons(car(l) cdr(l)) results in a new list with the car(l) duplicated ; we then replace the cdr of l so that we are now pointing to this new list rplacd(l cons(car(l) cdr(l))) ; we replace the previously duplicated car(l) with the element we want rplaca(l elem) ) a = list(1 2 3) ==> (1 2 3)prepend_list(a 0)==> (0 1 2 3)a==> (0 1 2 3) This works for me, but I find it surprising there is no built-in function to do this. Am I perhaps overlooking something in the documentation? I know that tconc is an efficient and destructive way to append items to the end of a list, but there isn't an equivalent for the front of the list? Full Article
or μWaveRiders: Thermal Analysis for RF Power Applications By community.cadence.com Published On :: Thu, 22 Sep 2022 08:27:00 GMT Thermal analysis with the Cadence Celsius Thermal Solver integrated within the AWR Microwave Office circuit simulator gives designers an understanding of device operating temperatures related to power dissipation. That temperature information can be introduced into an electrothermal model to predict the impact on RF performance.(read more) Full Article CFD RF Simulation featured Circuit simulation AWR Design Environment awr Cadence Celsius Thermal Analysis microwave office electrothermal models thermal solver
or New Training Courses for RF/Microwave Designers Featuring Cadence AWR Software By community.cadence.com Published On :: Mon, 03 Oct 2022 03:00:00 GMT Cadence AWR Design Environment Software Featured in Multiple Training Course Options: Live and Virtual Starting in October(read more) Full Article featured AWR Design Environment microwave design
or μWaveRiders: Scoring Goals with the Latest AWR Design Environment Optimizer By community.cadence.com Published On :: Mon, 21 Nov 2022 09:55:00 GMT AWR V22.1 software introduces the Pointer-Hybrid optimization method which uses a combination of optimization methods, switching back and forth between methods to efficiently find the lowest optimization error function cost. The optimization algorithm automatically determines when to switch to a different optimization method, making this a superior method over manual selection of algorithms. This method is particularly robust in regards to finding the global minima without getting stuck in a local minima well.(read more) Full Article featured AWR Design Environment Pointer-Hybrid optimizer RF design microwave office global minima Optimization cost Optimizer goals Optimizer methods
or Knowledge Booster Training Bytes - Working with Data Sets in Microwave Office By community.cadence.com Published On :: Fri, 06 Jan 2023 19:39:00 GMT Data sets are a powerful and easy-to-use feature in Microwave Office. Data can be effortlessly be swapped in graphs, and circuit schematics.(read more) Full Article RF Simulation AWR Design Environment awr AWR customization AWR Microwave Office microwave office
or Training Webinar: Microwave Office: An Integrated Environment for RF and Microwave Design By community.cadence.com Published On :: Thu, 07 Sep 2023 06:08:00 GMT A recording of a training webinar on Microwave Office is available. Topics show the design environment, with special emphasis placed on electromagnetic (EM) simulation. Normal 0 false false false EN-US JA X-NONE ...(read more) Full Article
or read from text file with two values and represent that as voltage signals on two different port a and b By community.cadence.com Published On :: Fri, 24 Feb 2023 00:33:01 GMT i want to read from text file two values on two ports , i wrote that code, and i have that error that shown in the image below . and also the data in text file is shown as screenshot module read_file (a,b); electrical a,b;integer in_file_0,data_value, valid, count0,int_value; analog begin @(initial_step) begin in_file_0 = $fopen("/home/hh1667/ee610/my_library/read_file/data2.txt","r"); valid = $fscanf (in_file_0, "%b,%b" ,int_value,count0); end V(a) <+ int_value; V(b) <+ count0; end endmodule Full Article
or In Simvision, how do I change the waveform font size of the signal names? By community.cadence.com Published On :: Mon, 27 Mar 2023 09:01:44 GMT Hi Cadence, I use simvision 20.09-s007 but my computer screen resolution is very high. As a result, the texts are too small. In ~/.simvision/Xdefaults I changed that number to 16, from 12. But the signal names in the waveform traces don't reflect the change. Simvision*Font: -adobe-helvetica-medium-r-normal--16-*-*-*-*-*-*-* Other .font changes seem to reflect on the simvision correctly, except the signal names. How do I fix that? I dont mind a single variable to change all the texts fonts to 16. Thank you! PS: I found the answer with another post. I change Preference/Waveform/Display/Signal Height. Full Article
or Stream in gds to virtuoso from directory other than where cds.lib exists By community.cadence.com Published On :: Fri, 31 Mar 2023 16:35:39 GMT I am scripting gds streamin using 'strmin', which works fine so far. But, as it apparently doesn't have an option to specify where the cds.lib file is, I have to run it from the directory where the cds.lib file is, or I guess I could create a dummy one to source that one. Is there a way to tell strmin where the cds.lib file is? Full Article
or Request information on Tools By community.cadence.com Published On :: Wed, 02 Aug 2023 05:48:04 GMT We are looking for suitable tools that could be used for RTL design, IP-XACT based integration (third party IP) and RTL design verification ( SV / UVM based methodology). Request to share details on the different Cadence tools that is most suitable for these activities. Full Article
or Conformal LEC can't finish at analyze abort step. How do I proceed? By community.cadence.com Published On :: Mon, 07 Aug 2023 02:19:35 GMT Hi Cadence & forumers, I am running a conformal LEC with a flattened netlist against RTL. The run hang for 5 days at the "analyze abort" step which is automatically launched by the compare. The netlist is flattened at some levels so hierarchical flow which I tried didn't help much. The flattened/highly optimized netlist is from customer and the ultimate goal. How shall I proceed now? On the a side note, a test run with a hierarchical netlist from a simple DC "compile -map_effort medium" command finished after 1 day or so. Thank you! // Command: vpx compare -verbose -ABORT_Print -NONEQ_Print -TIMEstamp// Starting multithreaded comparison ... Comparing 241112 points in parallel. // Multithreading Overhead: 38% Gates: 8501606/6168138// Multithreaded processing completed. ================================================================================Compared points PO DFF DLAT BBOX CUT Total --------------------------------------------------------------------------------Equivalent 1025 241638 30 75 21 242789 --------------------------------------------------------------------------------Abort 0 124 0 0 0 124 ================================================================================Compare results of instance/output/pin equivalences and/or sequential merge ================================================================================Compared points DFF Total --------------------------------------------------------------------------------Equivalent 204 204 ================================================================================// Warning: 512 DFFs/DLATs have 1 disabled clock port: skipped data cone comparison// Resolving aborts by analyze abort... Full Article
or Detailed waveform dumping for selected waveform By community.cadence.com Published On :: Wed, 23 Aug 2023 15:54:14 GMT I'm currently trying to explore the verilog simulation option in cadence. One thing that comes to my mind that if there exists a way in cadence workflow to dump selected register/wire's waveform during the simulation. Are there any additional tools needed apart from xcelium, is there a tutorial or specific training course for this aspect. I glance through Xcelium Simulator Course Version 22.09, but it seems not having related context. I know in Synopsys's workflow, it can be realized using verdi & fsdb in the command line as follows: if (inst.CTRL_STATE==STATE_START_TO_DUMP) $fsdbDumpvars(0, inst_1.reg_0); end Thanks in advance! Full Article
or How to generate "Sheet Name" column in a pin report? By community.cadence.com Published On :: Wed, 08 Nov 2023 03:52:26 GMT Hi everyone, Is there any method to generate "Sheet" column for a pin report like table below? The column "Name.Pin" & "Signal" can be generated easily, but I have no idea to generate the column of "Sheet Name". The software using here are Allegro Design Entry HDL, OrCAD Capture and Allegro PCB Editor. Can these 3 software generate "Sheet Name" data? Name.Pin Signal Sheet Name C1_1.1 N301321 SITE1_1 C1_1.2 GND_ANA_1 SITE1_1 C1_2.1 N180243 SITE2_1 C1_2.2 GND_ANA_2 SITE2_1 Thank you. Full Article
or How to identify old Orcad Schematic entry version By community.cadence.com Published On :: Fri, 19 Jan 2024 10:49:20 GMT Good morning,I dug up an old project from 2005 and I should open the schematic to check some things.This is the schematic of a XILINX XC95108-pq160 CPLD which the XILINX ISE 6.1 software then translated and compiled, to generate a JEDEC file to burn CPLD.My problem is that I can't open schematics with the versions of Orcad Schematic Entry that I have.Can anyone help me understand which version of Orcad Schematic Entry I need to install to see these files?I shared the files on:drive.google.com/.../viewThank you very much Full Article
or Merge several worklibs By community.cadence.com Published On :: Mon, 19 Feb 2024 15:58:11 GMT Hi, I find there is a similar question 10 years ago and the answer is out of date, so I come to ask again. I have compiled 2 different blocks in 2 different paths, using basic xrun -f xxxx.f, generated 2 xcelium.d folder. Then I have to compile another block based on these 2, how can I link these 2 generated libraries while compiling the 3rd one? Thanks Full Article
or Regarding the loading of waveform signals in the waveform windown using the tcl command By community.cadence.com Published On :: Mon, 26 Feb 2024 09:26:52 GMT Hello, I am trying to load some of the signals of the design saved in the signals.svwf to the waveform windown via the tcl file, I am using the following commands but nothing works, Can you please help -submit waveform loadsignals -using "Waveform 2" FB1.svwf but it gives me the below error -submit waveform new -reuse -name Waveforms Full Article
or Error orprobe3086 By community.cadence.com Published On :: Tue, 12 Mar 2024 09:27:56 GMT I got "no simulation data for marker" for each A<B, A=B and A>B markers. Simulation output doesn't show these outputs but the inputs shown. How can I solve this error? Full Article
or Conformal CEC checking By community.cadence.com Published On :: Tue, 19 Mar 2024 21:04:55 GMT Below is showing my Master.v ******************************************************************************************************************************************************************************************************************** ///////ALUmodule ALU ( input [31:0] A,B, input[3:0] alu_control, output reg [31:0] alu_result, output reg zero_flag); always @(*) begin // Operating based on control input case(alu_control) 4'b0001: alu_result = A+B; 4'b0010: alu_result = A-B; 4'b0011: alu_result = A*B; 4'b0100: alu_result = A|B; 4'b0101: alu_result = A&B; 4'b0110: alu_result = A^B; 4'b0111: alu_result = ~B; 4'b1000: alu_result = A<<B; 4'b1001: alu_result = A>>B; 4'b1010: begin if(A<B) alu_result = 1; else alu_result = 0; end default: alu_result = A+B; endcase // Setting Zero_flag if ALU_result is zero if (alu_result) zero_flag = 1'b1; else zero_flag = 1'b0; endendmodule/////CONTROL UNIT/* Control unit controls takes opcode, funct7, funct3 of the instruction code to determineand control regwrite in IFU, alu control in ALU to execute proper instruction*//* Control unit controls takes opcode, funct7, funct3 of the instruction code to determineand control regwrite in IFU, alu control in ALU to execute proper instruction*/module CONTROL( input [4:0] opcode, output reg [3:0] alu_control, output reg regwrite_control,memread_control,memwrite_control); always @(opcode) begin case(opcode) 5'b00001: begin alu_control=4'b0001; //add regwrite_control=1; memread_control=0; memwrite_control=0; end 5'b00010: begin alu_control=4'b0010; ///sub regwrite_control=1; memread_control=0; memwrite_control=0; end 5'b00011: begin alu_control=4'b0011; //mul regwrite_control=0; memread_control=0; memwrite_control=1; end 5'b00100: begin alu_control=4'b0100; ///OR regwrite_control=0; memread_control=0; memwrite_control=1; end 5'b00101: begin alu_control=4'b0101; ///AND regwrite_control=1; memread_control=0; memwrite_control=0; end 5'b00110: begin alu_control=4'b0110; ///XOR regwrite_control=0; memread_control=0; memwrite_control=1; end 5'b00111: begin alu_control=4'b0111; ///NOT regwrite_control=0; memread_control=0; memwrite_control=1; end 5'b01000: begin alu_control=4'b1000; //SL regwrite_control=1; memread_control=1; memwrite_control=0; end 5'b11001: begin alu_control=4'b1001; //SR regwrite_control=1; memread_control=1; memwrite_control=0; end 5'b01010: begin alu_control=4'b1010; //COMPARE regwrite_control=1; memread_control=1; memwrite_control=0; end //5'b11010: begin ALU_control=4'b0000; //SW //regwrite_control=1; memread_control=0; memwrite_control=0; //end //5'b01010: begin ALU_control=4'bxxxx; //LW //regwrite_control=0; memread_control=0; memwrite_control=1; //end default : begin alu_control = 4'b0001; regwrite_control=1; memread_control=0; memwrite_control=0; end endcase endendmodule//////DATA MEMORYmodule Data_Mem(input clock, rd_mem_enable, wr_mem_enable,input [11:0] address,input [31:0] datawrite_to_mem,output reg [31:0] dataread_from_mem );reg [31:0] Data_Memory[8:0];initial begin Data_Memory[0] = 32'hFFFFFFFF; Data_Memory[1] = 32'h00000001; Data_Memory[2] = 32'h00000005; Data_Memory[3] = 32'h00000003; Data_Memory[4] = 32'h00000004; Data_Memory[5] = 32'h00000000; Data_Memory[6] = 32'hFFFFFFFF; Data_Memory[7] = 32'h00000000; //Data_Memory[8] = 32'h00000008; //Data_Memory[9] = 32'h00000009; //Data_Memory[10] = 32'h0000000A; //Data_Memory[11] = 32'h0000000B; //Data_Memory[12] = 32'h0000000C; //Data_Memory[13] = 32'h0000000D; //Data_Memory[14] = 32'h0000000E; //Data_Memory[15] = 32'h0000000F; //Data_Memory[16] = 32'h00000010; //Data_Memory[17] = 32'h00000011; //Data_Memory[18] = 32'h00000012; //Data_Memory[19] = 32'h00000013; //Data_Memory[20] = 32'h00000014; //Data_Memory[21] = 32'h00000015; //Data_Memory[22] = 32'h00000016; //Data_Memory[23] = 32'h00000017; //Data_Memory[24] = 32'h00000018; //Data_Memory[25] = 32'h00000019; //Data_Memory[26] = 32'h0000001A; //Data_Memory[27] = 32'h0000001B; //Data_Memory[28] = 32'h0000001C; //Data_Memory[29] = 32'h0000001D; //Data_Memory[30] = 32'h0000001E; Data_Memory[31] = 32'h0000001F; end always@(posedge clock) begin if(wr_mem_enable) begin Data_Memory[address] <= datawrite_to_mem; end else if(rd_mem_enable) begin dataread_from_mem <= Data_Memory[address]; end else begin dataread_from_mem <= 32'h00000000; end endendmodule /////INST MEM/* */module INST_MEM( input [31:0] PC, input reset, output [31:0] Instruction_Code); reg [7:0] Memory [43:0]; // Byte addressable memory with 32 locations assign Instruction_Code = {Memory[PC+3],Memory[PC+2],Memory[PC+1],Memory[PC]}; initial begin // Setting 32-bit instruction: add t1, s0,s1 => 0x00940333 Memory[3] = 8'b0000_0000; Memory[2] = 8'b0000_0001; Memory[1] = 8'b0111_1100; Memory[0] = 8'b0000_0001; // Setting 32-bit instruction: sub t2, s2, s3 => 0x413903b3 Memory[7] = 8'b0000_0000; Memory[6] = 8'b0000_0110; Memory[5] = 8'b1000_1111; Memory[4] = 8'b1110_0010; // Setting 32-bit instruction: mul t0, s4, s5 => 0x035a02b3 Memory[11] = 8'b0000_0000; Memory[10] = 8'b0000_0101; Memory[9] = 8'b0111_1100; Memory[8] = 8'b0000_0011; // Setting 32-bit instruction: or t3, s6, s7 => 0x017b4e33 Memory[15] = 8'b1111_1111; Memory[14] = 8'b1111_0100; Memory[13] = 8'b1010_0000; Memory[12] = 8'b1010_0100; // Setting 32-bit instruction: and Memory[19] = 8'b0000_0000; Memory[18] = 8'b0010_1001; Memory[17] = 8'b0001_1101; Memory[16] = 8'b0010_0101; // Setting 32-bit instruction: xor Memory[23] = 8'b0000_0000; Memory[22] = 8'b0001_1000; Memory[21] = 8'b0000_1101; Memory[20] = 8'b0110_0110; // Setting 32-bit instruction: not Memory[27] = 8'b0000_0000; Memory[26] = 8'b0010_1001; Memory[25] = 8'b0011_1101; Memory[24] = 8'b1100_0111; // Setting 32-bit instruction: shift left Memory[31] = 8'b0000_0000; Memory[30] = 8'b0101_0111; Memory[29] = 8'b1100_0110; Memory[28] = 8'b0000_1000; // Setting 32-bit instruction: shift right Memory[35] = 8'b0000_0000; Memory[34] = 8'b0110_1010; Memory[33] = 8'b1101_0010; Memory[32] = 8'b0111_1001; /// Setting 32-bit instruction: Campare Memory[39] = 8'b0000_0000; Memory[38] = 8'b0111_1010; Memory[37] = 8'b1101_0010; Memory[36] = 8'b0110_1010; /// Setting 32-bit instruction: Memory[43] = 8'b0000_0000; Memory[42] = 8'b0111_0111; Memory[41] = 8'b1101_0010; Memory[40] = 8'b0111_0010; end endmodule//IFU/*The instruction fetch unit has clock and reset pins as input and 32-bit instruction code as output.Internally the block has Instruction Memory, Program Counter(P.C) and an adder to increment counter by 4, on every positive clock edge.*/module IFU( input clock,reset, output [31:0] Instruction_Code);reg [31:0] PC = 32'b0; // 32-bit program counter is initialized to zero always @(posedge clock, posedge reset) begin if(reset == 1) //If reset is one, clear the program counter PC <= 0; else PC <= PC+4; // Increment program counter on positive clock edge end // Initializing the instruction memory block INST_MEM instr_mem(.PC(PC),.reset(reset),.Instruction_Code(Instruction_Code));endmodule///MUXmodule Mux_2X1 ( input mem_rd_select, // rd_mem_enable input wire [31:0] dataread_from_mem, regdata2, output reg [31:0] mux_out);always @(mem_rd_select or dataread_from_mem or regdata2) begin if (mem_rd_select == 1) mux_out <= dataread_from_mem ; else mux_out <= regdata2; endendmodule//DFlipFlopmodule DFlipFlop(D,clock,Q);input D; // Data input input clock; // clock input output reg Q; // output Q always @(posedge clock) begin Q <= D; end endmodule ///DATA pathmodule DATAPATH( input [4:0]Read_reg_add1, input [4:0]Read_reg_add2, input [4:0]Reg_write_add, input [3:0]Alu_control, input [11:0]Address, input Wr_reg_enable,Wr_mem_enable,Rd_mem_enable, input clock, input reset, output OUTPUT ); // Declaring internal wires that carry data wire zero_flag; wire [31:0]Dataread_from_mem; wire [31:0]read_data1; wire [31:0]read_data2; wire [31:0]Mux_out; wire [31:0]Alu_result; //wire [31:0]datawrite_to_reg; // Instantiating the register file REG_FILE reg_file_module(.reg_read_add1(Read_reg_add1),.reg_read_add2(Read_reg_add2),.reg_write_add(Reg_write_add),.datawrite_to_reg(Alu_result),.read_data1(read_data1),.read_data2(read_data2),.wr_reg_enable(Wr_reg_enable),.clock(clock),.reset(reset)); // Instanting ALU ALU alu_module(.A(read_data1), .B(Mux_out), .alu_control(Alu_control), .alu_result(Alu_result), .zero_flag(zero_flag)); //Mux Mux_2X1 mux(.mem_rd_select(Rd_mem_enable),.dataread_from_mem(Dataread_from_mem),.regdata2(read_data2),.mux_out(Mux_out)); //Data Memory Data_Mem DM(.clock(clock),.rd_mem_enable(Rd_mem_enable),.wr_mem_enable(Wr_mem_enable),.address(Address),.datawrite_to_mem(Alu_result),.dataread_from_mem(Dataread_from_mem)); // Dflipflop DFlipFlop DF (.D(zero_flag), .Q(OUTPUT),.clock(clock));endmodule/*A register file can read two registers and write in to one register. The RISC V register file contains total of 32 registers each of size 32-bit. Hence 5-bits are used to specify the register numbers that are to be read or written. *//*Register Read: Register file always outputs the contents of the register corresponding to read register numbers specified. Reading a register is not dependent on any other signals.Register Write: Register writes are controlled by a control signal RegWrite. Additionally the register file has a clock signal. The write should happen if RegWrite signal is made 1 and if there is positive edge of clock. */module REG_FILE( input [4:0] reg_read_add1, input [4:0] reg_read_add2, input [4:0] reg_write_add, input [31:0] datawrite_to_reg, output [31:0] read_data1, output [31:0] read_data2, input wr_reg_enable, input clock, input reset); reg [31:0] reg_memory [31:0]; // 32 memory locations each 32 bits wide initial begin reg_memory[0] = 32'h00000000; reg_memory[1] = 32'hFFFFFFFF; reg_memory[2] = 32'h00000002; reg_memory[3] = 32'hFFFFFFFF; reg_memory[4] = 32'h00000004; reg_memory[5] = 32'h01010101; reg_memory[6] = 32'h00000006; reg_memory[7] = 32'h00000000; reg_memory[8] = 32'h10101010; reg_memory[9] = 32'h00000009; reg_memory[10] = 32'h0000000A; reg_memory[11] = 32'h0000000B; reg_memory[12] = 32'h0000000C; reg_memory[13] = 32'h0000000D; reg_memory[14] = 32'h0000000E; reg_memory[15] = 32'h0000000F; reg_memory[16] = 32'h00000010; reg_memory[17] = 32'h00000011; reg_memory[18] = 32'h00000012; reg_memory[19] = 32'h00000013; reg_memory[20] = 32'h00000014; reg_memory[21] = 32'h00000015; //reg_memory[22] = 32'h00000016; //reg_memory[23] = 32'h00000017; //reg_memory[24] = 32'h00000018; //reg_memory[25] = 32'h00000019; //reg_memory[26] = 32'h0000001A; //reg_memory[27] = 32'h0000001B; //reg_memory[28] = 32'h0000001C; //reg_memory[29] = 32'h0000001D; //reg_memory[30] = 32'h0000001E; reg_memory[31] = 32'hFFFFFFFF; end // The register file will always output the vaules corresponding to read register numbers // It is independent of any other signal assign read_data1 = reg_memory[reg_read_add1]; assign read_data2 = reg_memory[reg_read_add2]; // If clock edge is positive and regwrite is 1, we write data to specified register always @(posedge clock) begin if (wr_reg_enable) begin reg_memory[reg_write_add] = datawrite_to_reg; end else reg_memory[reg_write_add] = 32'h00000000; endendmodule/////PROCESSORmodule PROCESSOR( input clock, input reset, output Output); wire [31:0] instruction_Code; wire [3:0] ALu_control; wire WR_reg_enable; wire WR_mem_enable; wire RD_mem_enable; IFU IFU_module(.clock(clock), .reset(reset), .Instruction_Code(instruction_Code)); CONTROL control_module(.opcode(instruction_Code[4:0]),.alu_control(ALu_control),.regwrite_control(WR_reg_enable),.memread_control(RD_mem_enable),.memwrite_control(WR_mem_enable)); DATAPATH datapath_module(.Wr_mem_enable(WR_mem_enable),.Rd_mem_enable(RD_mem_enable),.Read_reg_add1(instruction_Code[9:5]),.Read_reg_add2(instruction_Code[14:10]),.Reg_write_add(instruction_Code[19:15]),.Address(instruction_Code[31:20]),.Alu_control(ALu_control),.Wr_reg_enable(WR_reg_enable), .clock(clock), .reset(reset), .OUTPUT(Output));endmodule**********************************************************************************************************************************************************Below is my Synthesis.tcl file for genus synthesis ******************** set_attribute lib_search_path "/home/sameer23185/Desktop/VDF_PROJECT/lib"set_attribute hdl_search_path "/home/sameer23185/Desktop/VDF_PROJECT"set_attribute library "/home/sameer23185/Desktop/VDF_PROJECT/lib/90/fast.lib"read_hdl Master.velaborateread_sdc Min_area.sdcset_attribute hdl_preserve_unused_register trueset_attribute delete_unloaded_seqs falseset_attribute optimize_constant_0_flops falseset_attribute optimize_constant_1_flops falseset_attribute optimize_constant_latches falseset_attribute optimize_constant_feedback_seqs false#set_attribute prune_unsued_logic falsesynthesize -to_mapped -effort mediumwrite_hdl > report/HDL_min_Netlist.vwrite_sdc > report/constraints.sdc write_script > report/synthesis.greport_timing > report/synthesis_timing_report.repreport_power > report/synthesis_power_report.repreport_gates > report/synthesis_cell_report.repreport_area > report/synthesis_area_report.repgui_show **********************************************WHEN I COMPARING MY GOLDEN.V WITH HDL_min_Netlist.v during conformal , I got these non-equivalent point for every reg memory and for every data memory. I don't know what to do with these non-equivalent point. I've been stuck here for the past four days. Please help me in this and how can I remove this non- equivalent point , since I am new to this I really don't know what to do. Full Article
or how to tell conformal to ignore certain combination of input By community.cadence.com Published On :: Thu, 04 Apr 2024 10:35:38 GMT hi How can I tell the LEC tool to ignore a combination of Primary input bus in both Golden and revised. For example in both Golden and revised there is input [3:0] data_in I want LEC not to check the case that data_in[3:0] == 4'b1000 Full Article
or which tools support Linting for early stages of Digital Design flow? By community.cadence.com Published On :: Thu, 03 Oct 2024 19:08:53 GMT I am trying to understand the Linting process. I know that mainly JasperGold is the tool for this purpose. Though I think JasperGold is more suited for later stages of the design. As a RTL Design Engineer, I want to make sure that if another tool has the capability of doing Linting earlier in the flow. for example, does Xcelium, Genus or Confomal support linting. I have seen some contradicting information online regarding this topic, though I can't find anything related to Linting on any of these tools. Thanks Full Article
or Asking for a software suggestion. By community.cadence.com Published On :: Tue, 15 Oct 2024 23:05:41 GMT Hi. I'm a very new learner on Cadence. I want to synthesis my logic design for the maximum, minimum and an average results of delay, power dissipation and area under varying multiple inputs of different data. The different data will be exported from other software results. I'm lost on the steps/processes I should do. Could anyone suggest me on which software and/or function or scripts I should use to achieve these results? Full Article
or Quest for Bugs – The Constrained-Random Predicament By community.cadence.com Published On :: Tue, 14 Jun 2022 14:54:00 GMT Optimize Regression Suite, Accelerate Coverage Closure, and Increase hit count of rare bins using Xcelium Machine Learning. It is easy to use and has no learning curve for existing Xcelium customers. Xcelium Machine Learning Technology helps you discover hidden bugs when used early in your design verification cycle.(read more) Full Article compression throughput machine learning Hard to Hit Bin Coverage Closure Regression simulation
or Data Integrity for JEDEC DRAM Memories By community.cadence.com Published On :: Wed, 06 Jul 2022 16:58:00 GMT With the DRAM fabrication advancing from 1x to 1y to 1z and further to 1a, 1b and 1c nodes along with the DRAM device speeds going up to 8533 for Lpddr5/8800 for DDR5, Data integrity is becoming a really important issue that the OEMs and other users have to consider as part of the system that relies on the correctness of data being stored in the DRAMs for system to work as designed. It’s a complicated problem that requires multiple ways to deal with it. Traditionally one of the main approaches to deal with data errors is to rely on the ECC. ECC requires additional memory storage in which the ECC codes will calculated and stored at the time of memory write to DRAM. These codes will be read back along with the memory data during to the reads and checked against the data to make sure that there are no errors. Typical ECC schemes use Hamming code that provide for single bit error correction and double bit error detection per burst. Also, while several of previous generation of DRAM required Host to keep aside system memory for ECC storage latest DRAMs like Lpddr5 and DDR5 support on die ECC as part of the normal DRAM function that can be enabled using mode registers. DDR5 further requires Host to run through an ECC Error Check and Scrub (ECS) cycle on an average every tECSint time (Average Periodic ECS Interval) to prevent data errors. Not meeting the DRAM Refresh requirement is a major reason that can lead to loss of data. This could be challenging as the PVT variation can cause the refresh requirement to change over time. Putting the DRAM in Self Refresh mode can help off-loading Refresh tracking responsibilities to DRAM but may prevent Host to do other scheduling optimizations and should be carefully considered. Some of the other things that can affect the DRAM data are Row hammer where same or adjacent rows are activated again and again leading to loss or changing of data contents in the rows that has not being addressed. Latest DRAMs like Lpddr5/Ddr5 support Refresh Management (including DRFM and ARFM) that allows the Host to compensate for these problems by issuing dedicated RFM commands helping DRAMs deals with potential Data loss issues arising out of Row hammer attacks. Device temperature is another important factor that the Host needs to be aware of and if the application requires DRAM to operate at elevated temperature. The user needs to check with DRAM Vendor on the temperature range that DRAM can still operate. Data integrity at thresholds greater than certain temperature is not assured regardless of refresh rate unless DRAM is manufactured to withstand that. Loss of power to DRAM will cause DRAM to lose all its contents. If this is a real concern for the system designer, they should consider using NVDIMM-N devices which has an onchip controller and a power source which is just enough to allow the DRAM contents to be copied into a backup non-volatile memory before power is lost. When the power is stored back, the stored memory contents in the non-volatile memory will be written back to the DRAM and system can continue to operate as it was before the power loss event occurred. For transmissions and manufacturing errors DRAMs support additional features like CRC, DFE, Pre-Emphasis and PPR which will be covered in the next blog. Cadence MMAV VIPs for DDR5/DDR5 DIMM and LPDDR5 are compressive VIP solutions and supports all of the above-listed Data integrity features including support for ECC error injection and SBE correction/DBE detection to assist with the verification challenges dealing with data integrity issues. More information on Cadence DDR5/LPDDR5 VIP is available at Cadence VIP Memory Models Website. Shyam Full Article Verification IP ddr5 Memory DDR5 DIMM VIP JEDEC DRAM lpddr5 data integrity NVDIMM verification
or Cadence in Collaboration with Arm Ensures the Software Just Works By community.cadence.com Published On :: Tue, 12 Jul 2022 01:02:00 GMT The increase in compute and data-intensive applications and the need for lower power consumption have resulted in a rapidly growing number of Arm-based devices in various market segments; this requires fast time to market (TTM) and support for off-t...(read more) Full Article SBSA Emulation Pre Silicon compliance Testing Arm SystemReady
or Jasper C2RTL App for Datapath Verification By community.cadence.com Published On :: Wed, 13 Jul 2022 02:31:00 GMT Ensuring that the RTL designs correctly implement the C++ algorithmic intent in every circumstance is difficult to achieve with conventional verification. Learn more how Jasper C2RTL App helps to perform equivalence checking with 100x performance improvement(read more) Full Article Datapath Verification c2rtl Jasper C2RTL Equivalence Checking
or Stay Ahead of Competition with Real-Time Cross-Team Collaborations By community.cadence.com Published On :: Tue, 26 Jul 2022 05:21:00 GMT To stay ahead in competition in chip design real-time collaborations ensure traceability, speedy innovations at reduced the cost.(read more) Full Article collaboration Palladium verification management Traceability vManager
or Coalesce Xcelium Apps to Maximize Performance by 10X and Catch More Bugs By community.cadence.com Published On :: Tue, 02 Aug 2022 04:30:00 GMT Xcelium Simulator has been in the industry for years and is the leading high-performance simulation platform. As designs are getting more and more complex and verification is taking longer than ever, the need of the hour is plug-and-play apps that ar...(read more) Full Article performance SoC apps xcelium simulation verification
or JEDEC UFS 4.0 for Highest Flash Performance By community.cadence.com Published On :: Thu, 11 Aug 2022 12:30:00 GMT Speed increase requirements keep on flowing by in all the domains surrounding us. The same applies to memory storage too. Earlier mobile devices used eMMC based flash storage, which was a significantly slower technology. With increased SoC processing speed, pairing it with slow eMMC storage was becoming a bottleneck. That is when modern storage technology Universal Flash Storage (UFS) started to gain popularity. UFS is a simple and high-performance mass storage device with a serial interface. It is primarily used in mobile systems between host processing and mass storage memory devices. Another important reason for the usage of UFS in mobile systems like smartphones and tablets is minimum power consumption. To achieve the highest performance and most power-efficient data transport, JEDEC UFS works in collaboration with industry-leading specifications from the MIPI® Alliance to form its Interconnect Layer. MIPI UniPro is used as a transport layer, and MIPI MPHY is used as a physical layer with the serial DpDn interface. UFS 4.0 specification is the latest specification from JEDEC, which leverages UniPro 2.0 and MPHY 5.0 specification standards to achieve the following major improvements: Enables up to 4200 Mbps read/write traffic with MPHY 5.0, allowing 23.29 Gbps data rate. High Speed Link Startup, along with Out of Order Data Transfer and BARRIER Command, were introduced to improve system latencies. Data security is enhanced with Advanced RPMB. Advance RPMB also uses the EHS field of the header, which reduces the number of commands required compared to normal RPMB, increasing the bandwidth. Enhanced Device Error History was introduced to ease system integration. File Based Optimization (FBO) was introduced for performance enhancement. Along with many major enhancements, UFS 4.0 also maintains backward compatibility with UFS 3.0 and UFS 3.1. JEDEC has just announced the UFS 4.0 specification release, quoting Cadence support as a constant contributor in the JEDEC UFS Task Group, actively participating in these specifications development. With the availability of the Cadence Verification IP for JEDEC UFS 4.0, MIPI MPHY 5.0 and MIPI UniPro 2.0, early adopters can start working with the provisional specification immediately, ensuring compliance with the standard and achieving the fastest path to IP and SoC verification closure. More information on Cadence VIP is available at the Cadence VIP Website. Yeshavanth B N Full Article Verification IP Memory UniPro MIPI Alliance IoT VIP JEDEC UFS storage MPHY
or TSN-PTP: A Real-Time Network Clock Synchronizing Protocol By community.cadence.com Published On :: Mon, 12 Sep 2022 06:45:00 GMT In a network containing multiple nodes, the need for synchronization between the various nodes is not just instrumental but also a complicated and highly complex process. This process becomes even more tricky if we synchronize the clocks between the Manager and the Peripheral. As we know, in a real-time network, some of the nodes would behave like Managers while some would be a Peripheral. If we must make the communication process smooth, then the local clocks of these nodes must be synchronized. The problem with this synchronization is that we have the clock running in the Manager as well. If we send the value of the Manager clock to the Peripheral, the synchronization doesn’t happen as we have a propagation delay of the messages, along with the propagation delay of the electronic circuits of Manager and the Peripheral. The cherry on the cake is that these electronic circuit propagation delays are not random and remain constant, so we can add a time offset to it to match the clock. To tackle this challenge, IEEE has come up with a protocol named “Precision Timing Protocol.” Operation of PTP: To synchronize the clocks, a Sync message is sent by the Manager to the Peripheral, which then timestamps the receiving time of the same. Following this, a ‘Follow up’ message is issued by the Manager stating the timestamp at which the Sync message was sent. The Peripheral then finds the difference between the two values and adds this to its current time. After this, the time difference between the Manager and the Peripheral narrows down to only the propagation delay of the messages. To overcome this, the Peripheral issues a ‘Delay Request’ to the Manager, and the Manager, in turn, issues a ‘Delay Response.’ Both these messages have the timestamp of when they were issued. The time at which they are received is then noted. Since two messages are sent, one from the Peripheral and the other from the Manager, there are two propagation delays. Then half of this value is our propagation delay. The Peripheral then adds this propagation delay to its clock, and hence the clock gets synchronized. Advantages of PTP: It provides accurate time stamping. It is a well-known clock synchronization protocol. It provides intensified security inside the premises. It provides the possibility of setting coordinated actions and synchronized communication. There are various versions of PTP that have been developed over time, namely PTPv1, PTPv2, PTPv2_1, and the latest PTP-AS. Cadence Verification IP for Ethernet is available to support the newer version of PTP, allowing simulation of the device for efficient IP, SoC, and system-level design verification. Semiconductor companies can start using it to fully verify their controller design and achieve functional verification closure on it within no time. Full Article Verification IP uvm 5G Network Ethernet VIP Functional Verification Cadence VIP portfolio VIP Automotive Ethernet Ethernet TSN PTP precision timing protocol verification
or BoardSurfers: Optimizing RF Routing and Impedance Using Allegro X PCB Editor By community.cadence.com Published On :: Thu, 18 Jul 2024 21:15:00 GMT Achieving optimal power transfer in RF PCBs hinges on meticulously routed traces that meet specific impedance requirements. Impedance matching is essential to ensure that traces have the same impedance to prevent signal reflection and inefficient pow...(read more) Full Article RF PCB Routing Allegro X PCB Editor BoardSurfers RF design PCB design shapes allegro x
or IC Packagers: Workflows That Work for You By community.cadence.com Published On :: Fri, 19 Jul 2024 09:07:00 GMT New IC packaging workflows in Cadence Allegro X layout tools allow you to follow a guided path from starting a design through final manufacturing. The path is there to ensure that you don’t miss steps and perform actions in the optimal order. W...(read more) Full Article IC Packaging and SiP Design IC Packaging Workflows Allegro X PCB Editor Allegro X Advanced Package Designer APD PCB design 23.1 allegro x SKILL
or BoardSurfers: Some Wisdom from Designing for a High-Volume Production OEM By community.cadence.com Published On :: Wed, 21 Aug 2024 05:19:00 GMT At what stage in the design cycle do you start to think about the PCB material costs? What about the costs to assemble the PCB? Once a design becomes successful, should you then redesign it to achieve a scalable product? Placing components and routi...(read more) Full Article Allegro X PCB Editor BoardSurfers Allegro X Advanced Package Designer SPB PCB Editor PCB design allegro x Allegro
or OrCAD X – The Anytime Anywhere PCB Design Platform By community.cadence.com Published On :: Mon, 26 Aug 2024 10:08:00 GMT OrCAD X is the next-generation integrated PCB design platform. It brings to you a powerful cloud-enabled design solution that includes design and library data management integrated with the proven PCB design and analysis product portfolio of Cad...(read more) Full Article PCB OrCAD X Capture innovation PSpiceA/D PSPICE Layout PCB design OrCAD X Presto OrCAD X Constraints simulation Schematic
or 10 Most Viewed Posts in Cadence Community Forum By community.cadence.com Published On :: Thu, 26 Sep 2024 05:39:00 GMT Community engagement is a dynamic concept that does not adhere to a singular, universal approach. Its various forms, methods, and objectives can vary significantly depending on the specific context, goals, and desired outcomes. Whether you seek assis...(read more) Full Article PCB CFD Allegro X AI Community cadence awr community forum PCB Editor OrCAD PCB design OrCAD X allegro x PCB Capture
or BoardSurfers: Optimizing Designs with PCB Editor-Topology Workbench Flow By community.cadence.com Published On :: Wed, 09 Oct 2024 09:12:00 GMT When it comes to system integration, PCB designers need to collaborate with the signal analysis or integrity team to run pre-route or post-route analysis and modify constraints, floorplan, or topology based on the results. Allegro PCB Edito...(read more) Full Article Allegro X PCB Editor BoardSurfers Topology Workbench Allegro X Advanced Package Designer SPB PCB Editor PCB design Allegro PCB Editor system integration allegro x Allegro
or Cadence OrCAD X and Allegro X 24.1 is Now Available By community.cadence.com Published On :: Thu, 10 Oct 2024 06:21:00 GMT The OrCAD X and Allegro X 24.1 release is now available at Cadence Downloads. This blog post provides links to access the release and describes some major changes and new features. OrCAD X /Allegro X 24.1 (SPB241) Here is a representative li...(read more) Full Article new features Allegro X PCB Editor PSpiceA/D Allegro X Advanced Package Designer what's new APD Cadence Doc Assistant CDA PSPICE OrCAD X Presto 24.1 Pulse allegro x Allegro X System Capture
or Accelerate PCB Documentation in OrCAD X Presto with Live Doc By community.cadence.com Published On :: Fri, 18 Oct 2024 10:05:00 GMT Live Doc is an advanced automated PCB documentation generation tool integrated with OrCAD X Presto designed to streamline the creation of PCB documentation. By automating the generation of PCB fabrication and assembly drawings, Live Doc significantly...(read more) Full Article digital badge Cadence Design Systems Live Doc PCB manufacturing Allegro X PCB Editor 3dx SPB PCB design Training Insights OrCAD X Presto OrCAD X 23.1 PCB fabrication OrCAD Experts PCB Documentation online training 23.1-2023 PCB Gerber
or Multiple touch points for bond wires on a die pin By community.cadence.com Published On :: Mon, 27 Nov 2023 21:46:03 GMT Does anyone know whether it is possible to have multiple contact points for a bond wire on a large die pad? Note: This is different from adding multiple wires which I will also be doing. I need to add multiple bond connections to the same large die pad for redundancy connections to each pad for each wire. I have a large die pad which I need to have 5 wires with each wire having 3 bond connections to the same die pad. Full Article
or How to reuse device files for existing components By community.cadence.com Published On :: Thu, 07 Dec 2023 11:09:26 GMT Have you ever encountered ERROR(SPMHNI-67) while importing logic? If yes, you might already know that you had to export libraries of the design and make sure that paths (devpath, padpath, and psmpath) include the location of exported files. Starting in SPB23.1, if you go to File > Import > Logic/Netlist and click on the Other tab, you will see an option, Reuse device files for existing components. After selecting this option, ERROR(SPMHNI-67) will no longer be there in the log file, because the tool will automatically extract device files and seamlessly use them for newly imported data. In other words, SPB_23.1 lets you reuse the device / component definitions already in the design without first having to dump libraries manually. An excellent improvement, don’t you think? Full Article
or How to access the Transmission Line Calculator in Allegro X APD By community.cadence.com Published On :: Tue, 02 Jan 2024 17:05:21 GMT Have you ever thought of a handy utility to specify all necessary transmission line parameters to decide upon the stackup? Starting SPB 23.1, a handy feature Transmission Line Calculator, is built into Allegro X Advanced Package Designer (Allegro X APD). This feature will require either an SiP Layout license or can be accessed through SiP Layout Bundle. From the Analyze dropdown menu in the 23.1 Allegro X APD toolbar, you can choose Transmission Line Calculator. You can use this calculator to help decide constraints and stackup for laminate-based PCB or Packages. You can calculate the correct stackup material and width/spacing to meet any requirements that may be later entered in a constraint. This is truly a calculated number and not a true field solver. The different types of calculations that the Transmission Line Calculator can provide are Microstrip, Embedded microstrip, Stripline, CPW (Coplanar), FGCPW (frequency-dependent Coplanar), Asymmetric stripline, Coupled microstrip (Differential Pair), Coupled stripline (Differential Pair), and Dual striplines. This feature is important for customers relying on fabricators/spreadsheets to provide this information or need to test a quick spacing/width as per the impedance value. Let us know your comments on this new feature in 23.1 Allegro X APD. Full Article
or How to export and import symbols and component properties through Die Text wizards By community.cadence.com Published On :: Thu, 04 Jan 2024 15:50:39 GMT Starting SPB 23.1, Allegro X APD lets you import/export the symbol and component properties by using Die Text-In/Out wizards. Exporting the symbol You can export the symbol by using File > Export > Die Text-Out Wizard. In the Die Text-Out Wizard window, you can see the newly added options, that is, Component Properties and Symbol Properties. This entire information including the properties will be saved in a text file. Importing the symbol You can import the same text file in Allegro X APD by using Die Text-In Wizard. Choose the text file you want to import. Symbol properties added in the text file will be visible in the Die Text-In Wizard window. Full Article
or modify bump and export the modified bump By community.cadence.com Published On :: Fri, 23 Feb 2024 13:23:01 GMT hello, help me! There are many change in the bump design. I want to design bump by APD. The bump(die) is a stagger , create it by die generator. Because,the pin is not isometric. In order to RDL routing, so the bump is not isometric. I move the symbol pin in APD symbol edit(as show in the picture), and selected symbol RBM write device file, write library symbol. Export the bga text( bga text out) ,But the bump is not modified, the bump is still stagger. Can you help me! pitch2> pitch1 thanks Full Article
or DFA check space of compont to BGA ball or BGA PAD in APD By community.cadence.com Published On :: Fri, 29 Mar 2024 12:37:40 GMT Hi, There are mang components in BGA ball side of flipchip package. Are there DFA check space of compont body or pin soldermask to BGA ball or BGA PAD or bga soldermask in allegro APD? I only find space of compont to compont in APD DFA. Full Article
or Allegro X APD - Tip of the week: Wondering how to set two adjacent layers as conductor layers! Then this post should help you. By community.cadence.com Published On :: Fri, 10 May 2024 14:01:45 GMT By default, a dielectric must separate each pair of conductor layers in the cross-section of a design. In rare cases, this does not represent the real, manufactured substrate. If your design requires you to have conductor layers that are not separated by a dielectric (such as, for half-etch designs), there is a variable that needs to be set in Allegro X APD. You must set this by enabling the variable icp_allow_adjacent_conductors. This entry, and its location in the User Preferences Editor, are shown in the following image. The Objects on adjacent conductor layers do not electrically connect together, automatically. A via must be used to establish the inter-layer connections. When enabling this option, it is recommended to exercise caution because excluding dielectric layers from your cross-section can lead to inaccurate calculations, including the calculations for signal integrity and via heights. It is important that your cross-section accurately reflect the finished product to ensure the most accurate results possible. Any dielectric layers present in the manufactured part need to be in the cross-section for accurate extraction, 3D viewing, and so on. Let us know your comments on the various designs that would require adjacent conductor layers. Full Article