Emulators are great. They vastly speed up verification to the point where it’s hard to imagine life without them; as designs grow in complexity, simple simulation can’t keep up for the biggest designs. The extra oomph from emulation is almost a necessity for the top percentages of design sizes. However, many users of Palladium aren’t efficiently using their unit’s processing power, and as a result they’re missing out on the full speed-up potential that Palladium can provide.

Altair’s HERO is here for you. With its help, your Palladium unit can be even more amazing for your productivity than before.

HERO (that’s Hardware Emulator Resource Optimizer) adds emulator support to Altair’s Accelerator. You already know and love Altair’s scheduling tools; so why not make them do more for you, so you can be one of those people who are making the most out of their Palladium system?

Emulators are kind of like big computers, but it’s a lot harder to manage leftover resources on an emulator than it is on, say, a CPU. A scheduler like HERO neatly sidesteps this problem by more intelligently using the resources available to ensure that there’s a minimal patchwork of leftover resources to begin with.

HERO supports past generations of Palladium as well, so if you’re still using an older version, you can still take advantage of the upgrades HERO provides. There’s a wide variety of features HERO has that make your emulator easier to use. HERO separates a job into a “select” section and a “run” section: the “select” part makes a last-minute decision on which domains or boards to use, while the “run” part is the actual job. This makes it easier to ensure that your Palladium emulator is being used as efficiently as possible. Jobs are placed using “shapes”, which are a set of job types; these can be selected from a list of pre-defined ones by the user. Shapes can have special constraints if those are needed.

A new reservation system also helps HERO organize Palladium’s processing power better. HERO offers both “hard” reservations and “soft” reservations. A hard reservation locks other users out of reserving any part of the emulator at all, while a soft reservation allows a user to reserve a part of the emulator for a later use. Think of it like this: a soft reservation is like grabbing a ticket from the deli counter, while a hard reservation stops you from ever entering the market.

When using HERO, you can manage your entire verification workload. You’ll find that your utilization of your emulator vastly increases—it’s been reported that some users using only 30% of the capabilities of their Palladium unit(s) saw a massive increase to over 90% once they made the switch to HERO.

If you’re ready to take your Palladium productivity to the next level, Altair has a HERO for you.

To see the full presentation given by Andrea Casotto in the Cadence Theater at DAC 2019, check here.

Virtuoso Version -- IC6.1.7-64b.500.23

Cadence Spectre Version -- 17.10.515

I have a very simple circuit. Please find attached. It is basically a resistor across a port. I run a S-param simulation and can plot the S-params, but unfortunately not the Z-param or Y-param. 

/resized-image/__size/320x240/__key/communityserver-discussions-components-files/33/Capture_5F00_Sch.JPG

/resized-image/__size/320x240/__key/communityserver-discussions-components-files/33/Capture_5F00_Error.JPG

Can anyone point me in the correct direction to sort out this problem? The zpm does work in another design environment, but not in the new design environment (a new project). The virtuoso and the cadence-spectre versions match in both the project environments. I am at a loss at what to look for. 

Hi , 

I am sharing with you some simple skill script that draw line in user layer :

axlCmdRegister("DrawLine" 'DrawLine)
procedure(DrawLine()
   layer_name = "substrate geometry/userlayer"
   mypopup = axlUIPopupDefine(nil '(
      ("Done" "axlDBTransactionCommit(mark), axlFinishEnterFun()")
      ("Oops" "axlDBTransactionOops(mark), when(zerop(--oopsNum)")
      ("Cancel" "axlDBTransactionRollback(mark), axlCancelEnterFun()")
      ("MENU_SEPARATOR", nil)))
   axlUIPopupSet( mypopup)
   ; Clear the dynamic buffer
   axlClearDynamics()

   if(axlLayerGet(layer_name) != nil then
      if(axlIsVisibleLayer(layer_name) == nil then
         axlVisibleLayer(layer_name,t)
         axlVisibleUpdate(t)
      );End if
   else
      if(axlLayerGet("substrate geometry") == nil then
         layer_name = "board geometry/userlayer"
         axlLayerCreateNonConductor(layer_name)
         axlVisibleLayer(layer_name,t)
         axlVisibleUpdate(t)
      else
         axlLayerCreateNonConductor(layer_name)
         axlVisibleLayer(layer_name,t)
         axlVisibleUpdate(t)
      );End if
   );End if

   ; Clear mypath to nil, then loop gathering user picks:
   mypath = nil
   mark = axlDBTransactionStart()
   flag = t
   allP = list(nil)
   seg1 = nil
   seg2 = nil
   while( (mypath = axlEnterPath(?lastPath mypath))
      if(flag == t then
         p = axlDBCreatePath(mypath, layer_name)
         seg1 = car(car(car(p))->segments)
         seg2 = car(cdr(car(car(p))->segments))
         path = axlPathStart( list(car(seg1->startEnd)) , 0)
         axlPathLine( path , 0 , car(cdr(seg1->startEnd)))
         if(seg2 then
            axlPathLine( path , 0 , car(cdr(seg2->startEnd)))
         );end if
         flag = nil
      else
         p = axlDBCreatePath(mypath, layer_name)
         seg1 = car(car(car(p))->segments)
         seg2 = car(cdr(car(car(p))->segments))
         axlPathLine( path , 0 , car(cdr(seg1->startEnd)))
         if(seg2 then
            axlPathLine( path , 0 , car(cdr(seg2->startEnd)))
         );end if
      );end if
      allP = cons(car(car(p)) allP)
   );Loop
   axlDBCreatePath(path, layer_name)
   forall( x allP axlDeleteObject(x))
);End procedure

Is anyone can help to understand why this script can work with 16.5/16.6/17.2 and doesn't work with 17.4 ?

To be more informative in 17.4 this script behaves differently , when i am trying to draw line i can't zoom in/out ,i can't use my shortcuts to snap it on segment/middle/edge , it's like it's waiting only for next X/Y user click , all other functions just disabled .

Thanks .

I have a problem connected with my AXI4 coverage.

I enable coverage collection in AXI4 

      set_config_int("axi4_active_slave_agent_0.monitor.coverModel", "burst_started_enable", 1);
      set_config_int("axi4_active_slave_agent_0.monitor.coverModel", "coverageEnable", 1);

but i don't have a result.

I think the problem in Callback, but i try to connect all callback and i don't have positive result.

Can you help me?

Hi everyone! I'm working on a small battery powered PCB which will fit inside a small plastic "hockey puck" container. A number of these "pucks" will be sold together with a "charging doc" which will store and charge the pucks when not in use.

I'm trying to work out the best way to charge the battery. I'm thinking of having metal "pads" on the rr.com puck that pass through the puck's plastic shell and then make contact with the PCB on the inside, and having a similar system on the charging dock. I'm thinking of having SMD "contact sprints" mounted to the underside of the PCB and have these mate against metal pins that protrude through the puck, but it's the later of which I'm struggling to find. For a visual, think about "restaurant pagers" and how they charge.

Hello All,

Following is the einstein's puzzle solved by cadence Incisive92  (solved in less than 3 seconds -> FAST!!!!!!)

Thanks,

Vinay Honnavara

Verification engineer at Keyu Tech

vinayh@keyutech.com

 // Author: Vinay Honnavara

// Einstein formulated this problem : he said that only 2% in the world can solve this problem
// There are 5 different parameters each with 5 different attributes
// The following is the problem

// -> In a street there are five houses, painted five different colors (RED, GREEN, BLUE, YELLOW, WHITE)

// -> In each house lives a person of different nationality (GERMAN, NORWEGIAN, SWEDEN, DANISH, BRITAIN)

// -> These five homeowners each drink a different kind of beverage (TEA, WATER, MILK, COFFEE, BEER),

// -> smoke different brand of cigar (DUNHILL, PRINCE, BLUE MASTER, BLENDS, PALL MALL)

// -> and keep a different pet (BIRD, CATS, DOGS, FISH, HORSES)


///////////////////////////////////////////////////////////////////////////////////////
// *************** Einstein's riddle is: Who owns the fish? ***************************
///////////////////////////////////////////////////////////////////////////////////////

/*
Necessary clues:

1. The British man lives in a red house.
2. The Swedish man keeps dogs as pets.
3. The Danish man drinks tea.
4. The Green house is next to, and on the left of the White house.
5. The owner of the Green house drinks coffee.
6. The person who smokes Pall Mall rears birds.
7. The owner of the Yellow house smokes Dunhill.
8. The man living in the center house drinks milk.
9. The Norwegian lives in the first house.
10. The man who smokes Blends lives next to the one who keeps cats.
11. The man who keeps horses lives next to the man who smokes Dunhill.
12. The man who smokes Blue Master drinks beer.
13. The German smokes Prince.
14. The Norwegian lives next to the blue house.
15. The Blends smoker lives next to the one who drinks water.
*/




typedef enum bit [2:0]  {red, green, blue, yellow, white} house_color_type;
typedef enum bit [2:0]  {german, norwegian, brit, dane, swede} nationality_type;
typedef enum bit [2:0]  {coffee, milk, water, beer, tea} beverage_type;
typedef enum bit [2:0]  {dunhill, prince, blue_master, blends, pall_mall} cigar_type;
typedef enum bit [2:0]  {birds, cats, fish, dogs, horses} pet_type;




class Einstein_problem;

    rand house_color_type house_color[5];
    rand nationality_type nationality[5];
    rand beverage_type beverage[5];
    rand cigar_type cigar[5];
    rand pet_type pet[5];
        rand int arr[5];
    
    constraint einstein_riddle_solver {
    
        
    
        foreach (house_color[i])
            foreach (house_color[j])
               if (i != j)
                house_color[i] != house_color[j];
        foreach (nationality[i])
            foreach (nationality[j])
               if (i != j)
                nationality[i] != nationality[j];
        foreach (beverage[i])
            foreach (beverage[j])
               if (i != j)
                beverage[i] != beverage[j];
        foreach (cigar[i])
            foreach (cigar[j])
               if (i != j)
                cigar[i] != cigar[j];
        foreach (pet[i])
            foreach (pet[j])
               if (i != j)
                pet[i] != pet[j];
    
    
        //1) The British man lives in a red house.
        foreach(nationality[i])
                (nationality[i] == brit) -> (house_color[i] == red);
                
        
        //2) The Swedish man keeps dogs as pets.
        foreach(nationality[i])
                (nationality[i] == swede) -> (pet[i] == dogs);
                
                
        //3) The Danish man drinks tea.        
        foreach(nationality[i])
                (nationality[i] == dane) -> (beverage[i] == tea);
        
        
        //4) The Green house is next to, and on the left of the White house.
        foreach(house_color[i])        
                 if (i<4)
                    (house_color[i] == green) -> (house_color[i+1] == white);
        
        
        //5) The owner of the Green house drinks coffee.
        foreach(house_color[i])
                (house_color[i] == green) -> (beverage[i] == coffee);
                
        
        //6) The person who smokes Pall Mall rears birds.
        foreach(cigar[i])
                (cigar[i] == pall_mall) -> (pet[i] == birds);
        
        
        //7) The owner of the Yellow house smokes Dunhill.
        foreach(house_color[i])
                (house_color[i] == yellow) -> (cigar[i] == dunhill);
        
        
        //8) The man living in the center house drinks milk.
        foreach(house_color[i])
                if (i==2) // i==2 implies the center house (0,1,2,3,4) 2 is the center
                    beverage[i] == milk;
        
        
        
        //9) The Norwegian lives in the first house.
        foreach(nationality[i])        
                if (i==0) // i==0 is the first house
                    nationality[i] == norwegian;
        
        
        
        //10) The man who smokes Blends lives next to the one who keeps cats.
        foreach(cigar[i])        
                if (i==0) // if the man who smokes blends lives in the first house then the person with cats will be in the second
                    (cigar[i] == blends) -> (pet[i+1] == cats);
        
        foreach(cigar[i])        
                if (i>0 && i<4) // if the man is not at the ends he can be on either side
                    (cigar[i] == blends) -> (pet[i-1] == cats) || (pet[i+1] == cats);
        
        foreach(cigar[i])        
                if (i==4) // if the man is at the last
                    (cigar[i] == blends) -> (pet[i-1] == cats);
        
        foreach(cigar[i])        
                if (i==4)
                    (pet[i] == cats) -> (cigar[i-1] == blends);
        
        
        //11) The man who keeps horses lives next to the man who smokes Dunhill.
        foreach(pet[i])
                if (i==0) // similar to the last case
                    (pet[i] == horses) -> (cigar[i+1] == dunhill);
        
        foreach(pet[i])        
                if (i>0 & i<4)
                    (pet[i] == horses) -> (cigar[i-1] == dunhill) || (cigar[i+1] == dunhill);
                    
        foreach(pet[i])        
                if (i==4)
                    (pet[i] == horses) -> (cigar[i-1] == dunhill);
                    


        //12) The man who smokes Blue Master drinks beer.
        foreach(cigar[i])
                (cigar[i] == blue_master) -> (beverage[i] == beer);
        
        
        //13) The German smokes Prince.
        foreach(nationality[i])        
                (nationality[i] == german) -> (cigar[i] == prince);
        

        //14) The Norwegian lives next to the blue house.
        foreach(nationality[i])
                if (i==0)
                    (nationality[i] == norwegian) -> (house_color[i+1] == blue);
        
        foreach(nationality[i])        
                if (i>0 & i<4)
                    (nationality[i] == norwegian) -> (house_color[i-1] == blue) || (house_color[i+1] == blue);
        
        foreach(nationality[i])        
                if (i==4)
                    (nationality[i] == norwegian) -> (house_color[i-1] == blue);
        

        //15) The Blends smoker lives next to the one who drinks water.            
        foreach(cigar[i])            
                if (i==0)
                    (cigar[i] == blends) -> (beverage[i+1] == water);
        
        foreach(cigar[i])        
                if (i>0 & i<4)
                    (cigar[i] == blends) -> (beverage[i-1] == water) || (beverage[i+1] == water);
                    
        foreach(cigar[i])        
                if (i==4)
                    (cigar[i] == blends) -> (beverage[i-1] == water);
        
    } // end of the constraint block
    


    // display all the attributes
    task display ;
        foreach (house_color[i])
            begin
                $display("HOUSE : %s",house_color[i].name());
            end
        foreach (nationality[i])
            begin
                $display("NATIONALITY : %s",nationality[i].name());
            end
        foreach (beverage[i])
            begin
                $display("BEVERAGE : %s",beverage[i].name());
            end
        foreach (cigar[i])
            begin
                $display("CIGAR: %s",cigar[i].name());
            end
        foreach (pet[i])
            begin
                $display("PET : %s",pet[i].name());
            end
        foreach (pet[i])
            if (pet[i] == fish)
                $display("THE ANSWER TO THE RIDDLE : The %s has %s ", nationality[i].name(), pet[i].name());
    
    endtask // end display
    
    
endclass




program main ;

    initial
        begin
            Einstein_problem ep;
            ep = new();
            if(!ep.randomize())
                $display("ERROR");
            ep.display();
        end
endprogram // end of main

        

Hello,

 I am working in a digital design. The functional, post synthesis and post P&R without IO pads are all working fine, i.e., functionally and with clean timing reports "no setup/hold violations". I just added the IO pads to the same design, I had to change the timing constraints a bit for the synthesis but I have a clean design at SOC Encounter, i.e., clean DRC and clean timing reports "no setup/hold violations". However, when I perform simulation using the exported net-list from SOC Encounter together with SDF exported from the same tool, I got a lot of hold violations. Consequently, the design is not funcitioning.

Why and how I can overcome or trobleshoot this issue?

In waiting for your feedback and comments.

Regards.

Hello,

I am trying to import multiple verilog modules defined in a single file with "`define" directive in the top using Verilog In. The code below is an example of what my file contains.

When I use the settings below to import the modules into a library, it imports it correctly but completely ignores all `define directive; hence when I simulate using any of the modules below the simulator errors out requesting these variables.

My question: Is there a way to make Verilog In consider `define directives in every module cell created? 

Code to be imported by Cadence Verilog In:

--------------------------------------------------------

`timescale 1ns/1ps
`define PROP_DELAY 1.1
`define INVALID_DELAY 1.3

`define PERIOD 1.1
`define WIDTH 1.6
`define SETUP_TIME 2.0
`define HOLD_TIME 0.5
`define RECOVERY_TIME 3.0
`define REMOVAL_TIME 0.5
`define WIDTH_THD 0.0

`celldefine
module MY_FF (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF
`endcelldefine

`timescale 1ns/1ps
`celldefine
module MY_FF2 (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF2
`endcelldefine

--------------------------------------------------------

I am using the following Cadence versions:

MMSIM Version: 13.1.1.660.isr18

Virtuoso Version: IC6.1.8-64b.500.1

irun Version: 14.10-s039

Spectre Version: 18.1.0.421.isr9

Hi, 

I want my layout verified by Quantus QRC. But, I can't find the tool bar on the option list ( as show in the picture)

I have tried to install EXT182 and configured it with iscape already, and also make some path settings on .bashrc, .cshrc. But, when I re-source .cshrc and run virtuoso again, I just can't find the toolbar. 

If you have some methods, please let me know.

Thanks a lot!

Appreciated

My virtuoso version is: ICADV12.3

Hi,

I tried to open my layout by Library Manager, but the Virtuoso CIW window sometimes pops up the follow WARNING messages( as picture depicts). Thus, layout can't open.

Sometimes, I try to reconfigure ICADV12.3 by the iscape and restart my VM and then it incredibly works! But, often not!

So, If anyone knows what it is going on. Please let me know! Thanks!

Appreciated so much   

Hello,

I find a strange issue when using design variable -> right-click -> copy from cellview in assembler. Cadence version is IC618-64b. 500.9

In fact, I set the value of variable (e.g., AAA = 100), then after I right-click -> copy from cellview, AAA's is updated to other value. In my opinion "copy from cellview" should only update the missing variable to the list, but not change any variable value. 

Is there any mechanism could change variable value when using "copy from cellview"?

Thanks

Key Findings: Many more design teams will be reaching the mixed-signal methodology tipping point in 2015. That means you need to have a (verification) plan, and measure and execute against it.

As 2014 draws to a close, it is time to look ahead to the coming years and make a plan. While the macro view of the chip design world shows that is has been a mixed-signal world for a long time, it is has been primarily the digital teams that have rapidly evolved design and verification practices over the past decade. Well, I claim that is about to change. 2015 will be a watershed year for many more design teams because of the following factors:

• 85% of designs are mixed signal, and it is going to stay that way (there is no turning back)
• Advanced node drives new techniques, but they will be applied on all nodes
• Equilibrium of mixed-signal designs being challenged, complexity raises risk level
• Tipping point signs are evident and pervasive, things are going to change
• The convergence of “big A” and “big D” demands true mixed-signal practices

Reason 1: Mixed-signal is dominant

To begin the examination of what is going to change and why, let’s start with what is not changing. IBS reports that mixed signal accounts for over 85% of chip design starts in 2014, and that percentage will rise, and hold steady at 85% in the coming years. It is a mixed-signal world and there is no turning back!

Figure 1. IBS: Mixed-signal design starts as percent of total

The foundational nature of mixed-signal designs in the semiconductor industry is well established. The reason it is exciting is that a stable foundation provides a platform for driving change. (It’s hard to drive on crumbling infrastructure.  If you’re from California, you know what I mean, between the potholes on the highways and the earthquakes and everything.)

Reason 2: Innovation in many directions, mostly mixed-signal applications

While the challenges being felt at the advanced nodes, such as double patterning and adoption of FinFET devices, have slowed some from following onto to nodes past 28nm, innovation has just turned in different directions. Applications for Internet of Things, automotive, and medical all have strong mixed-signal elements in their semiconductor content value proposition. What is critical to recognize is that many of the design techniques that were initially driven by advanced-node programs have merit across the spectrum of active semiconductor process technologies. For example, digitally controlled, calibrated, and compensated analog IP, along with power-reducing mutli-supply domains, power shut-off, and state retention are being applied in many programs on “legacy” nodes.

Another graph from IBS shows that the design starts at 45nm and below will continue to grow at a healthy pace.  The data also shows that nodes from 65nm and larger will continue to comprise a strong majority of the overall starts. 

Figure 2.  IBS: Design starts per process node

TSMC made a comprehensive announcement in September related to “wearables” and the Internet of Things. From their press release:

TSMC’s ultra-low power process lineup expands from the existing 0.18-micron extremely low leakage (0.18eLL) and 90-nanometer ultra low leakage (90uLL) nodes, and 16-nanometer FinFET technology, to new offerings of 55-nanometer ultra-low power (55ULP), 40ULP and 28ULP, which support processing speeds of up to 1.2GHz. The wide spectrum of ultra-low power processes from 0.18-micron to 16-nanometer FinFET is ideally suited for a variety of smart and power-efficient applications in the IoT and wearable device markets. Radio frequency and embedded Flash memory capabilities are also available in 0.18um to 40nm ultra-low power technologies, enabling system level integration for smaller form factors as well as facilitating wireless connections among IoT products.

Compared with their previous low-power generations, TSMC’s ultra-low power processes can further reduce operating voltages by 20% to 30% to lower both active power and standby power consumption and enable significant increases in battery life—by 2X to 10X—when much smaller batteries are demanded in IoT/wearable applications.

The focus on power is quite evident and this means that all of the power management and reduction techniques used in advanced node designs will be coming to legacy nodes soon.

Integration and miniaturization are being pursued from the system-level in, as well as from the process side. Techniques for power reduction and system energy efficiency are central to innovations under way.  For mixed-signal program teams, this means there is an added dimension of complexity in the verification task. If this dimension is not methodologically addressed, the level of risk adds a new dimension as well.

Reason 3: Trends are pushing the limits of established design practices

Risk is the bane of every engineer, but without risk there is no progress. And, sometimes the amount of risk is not something that can be controlled. Figure 3 shows some of the forces at work that cause design teams to undertake more risk than they would ideally like. With price and form factor as primary value elements in many growing markets, integration of analog front-end (AFE) with digital processing is becoming commonplace.  

Figure 3.  Trends pushing mixed-signal out of equilibrium

The move to the sweet spot of manufacturing at 28nm enables more integration, while providing excellent power and performance parameters with the best cost per transistor. Variation becomes great and harder to control. For analog design, this means more digital assistance for calibration and compensation. For greatest flexibility and resiliency, many will opt for embedding a microcontroller to perform the analog control functions in software. Finally, the first wave of leaders have already crossed the methodology bridge into true mixed-signal design and verification; those who do not follow are destined to fall farther behind.

Reason 4: The tipping point accelerants are catching fire

The factors cited in Reason 3 all have a technical grounding that serves to create pain in the chip-development process. The more factors that are present, the harder it is to ignore the pain and get the treatment relief  afforded by adopting known best practices for truly mixed-signal design (versus divide and conquer along analog and digital lines design).

In the past design performance was measured in MHz with simple static timing and power analysis. Design flows were conveniently partitioned, literally and figuratively, along analog and digital boundaries. Today, however, there are gigahertz digital signals that interact at the package and board level in analog-like ways. New, dynamic power analysis methods enabled by advanced library characterization must be melded into new design flows. These flows comprehend the growing amount of feedback between analog and digital functions that are becoming so interlocked as to be inseparable. This interlock necessitates design flows that include metrics-driven and software-driven testbenches, cross fabric analysis, electrically aware design, and database interoperability across analog and digital design environments.

Figure 4.  Tipping point indicators

Energy efficiency is a universal driver at this point.  Be it cost of ownership in the data center or battery life in a cell phone or wearable device, using less power creates more value in end products. However, layering multiple energy management and optimization techniques on top of complex mixed-signal designs adds yet more complexity demanding adoption of “modern” mixed-signal design practices.

Reason 5: Convergence of analog and digital design

Divide and conquer is always a powerful tool for complexity management.  However, as the number of interactions across the divide increase, the sub-optimality of those frontiers becomes more evident. Convergence is the name of the game.  Just as analog and digital elements of chips are converging, so will the industry practices associated with dealing with the converged world.

Figure 5. Convergence drivers

Truly mixed-signal design is a discipline that unites the analog and digital domains. That means that there is a common/shared data set (versus forcing a single cockpit or user model on everyone). 

In verification the modern saying is “start with the end in mind”. That means creating a formal approach to the plan of what will be test, how it will be tested, and metrics for success of the tests. Organizing the mechanics of testbench development using the Unified Verification Methodology (UVM) has proven benefits. The mixed-signal elements of SoC verification are not exempted from those benefits.

Competition is growing more fierce in the world for semiconductor design teams. Not being equipped with the best-known practices creates a competitive deficit that is hard to overcome with just hard work. As the landscape of IC content drives to a more energy-efficient mixed-signal nature, the mounting risk posed by old methodologies may cause causalities in the coming year. Better to move forward with haste and create a position of strength from which differentiation and excellence in execution can be forged.

Summary

2015 is going to be a banner year for mixed-signal design and verification methodologies. Those that have forged ahead are in a position of execution advantage. Those that have not will be scrambling to catch up, but with the benefits of following a path that has been proven by many market leaders.

کوروناوائرس سے نمٹنے کیلئے عمران خان حکومت جو فیصلہ لے رہی ہے ا ن میں کافی حد تک مودی حکومت (Narendra Modi) کی جھلک نظر آرہی ہے۔ ایک نئے فیصلے میں عمران حکومت نے ہندستان سے سیکھ لیکر ملک کی ٹرینوں میں آئیسولیشن وارڈ بنانے کا فیصلہ لیا ہے۔

پوری دنیا میں کوروناوائرس (Coronavirus) کا خوف ہے۔ لوگ گھروں سے باہر نکلنے میں بھی ڈر رہے ہیں لیکن ایسالگ رہا ہے کہ پاکستان (Pakistan) کے لوگوں کوکوروناوائرس کا کوئی ڈر نہیں ہے۔

ایران کے وزیر خارجہ جوادظریف نے ٹویٹ کیا 'کوروناوائرس وبا کے دوران فنڈ روکنا شرمناک ہے۔ دنیا وہی دیکھ رہی ہے ہے جو یران ہمیشہ سہتا آیا ہے۔ ٹویٹ میں آگے لکھا کہ امریکی حکمرانی کی یہ دھمکیاں، ڈرانا اور جھگڑالو رویہ صرف اس کی ایل لت ہی نہیں بلکہ لوگوں کو مرنے دینے کی یہ اس کی پرانی عادت ہے '۔

میگھالیہ (Meghalaya) میں کوروناوائرس (Coronavirus) سے جان گنوانے والے پہلے شخص 69 سالہ ایک ڈاکٹر کو موت کے 36 گھنٹے بعد جمعرات کو یہاں دفنا دیا گیا۔ ایک قبرستان نے کوروناوائرس سے جان گنوانے والے لوگوں کی لاشوں کو دفنانے کیلئے پی پی ای نہیں ہونے اور مقامی لوگوں کی مخالفت کا حوالہ دیتے ہوئے ڈاکٹر کی بدھ کو آخری رسوم کرنے سے انکار کردیا تھا۔

شہزادی بسمہ نے ٹویٹر اکاونٹ پر لکھا جیسا کہ آپ جانتے ہیں کہ فی الحال میں الحائر جیل میں کسی جرم کے بغیر سزا کاٹ رہی ہوں ، میری صحت اس حد تک بگڑ رہی ہے کہ اس سے میری موت تک ہوسکتی ہے ۔

لاک ڈٓاون کی خلاف ورزی کرنے پر پولیس نے ان لوگوں کو حراست میں لے لیا ۔ حالانکہ بعد میں انہیں چھوڑ بھی دیا گیا ، لیکن ایمبولنس ڈرائیور کو پولیس نے ضرور گرفتار کرلیا اور اس کی گاڑی بھی ضبط کرلی ۔

بالی ووڈ کے سلطان سلمان خان کی آ نے والی فلم' بھارت' کی شوٹنگ شروع ہوچکی ہے۔فلم کےڈائرکٹر علی عباس ظفر نے شوٹنگ کے درمیان کی ایک تصویرشیئرکی ہے ۔

پاکستانی اداکارہ وینا ملک نے کشمیر کولیکر انسٹاگرام پر ایک ویڈیو شیئر کیا ہے۔ جس میں وہ پاکستان زندہ باد اور کشمیر بنے گا پاکستان کا نعرہ لگا رہی ہیں۔

شلپا کہتی ہیں "اگر میرا ملک مجھے ویز ا دیتا ہے اور ان کا ملک استقبال کرتا ہے تومیں ضرور پاکستان جاؤں گی۔ ایک فنکار ہونے کے ناطے میں پرفارم کروں گی۔ یہ میرا حق ہے، مجھے کوئی نہیں روک سکتا۔

بالی ووڈ کے سب سے ہٹ "بھائی گینگ "کے لاڈلے اور سب سے چھوٹے بھائی سہیل خان کمال کے انسان ہیں ۔آج ان کی سالگرہ ہے۔ ان کی پیدائش 20دسمبر1969 کو ہوئی۔ اب وہ 50 سال کے ہو جائیں گے۔

મહેસાણાઃ મહેસાણામાં આવેલ નાગલપુર કોલેજમાં એક તરફી પ્રેમમાં યુવકે વિદ્યાર્થીની પર એસિડ વડે હુમલો કર્યો છે. ત્યારે એસિડ એટેક તરનાર હાર્દિક પ્રજાપતીની પોલીસે ધરપકડ કરી છે. તેણે કોલેજમાં ફસ્ટયરમાં અભ્યાસ કરતી વિદ્યાર્થીની પર હુમલો કરાયો કર્યો હતો.

ایک رپورٹ کے مطابق ڈپارٹمینٹ آف ہیومن سروس نے جنم کی شرح کا ڈاٹا رلیز کیا تھا جس کے مطابق بچوں کو جنم دینے والے 22 مرد ٹرنسجینڈر تھے۔ حالانکہ سال 2009 تک اس سلسلے میں کوئی اعدادوشمار سامنے نہیں آیا تھا۔ بچوں کو جنم دینے کے ساتھ ہی ان مردوں کا 228 کی اس فہرست میں شامل ہوگیا جس میں گزشتہ ایک دہائی میں بچوں کو جنم دینے والے لوگوں کے نام درج تھے۔

اگر آپ کسی بھی ٹینشن میں ہیں یا پریشان ہیں تو ذرا وقت نکالئے اور رام کپور کی انسٹاگرام پوسٹ دیکھئے۔ رام کپور نے ایک مزیدار میم شیئر کیا اور بتایا کہ اگر بیوی غصے میں ہو تو اسے اپنے لئے سینڈوچ بنانے کو نہیں کہنا چاہئے۔

મોડાસાઃઅરવલ્લી જીલ્લાના માલપુરની વાત્રક નદીના કિનારે આવેલ જુના રક્ષેશ્વર મહાદેવ મંદિર વર્ષમાં એકવાર પાણીની બહાર આવે છે.રૂગનાથ પુર ગામ પાસે આવેલ જુના રક્ષેશ્વર મહાદેવ મંદિરે ત્રિદિવસીય ૩૧ કુંડી મહારુદ્ર યજ્ઞ યોજાતા હજારોની સંખ્યામાં જીલ્લાના ભકતો દર્શન કરવા માટે ઉમટી પડ્યા હતા.બ્રાહ્મણો દ્વારા વૈદિક મંત્રોચ્ચાર કરી મહારુદ્ર યજ્ઞનું પઠન કરાતા હર હર મહાદેવના નાદથી વાતાવરણ ગુંજી ઉઠ્યું હતું.

અમદાવાદઃ અમદાવાદમાં મુખ્યપ્રધાન આનંદીબહેન પટેલ શુક્રવારે સવારે ઈન્ડસ્ટ્રીયલ એક્સપોમાં સંબોધન કરતા નાનાઉદ્યોગ માટે બનાવેલી પોલિસીના કેટલાક મુદ્દા રજૂ કર્યા હતા અને 'સાણંદની જેમ હાલોલ-ભરૂચ ખાતે મહિલા ઉદ્યોગ પાર્ક શરૂ કરવાની જાહેરાત કરી હતી.

پولیس نے ضلع اونتی پورہ میں بھی وندک پورہ نامی گاوں کو ریڈ زون اور گوری پورہ علاقےکو بفر زون قرار دے دیا ہے۔ دوسری طرف قصبہ پانپورکے سونبورہ، الوچی باغ، اورکرنا بل، علاقوں کو ریڈ زون قراددیا گیا ہے۔

روز کام کرکے دو وقت کی روٹی کا انتظام کرنے والا سماج کا غریب اور مزدور طبقہ لاک ڈاؤن کے دوران سب سے زیادہ پریشان ہے۔ کام اور روزگار کے بغیر گزشتہ ایک ماہ سے زیادہ کا وقت گزرنے کے بعد اب ان مزدوروں کا حوالہ اور صبر ٹوٹ رہا ہے اور یہ غریب اب لاک ڈاؤن کے ختم ہونے کا انتظار کر رہے ہیں۔

لاک ڈاون کے بیچ ٹنگمرگ کنزر کے اُٹکو میں کشمیریت اور انسانیت کی ایک اور بہترین مثال قائم ہوئی۔ محمد ارشاد نے گلمرگ میں پھنسےغیر مسلم گوتم نامی سیاح کو پریشان حال دیکھ کر انہیں اپنے گھر میں پناہ دی۔

حسین جہاں کا ایک ویڈیو سوشل میڈیا پر فینس کافی پسند کررہے ہیں ، جس میں وہ ڈانس کررہی ہیں ۔

حکومت نے کہا ہے کہ یہ سہولت ادائیگی کی بنیاد پر مہیا کرائی جائےگی ۔ ان شہریوں کو لانے کیلئے خصوصی مسافر پروازوں کا انتظام کیا جائےگا ۔

کورونا وبا کے بڑھتے خطرے کے پیش نظر دار العلوم دیوبند نے اپریل ماہ میں ہونے والے سالانہ امتحانات کو پہلے ہی ملتوی کرکے تعطیلات کا اعلان کر دیا تھا اور اس کے بعد زیادہ تر طالب علم اپنے گھروں کو لوٹ گئے تھے۔

قرنطینہ کی مدت مکمل ہونے کے باوجود 200کے قریب تبلیغی جماعت کے ممبران کولکاتہ کے نیوٹاؤن حج ہاٶس میں موجود ہیں۔

کورونا وائرس کے علاج میں ہائیڈرو کسی کلوروکین مفید ہونے کی خبر کے بعد مارچ میں ہی آئی سی ایم آر نے ہائیڈرو کسی کلوروکین کے اندھادھند استعمال پر متنبہ کیا تھا ۔

تلنگانہ پولیس ملک بھر میں اپنی نوعیت کا پہلا اقدام کرتے ہوئے جدید ٹکنالوجی کی مدد سے ان لوگوں کا پتہ چلائے گی جو لاک ڈاؤن کے دوران فیس ماسک پہنے بغیر گھر سے باہر نکلیں گے۔

ملزم ٹیچر نے ایسے چیٹس کی جانکاری ہونے پر طلبہ و طالبات کو وارننگ دی ہے کہ وہ پولیس میں شکایت کرے گا ۔

#સાબરકાંઠા જિલ્લાના બહુચર્ચિત રૂ.55 લાખના પુસ્તક કૌભાંડમાં ચોંકાવનારી વિગતો સામે આવી છે. આ મામલે આરોપી ક્લાર્કની ધરપકડ કરાતાં રિમાન્ડ દરમિયાન અન્ય સ્ફોટક માહિતી સામે આવી છે. ચકચારી આ કૌભાંડમાં કચેરીના અધિકારી અને અન્ય કર્મચારીઓ પણ સંકળાયેલા હોવાનું પોલીસ તપાસમાં ખુલવા પામ્યું છે.