An accumulating apparatus (4) has an upper arm (51) in which a plurality of upper rollers (511) are arranged, and a lower arm (52) in which a plurality of lower rollers (521) are arranged. An upper gear (61) is fixed to the upper arm and a lower gear (62) is fixed to the lower arm. The upper gear is engaged with the lower gear so that the upper arm and the lower arm are simultaneously moved in opposite directions with respect to a vertical direction. Therefore, when moving the lower arm in the vertical direction, influence of the weight of the lower arm is canceled by the weight of the upper arm, and a force to move the lower arm upward can be reduced. As the result, an air cylinder (63) for changing a distance between the upper arm and the lower arm can be downsized.

Groups of phase shifted Pulse Width Modulation signals are generated that maintain their duty-cycle and phase relationships as a function of the period of the PWM signal frequency. The multiphase PWM signals are generated in a ratio-metric fashion so as to greatly simplify and reduce the computational workload for a processor used in a PWM system. The groups of phase shifted PWM signals may also be synchronized with and automatically scaled to match external synchronization signals.

In an embodiment, a method of generating a pulse-width modulated signal from an input signal includes calculating a finite number of basis functions of a first pulse-width modulated signal based on the input signal, and forming an electronic output based on the calculated finite number of basis functions.

A phase-locked loop double-point modulator may include a frequency divider having a ratio which can be changed by a first modulation signal, and an oscillator, a frequency of which can be changed by a second modulation signal correlated to the first modulation signal. A calibration circuit may be configured, in a calibration mode, to match the gains of the first and second modulation signals based on frequency measurements of the oscillator for two different calibration values of the second modulation signal. The phase-locked double-point modulator may also include an attenuator having a constant ratio greater than 1 and placed in the path of the second modulation signal, and a selector switch configured to be controlled by the calibration circuit to reduce the ratio of the attenuator in the calibration mode.

An amplifier receives an amplitude signal of a polar modulated signal at a base terminal of a transistor and receives a phase modulated carrier signal of the polar modulated signal at the base terminal of the transistor. The amplifier combines the amplitude signal and the phase modulated signal to produce a full complex waveform at a collector terminal of the transistor.

A modulator generates a baseband digital signal from an information-bearing digital signal. The baseband signal has time-varying phase and amplitude defined by a sequence of complex data words, each having an in-phase (I) component and a quadrature (Q) component. A noise-shaping modulator generates a noise-shaped digital signal from the baseband digital signal such that quantization noise in the noise-shaping modulator is attenuated by a spectral null of its noise transfer function. The spectral null is selected by a noise-shaping parameter corresponding to a selected one of a plurality of output frequencies. A signal converter generates an analog signal conveying the information of the information-bearing digital signal on an analog carrier signal having the selected output frequency.

A new coded continuous phase modulation (CPM) scheme is proposed to enhance physical layer performance of the current DVB-RCS standard for a satellite communication system. The proposed CPM scheme uses a phase pulse design and combination of modulation parameters to shape the power spectrum of CPM signal in order to improve resilience to adjacent channel interference (ACI). Additionally, it uses a low complexity binary convolutional codes and S-random bit interleaving. Phase response using the proposed CPM scheme is a weighted average of the conventional rectangular and raised-cosine responses and provides optimum response to minimize frame error rate for a given data rate.

A PWM circuit that can have two refresh rates, including: a first PWM signal generator and a second PWM signal generator; wherein the first PWM signal generator and the second PWM signal generator respectively control refresh rates in two dimensions of an output data generated from a target apparatus. A PWM signal generation method that can have two refresh rates, including: generating a first PWM signal; generating a second PWM signal; and controlling refresh rates in different dimensions of an output data generated from a target apparatus respectively by using the first PWM signal and the second PWM signal.

A digital pulse width modulation controller includes a pulse width modulation controller, a selection unit having at least one selector, a comparison unit having at least one comparator, and a signal conversion unit having at least one digital-to-analog converter. The digital-to-analog converter generates a reference current and/or voltage. The comparator receives the reference current and/or voltage, and performs a comparison operation to generate a comparison signal based on a feedback signal. The selector selects one selection signal to input into the pulse width modulation controller, which receives other parameters set by a user or the system at the same time so as to control characteristics of the digital pulse width modulation signals, thereby improving the electric properties of a loading circuit.

Techniques and mechanisms for configuring logic to implement a signal modulation. In an embodiment, the logic includes a finite impulse response (FIR) module comprising circuitry. The selection circuitry may be operable to concurrently receive signals from latch circuitry of the FIR module and, based on the signals, to select an input group of the selection circuitry and to output a voltage identifier. In another embodiment, configuration logic is operable to set an operational mode which determines a total number of concurrent input signals, received by the FIR module, which the FIR module will use to select an input group for generating an output representing a voltage level.

A circuit includes a switched modulator stage combining an information signal with a square wave carrier to produce a first modulated signal; and a second modulation stage forming additional steps in the first modulated signal to produce a second modulated signal.

A rail-to-rail comparator including a first comparison unit connected to a first terminal and configured to compare differential input signals to differential reference voltages; a second comparison unit connected to a second terminal and configured to compare the differential input signals to the differential reference voltages; and an output unit configured to be driven in response to a clock signal and to generate a complementary output signal according to comparison results of the first and second comparison units.

An example PWM includes a driver and a two-way oscillator. The oscillator includes, a first frequency adjust current source, a second frequency adjust current source, a capacitor, a switching reference and a comparator. The capacitor integrates a frequency adjust current by charging with the first frequency adjust current source. The capacitor subsequently integrates a second frequency adjust current by discharging with the second frequency adjust current source. The switching reference outputs a first reference voltage and a second reference voltage responsive to an oscillator signal. The comparator compares the output of the switching reference with a voltage on the capacitor. The first and second frequency adjust current sources vary the first and second frequency adjust currents to vary the frequency of the PWM signal to spread energy of switching harmonics over a frequency band and to reduce EMI.

A time-varying formant is generated at a formant frequency by generating first and second harmonic phase signals having first and second harmonic numbers, respectively, in relation to a modulation frequency. The first and second harmonic phase signals are generated in proportion to a master phase signal, which varies at the modulation frequency, modulo a factor corresponding to their harmonic numbers. First and second sound signals, based on the first and second harmonic phase signals, are frequency modulated to create an arbitrarily rich harmonic spectrum, depending on an FM index. The time-varying formant is generated by generating a time-varying combination of the first and second harmonic sound signals, weighting the first and second harmonic sound signals in accordance with their spectral proximities to the formant frequency. One or more of the harmonic numbers are updated when the time-varying formant frequency passes the frequency of either sound signal.

Methods and apparatus for translating duty cycle information in duty-cycle-modulated signals to higher frequencies or higher data rates. An exemplary duty cycle translator includes a duty cycle evaluator, a high-speed digital counter, and a comparator. The duty cycle evaluator generates a first digital number representing a duty cycle of a low-frequency input duty-cycle-modulated (DCM) signal. The comparator compares the first digital number to a second digital number generated by the high-speed digital counter, and generates, based on the comparison, an output DCM signal having a higher frequency or data rate than the frequency or data rate of the low-frequency input DCM signal but a duty cycle that is substantially the same as the duty cycle of the low-frequency input DCM signal.

A communications transmitter includes a baseband processor configured to generate amplitude, angle, in-phase and quadrature baseband signals and a combination modulator that is configurable to modulate in the polar domain and, alternatively, in the quadrature domain. The combination modulator includes a quadrature modulator and a separate and distinct angle modulator that is configured to serve as a local oscillator for the quadrature modulator. In one embodiment of the invention the combination modulator is configured to modulate in the quadrature domain when the transmitter is operating according to a first communications condition (e.g., first transmit power level or first modulation scheme) and is configured to modulate in the polar domain when the transmitter is operating according to a second communications condition (e.g., second transmit power level or second modulation scheme).

A device for mixing multiple (N) pulse density modulated (PDM) bit streams of a bit rate, the device comprises an input logic, an error accumulation circuit, an error correction circuit and an adder of more than N bits; wherein the device is arranged to output an output PDM bit stream that represents a mixture of the multiple input PDM bit streams; wherein the output PDM bit stream comprises a plurality of output PDM bits, wherein a certain output PDM bit of a plurality of output PDM bits that form the output PDM bit stream is generated during a certain clock cycle; wherein the input logic is arranged to select, during each fraction of the certain clock cycle, a current bit of a selected PDM bit stream, wherein different PDM bit streams are selected during different fragments of the certain clock cycle; wherein the error accumulation circuit is arranged to store intermediate values during a first fraction till a penultimate fraction of the certain clock signal and to store a last value during a last fraction of the certain clock signal.

A frequency modulating path for generating a frequency modulated clock includes a direct feed input arranged for directly modulating frequency of an oscillator, and a compensating feed input arranged for compensating effects of frequency modulating on a phase error; wherein the compensating feed input is resampled by a down-divided clock that is an integer edge division of the oscillator. A reference phase generator for generating a reference phase output includes a resampling circuit, an accumulator and a sampler. The resampling circuit is for resampling a modulating frequency command word (FCW) input to produce a plurality of samples. The accumulator is for accumulating the samples to generate an accumulated result. The sampler is for sampling the accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein the reference phase output is updated according to at least the sampled result.

A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word.

Embodiments of digital high-speed bi-phase modulator and method for bi-phase modulation are generally described herein. In some embodiments, the digital high-speed bi-phase modulator comprises a high-speed digital divider, a high-speed digital multiplexer, and matched signal paths provided between the divider and the multiplexer. The high-speed digital divider is configured to receive a carrier signal and generate complementary output signals. The high-speed digital multiplexer is configured to switch between the complementary output signals and generate a bi-phase modulated output at a carrier frequency (fc) modulated with a bi-phase code. The bi-phase code may be provided to control inputs of the multiplexer.

Provided is a method of generating a driving signal for driving a dual mode supply modulator for a power amplifier. The method includes obtaining an envelope of a complex baseband signal to be transmitted, comparing the envelope of the complex signal with a preset threshold value, when a current envelope of the complex signal is the preset threshold value or greater or when there is a result having the preset threshold value or greater in previous N comparisons, outputting a digital board output signal configured with a first logic level through a digital-to-analog converter; and when the current envelope of the complex signal is smaller than the preset threshold value and when there is no result having the preset threshold value or greater in the previous N comparisons, outputting a digital board output signal configured with a second logic level through the digital-to-analog converter.

In an embodiment, a method of producing a multi-level RF signal includes producing plurality of pulse-width modulated signals based on an input signal. The method further includes driving a corresponding plurality of parallel amplifiers with the plurality of pulse-width modulated signals by setting a parallel amplifier to have a first output impedance when a corresponding pulse-width modulated signal is in an active state and setting the parallel amplifier to have a second output impedance when the corresponding pulse-width is in an inactive state. The method also includes phase shifting the outputs of the plurality of parallel amplifiers, wherein phase shifting transforms the second output impedance into a third impedance that is higher than the second output impedance, and combining the phase shifted outputs.

According to some embodiments, a method and apparatus are provided to vary a clock signal frequency for a first time period between a lower limit of a range of problematic frequencies and a frequency lower than the lower limit, and vary the clock signal frequency for a second period of time between an upper limit of the range of problematic frequencies and a frequency greater than the upper limit.

A modulation apparatus for a class D switching amplifier is capable of reducing power consumption of an Electro-Migration Interface (EMI) of an output end and a gate driver end in a zero input signal. The modulation apparatus for a class D switching amplifier includes a control unit for detecting and outputting a control signal which is a common signal component of a first modulation signal modulated by using a first input signal and a second modulation signal modulated by using a second input signal; and is characterized by feedback of a first output signal, a second output signal and a common output signal outputted by using the first modulation signal, the second modulation signal and the control signal through an input of the modulation apparatus.

A communications system includes a target receiver having a passband and configured to receive an intended signal within the passband. The communications system also includes a jammer configured to jam the target receiver from receiving the intended signal. The jammer has at least one antenna, a jammer receiver coupled to the at least one antenna, a jammer transmitter coupled to the at least one antenna, and a controller configured to cooperate with the jammer receiver. The controller is configured to detect the intended signal and to generate an interfering signal comprising a continuous phase modulation (CPM) waveform having a constant envelope so that the interfering signal at least partially overlaps the passband of the target receiver.

In various embodiments, systems and methods for generating high-precision pulse-width modulation include a delay-locked loop comprising multiple delay units having time-variable delays, control logic for selecting a subset S of the multiple delay units to thereby generate a time-invariant shift amount having a precision finer than that of a system clock and circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform.

A modulation method is provided. The modulation method includes the steps of receiving multiple sinusoidal signals, obtaining the maximum value of the sinusoidal signals, obtaining the median value of the sinusoidal signals, and obtaining the minimum value of the sinusoidal signals within a period to generate a difference between the maximum value and the minimum value, generating a difference according to an upper limit and a lower limit of a predetermined comparison value, and comparing the two differences to generate an optimized modulation signal.

An ultra-wide band frequency modulator is disclosed. The frequency modulator includes a direct modulation phase lock loop that receives a small component. The frequency modulator also includes a delay module that produces a plurality of delay lines. The frequency modulator further includes an edge selector that receives a large component and the plurality of delay lines.

The present invention relates to a digital modulation method and a corresponding modulator. The modulator comprises a transcoder (110) followed by a FIFO register (120) and a 2-PSK modulator (130). The transcoder codes a binary word of fixed size into a code word of variable size using a transcoding table. The transcoding table codes at least one first binary word, leading to a first number of phase transitions at the output of the modulator, into a second word of size greater than that of the first word, leading to, at the output of the modulator, a second number of phase transitions less than the first number of phase transitions.

The present invention provides a digitally controlled, current starved, pulse width modulator (PWM). In the PWM of the present invention, the amount of current from the voltage source to the ring oscillator is controlled by the proposed header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, where the duty cycle can vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations.

Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

A memristor-based emulator including a memristor circuit for use in digital modulation that includes a first current feedback operational amplifier (CFOA) having multiple terminals in communication with a capacitor Cd and in further communication with a resistor Ri. A second CFOA having multiple terminals is in communication with the first CFOA and is adapted to be in further communication with a voltage vM to provide an input current iM for integration by a capacitor Ci. A nonlinear resistor is in communication with the second CFOA. A third CFOA having multiple terminals is in communication with the nonlinear resistor and is in further communication with the first CFOA and a resistor Rd. The third CFOA and the resistor Rd act as an inverting amplifier associated with the nonlinear resistor to increase a current gain to increase a difference between ON and OFF values of a resistance of a realized memristor.

A method for phase modulation of a carrier signal from a transmitter to a contactless transponder in which data is coded as consecutive symbols, each corresponding to a predefined number of carrier cycles, and in which a symbol time is at least two cycles of the carrier signal includes, at the transmitter, spreading a phase jump of a symbol in relation to a preceding symbol over a first part of the symbol time. The establishment of the phase jump is completed in the first part of the symbol time. The periods of the cycles are constant during a second part of the symbol time.

A modulator which has a first terminal to receive a carrier signal, a second terminal to receive a first control signal to control a frequency band of the carrier signal and a third terminal to receive a second control signal to control a modulation depth of the carrier signal.

An electromagnetic actuator comprising a core moving between a latched position and an open position, a permanent magnet, a coil designed to generate a first magnetic control flux to move the core from an open position to a latched position, and a second magnetic control flux designed to facilitate movement of the moving core from the latched position to the open position. The permanent magnet is positioned on the moving core so as to be at least partly outside the fixed magnetic circuit in which the first magnetic control flux flows in the open position, and to be at least partly inside the fixed magnetic circuit used for flow of a magnetic polarization flux of the magnet in the latched position.

A driver for a switch in a GIS (Gas Insulation Switchgear) includes a motor, a shaft connected with a moving contact of the switch, a gear connected with one terminal of the shaft and configured to transfer power of the motor to cause the shaft to reciprocate the moving contact through the shaft, a cam spline combined with the shaft and spaced apart from the gear, and a micro-switch connected with the cam spline and configured to control an operation of the motor.

The high voltage relay consists of a main body (1). One set of electrical contacts (2a, 2b) upper and lower respectively. High voltage connections to connect the voltage being switched (3a, 3b) are electrically connected to the upper and lower contacts respectively. Several size options for the electrical contacts will allow for a wide range of currents. A cylinder (4) driven by a fluid (e.g. Air, Nitrogen, Hydraulic fluid) moves the electrical contacts together during the ON state of the device. During the OFF state of the device the cylinder moves the electrical contacts apart to isolate the switch voltage. The greater the High Voltage being switched the greater the distance the electrical contacts must be moved apart in the OFF state. The cylinder is supplied the fluid power from a small solenoid (5) on the device. This solenoid has control voltage connections to actuate the device.

Provided is a sector gear including: a drive gear having a drive part that forms a part of a circle and has a plurality of teeth and a non-drive part that forms a remaining part of the circle and provides a non-contact angle of at least approximately 90 degrees; first and second movers forming a disconnector and a grounded breaking switch, respectively; and first and second driven gears engaged with the drive gear and respectively engaged with the first and second movers and configured to make the first mover or the second mover operate in conjunction with the drive part of the drive gear according to a direction of rotation of the drive gear, wherein an intermediate angle between the first and second movers is between approximately 90-135 degrees. The present invention can reduce the size of the gas-insulated switchgear having the sector gear.

A gas insulated switchgear includes an enclosure, a first fixed conductor, one side of the first fixed conductor being bent at a right angle and another side of the first fixed conductor being fixed on one side of the enclosure, a second fixed conductor configured to be spaced apart from the first fixed conductor and configured to be fixed on another side of the enclosure, a screw configured to form an axis on inner of the enclosure and being spaced apart from the first and second fixed conductors and a movable conductor configured to move along the axis through a rotation of the screw, one side of the movable conductor being in contact with the second fixed conductor.

A gas-insulated type circuit breaker including a housing defining a gas volume for a dielectric insulation gas; a first arcing contact member and a second arcing contact member, wherein the first arcing contact member and the second arcing contact member are movable relative to each other along an axis; a first nominal contact member and a second nominal contact member, wherein the first nominal contact member and the second nominal contact member are movable relative to each other along the axis; and a first nominal contact shielding arrangement including an inner shield member and an outer shield member, wherein the inner shield member and the outer shield member are arranged coaxially about the axis. The first nominal contact member is arranged co-axially between the inner shield member and the outer shield member, and is movable relative to the inner shield member and to the outer shield member.

A circuit breaker includes a first contact and a second contact. An electric arc zone is disposed between the contacts. A feed channel opens into the electric arc zone, connecting the electric arc zone to a hot gas reservoir volume. The hot gas reservoir volume, in turn, is connected to a compression volume. An outflow opening is disposed in a wall of the compression volume. The outflow opening is permanently open, at least in a contacting state of the contacts.

Circuit breakers include an arc chamber and an arc chute comprising a plurality of arc plates in the arc chamber. The circuit breakers also include a line conductor assembly with at least one arc runner attached to a line conductor in the arc chamber. The arc runner can extend below but adjacent to a bottom arc plate to thereby guide a respective arc into the arc chute.

A gas-insulated circuit interrupter is disclosed, the interrupter having an improved design for quenching electrical arcs. The interrupter includes a first contact and a second contact configured to alternatively connect to and disconnect from the first contact. One or both of the contacts are at least partially contained in an arcing chamber. The arcing chamber includes the point at which the contacts connect during current-carrying operation of the interrupter. The arcing chamber is at least partially surrounded by a heating chamber for accommodating a quenching gas. A channel connects the heating chamber and the arcing chamber and is positioned to direct the quenching gas toward the first contact and the second contact arcing area. One or more valves direct gas from the arcing chamber to the heating chamber when the interrupter is operated to interrupt a current.

A profiled arc splitter plate for a switch having a fixed contact and a movable contact is provided to increase electromagnetic attractive forces on the arc generated during contact separation. The plate (300) comprises a body (306) defining an operatively inverted substantially V-shaped recess having a center notch (302) provided at the vertex of the recess and at least one protrusion (304) defined on either side of the center notch (302) along the inclined side walls of the recess, the movable contact of the switch displaceable through the recess without contacting the inclined side walls, in a spaced apart manner from the protrusions (304) and the center notch (302). Chamfers 308 are provided at an end of the plate (300) proximal to the vertex of the recess to provide an exit for hot gases towards the vent of the arc chamber.

A removable faceplate for a portable electronic device is provided. The faceplate permits a user to change the physical appearance of a surface of the device while retaining access to the mechanisms for controlling the function of the device. Preferably, the removable faceplate and electronic device are configured with a means for association and dissociation that can be activated without the use of a tool and the means is not visible when the faceplate is attached. Additionally, an improved packaging system is provided to enable a vendor or manufacturer to package faceplates with the devices that they will cover and to allow substitution of faceplates in the packaging without disturbing the packaging of the electronic device itself. Further, there is a method for distribution of the packaging system.

Containers and dispensers for wiping substrates, and wet wiping substrates in particular, have been provided with lids, the containers have been susceptible to leakage, or difficulties in dispensing the contents. Provided is a refillable container for storing and dispensing wiping substrates. A refill cartridge containing wiping substrates having a peelable seal disposed on a first surface and a second surface for forming a seal with the container lid is provided.

A packaging device includes first and second thermoplastic films superposed with each other, wherein predetermined portions of the thermoplastic films are bonded creating a plurality of fluid containers, a plurality of check valves each connected to a corresponding fluid container, a fluid passage in a first direction connected to the check valves, and a second border between an inflated section including the plurality of fluid containers and an uninflated section, wherein the first and second thermoplastic films are folded and two side edges of the films are bonded and a first portion of a first border connecting the inflated section to a second section is folded and an overlapped portion of the first portion is bonded leaving a remaining portion of the first border unbonded wherein the uninflated section forms a loop, and wherein the uninflated section forming the loop is folded into the inflated section to form a lining.

A multi-standard flash-memory-card carrier is about the same size as a thick credit card and fits into a wallet. The multi-standard flash-memory-card carrier has bays that accept flash-memory cards. Larger bays on one side receive SD cards and a Memory Stick Duo card, while micro bays on another side of the carrier receive microSD cards and Memory Stick Micro cards. A carrier spine sandwiched between top and bottom covers has openings forming the bays. Spring-clip tabs on spring-clip fingers fit into notches on the side of the flash-memory cards to secure the flash-memory cards into the multi-standard flash-memory-card carrier to prevent loss. The spring-clip fingers are movable parts of the carrier spine that are deformed during insertion of the flash-memory cards. Both micro and standard flash-memory cards can be carried in the same multi-standard flash-memory-card carrier that can be placed in plastic sleeves for credit cards in a person's wallet.

A novel packaging for flat media having substantially square panels wherein at least one of the panels is adapted to form a compartment for storing a phonographic record, an audiovisual record or any flat media. The arrangement of the square panels enables the package to be folded in a compact, flat configuration for ease of storage and shipping. When erected, the package forms a cube that could be used as additional storage. The cube may be erected with either of the sides of the panels visible so as to afford greater opportunity for display.

A catheter assembly including an elongate member having a proximal end and a distal end. The distal end has at least one drainage opening. A hydrophilic coating is provided on at least a portion of the elongate end of the catheter. A fluid containing member is provided and is either arranged on the elongate member or within a separate area of the container. The fluid containing member contains sufficient hydrating fluid to hydrate the coating of the catheter. A container contains the elongate member and the fluid containing member and incorporates at least one foil layer to prevent evaporation of the hydrating fluid. A method of using the catheter includes inserting a catheter into a user's body and draining fluid from the user's body.