IFTTT (If This Than That), a web-based software that automates and connects over 600 online services/software raised a $24M Series C led by Salesforce. Other investors include IBM and the Chamberlain Group and Fenox Venture Capital.

The latest round brings IFTTT’s funding to $63M and it will use the funding proceeds to provide integration for enterprise and IoT services and hiring. In IFTTT’s platform, applets are code/script users need to deploy to integrate two or more services (such Google Drive’s integration with Twitter/Facebook).

Investment in IFTTT reveals that Salesforce is consolidating its presence in enterprise IoT space. It also acquired Mulesoft, an integration platform that rivals Microsoft’s BizTalk.

IBM’s investment in IFTTT is also noteworthy as the former is pushing its IBM Watson IoT platform. The following statement also shows its keen interest in IFTTT.

Other recent investments in IoT companies include $30M Series B of Armis and Myriota's $15M for its IoT satellite-based connectivity platform.

For latest IoT funding and product news, please visit our IoT news section.

Owlet, a connected-baby care company raised a $24 million Series B investment from Trilogy Equity Partners, with participation from existing investors, including Eclipse Ventures, Broadway Angels, and Enfield Ventures, and the addition Pelion Venture Partners.

Owlet’s core product is a baby sock that contains a smart sensor. The sensor monitors pulse oximetry, a technology used in hospitals to measure an infant's heart rate and blood oxygen levels. The vital signs are communicated to parents’ smartphone via Bluetooth connection. The product retails for $299 and parents can also choose from monthly payment plans.

Other IoT-health startups using sensors to monitor vital signs include Aifloo, a company selling wrist-bands for elders and Air by Propeller, a smart health company that provides an API to predict local asthma conditions.

A complete product package of Owlet monitor includes three fabric socks, smart sock sensor, a base station (which rings an alarm if a baby’s vital signs are abnormal), and charging cords.

Before the company raised the latest round, it closed a $15 million Series B round in late 2016. The recent investment brought Owlet’s total equity funding to $46M. Owlet plans to use the growth capital to launch more baby care products.

Vesper, the maker of piezoelectric sensors used in microphone production and winner of CES Innovation Award 2018 raised a $23M Series B round. American Family Ventures led the investment with participation from Accomplice, Amazon Alexa Fund, Baidu, Bose Ventures, Hyperplane, Sands Capital, Shure, Synaptics, ZZ Capital and some undisclosed investors.

Vesper’s innovative sensors can be used in consumer electronics like TV remote controls, smart speakers, smartphones, intelligent sensor nodes, and hearables. The company will use the funding proceeds to scale-up its functions like mass production of its microphones and support expanded research and development, hiring, and establishing international sales offices.

The main product of Vesper is VM1000, a low noise, high range,single-ended analog output piezoelectric MEMS microphone. It consists of a piezoelectric sensor and circuitry to buffer and amplify the output.

The hot-selling product of Vesper is VM1010 with ZeroPower Listening which is the first MEMS microphone that enables voice activation to battery-powered consumer devices.

The unique selling point of Vesper’s products is they are built to operate in rugged environments that have dust and moisture.

"Vesper's ZeroPower Listening capabilities coupled with its ability to withstand water, dust, oil, and particulate contaminants enables users that have never before been possible," said Katelyn Johnson, principal of American Family Ventures. "We are excited about Vesper's quest to transform our connected world, including IoT devices."

Other recent funding news include $24 raised by sensor-based baby sock maker Owlet, IFTTT banks $24M from Salesforce to scale its IoT Enterprise offering, and Intel sells its Wind River Software to TPG.

Amber Solutions, an IoT product company that sells smart outlets, switches and circuit breakers closed Series A Preferred Stock round of financing that equals $3.3M in gross proceeds. Amber will use the funds to support the commercial development of Amber's core technologies.

One of Amber’s product is solid-state circuit interrupter (GFCI) that basically stops harmful levels of electricity from passing through a person. It operates as a safety device alerting the homeowner of electrocution incidents in real time.

Amber Solutions’ core markets are builders that prepare smart home/smart building ready infrastructure, certified electrical contractors or remodelers, and electrical manufacturers.

Other latest funding news include Owlet’s $24M Series B, Axonize’s $6M Series A round and addition of Deutsche Telekom as its strategic investor, and $30M Series B raised by Palo Alto-based Armis.

Smart baby monitor company Nanit raised a $14M Series B round led by Jerusalem Venture Partners (JVP). Other investors that participated include existing investors Upfront Ventures, RRE Ventures, Vulcan Capital and Vaal Investment Partners. The latest investment brings total equity funding of Nanit to $30M.

Nanit announced it will use the funding proceeds to expand its team of computer vision and machine learning engineers and grow its sales in Europe and Canada.

Nanit’s baby monitor helps new parents oversee nursery conditions as it has built-in temperature and humidity sensors. The camera lets parents remotely monitor baby’s crib whereas sound and motion are detected via smart sensors.

The monitor’s insights can be accessed via an accompanying mobile app. Nanit charges $10 per month for its premium package.

The key use cases of Nanit’s baby monitoring technology include sleep insights, behavioral analysis, expert guidance, and nightly video summaries. The company currently sells its smart monitors via its website.

Microsoft announced it has acquired Semantic Machines, a conversational AI startup providing chatbots and AI chat apps founded in 2014 having $20.9 million in funding from investors. The acquisition will help Microsoft catch up with Amazon Alexa, though the latter is more focused on enabling consumer applications of conversational AI.

Microsoft will use Semantic Machine’s acquisition to establish a conversational AI center of excellence in Berkeley to help it innovate in natural language interfaces.

Microsoft has been stepping up its products in conversational AI. It launched the digital assistant Cortana in 2015, as well as social chatbots like XiaoIce. The latest acquisition can help Microsoft beef up its ‘enterprise AI’ offerings.

As the use of NLP (natural language processing) increases in IoT products and services, more startups are getting traction from investors and established players. In June last year, Josh.ai, avoice-controlled home automation software has raised $8M.

Followed by it was SparkCognition that raised $32.5M Series B for its NLP-based threat intelligence platform.

It appears Microsoft’s acquisition of Semantic Machines was motivated by the latter’s strong AI team. The team includes technology entrepreneur Daniel Roth who sold his previous startups Voice Signal Technologies and Shaser BioScience for $300M and $100M respectively. Other team members include Stanford AI Professor Percy Liang, developer of Google Assistant Core AI technology and former Apple chief speech scientist Larry Gillick.

Arduino’s MKR family of products got two new wireless connectivity boards added to its range of products. These include MKR WiFi 1010 and MKR NB 1500, both aimed at streamlining IoT product/service development.

Arduino’s blog notes that “the Arduino MKR WiFi 1010 is the new version of the MKR1000 with ESP32 module on board made by U-BLOX.”

MKR WiFi 1010: For prototyping of WI-FI based IoT applications

The core difference of MKR WiFi 1010 compared to MKR WiFi 1000 is that the former can be put to use in production-grade IoT apps and it has ESP32-based module manufactured by u-blox. The former enables to add 2.4GHz WiFi and Bluetooth capability to the application. Additionally, it comes with a programmable dual-processor system (an ARM processor and a dual-core Espressif IC).

MKR NB 1500: For on-field monitoring systems and remote-controlled LTE-enabled modules

The Arduino MKR NB 1500 is based on new low-power NB-IoT (narrowband IoT) standard. This makes it appropriate for IoT apps running over cellular/LTE networks.

Key use cases of this board are remote monitoring systems and remote-controlled LTE-enabled modules. It supports AT&T, T-Mobile USA, Telstra, Verizon over the Cat M1/NB1 deployed bands 2, 3, 4, 5, 8, 12, 13, 20 and 28.

Arduino also pitches this board to be used in IoT apps which used to rely on alternative IoT networks such as LoRa and Sigfox. It promises to save power compared to GSM or 3G cellular-based connections.

Smart Lock Company LockState raised $5.8M Series A in new investment to fund its aggressive sales and marketing and partner development plan. The company previously raised $740K seed round and $1M in a round led by angel investors. The lead investor in latest round was Iron Gate Capital. Other investors include Kozo Keikaku Engineering Inc, Nelnet and Service Provider Capital.

The company’s Wi-Fi-enabled RemoteLock is used by 1000s of Airbnb and other vacation rental hosts. It helps hosts remotely provide access to guests. Locking/unlocking codes can be generated via a host’s computer or smartphone.

RemoteLock’s prices start at $299 which is its algorithmic ResortLock. The most pricey lock by LockState is its ‘RemoteLock 7i Black WiFi Commercial Smart Lock’ which costs $479.

Another core product of LockState is its cloud-based remote access platform for internet-enabled locks. It implies users can remotely manage their (internet-enabled) locks via LockState’s cloud platform.

Unlike smartphones and watches, customers don’t look forward to upgrading their smart locks or buying one when new models are launched. Thus, smart lock companies offset this disadvantage by partnering with property management and short-term rental companies to get new customers.

LockState has partnered with vacation rental brands like Airbnb, HomeAway, and other listing partners to automate guest access.

Igloohome a Singapore-based smart lock company also raised an investment of $4M in April this year.

EV Ultimo launches platform to assist brands, buyers, stakeholders in the Electric Vehicles ecosystem

[SAPS] - Polokwane based Hawks Serious Commercial Crime Investigation in collaboration with National Traffic Anti-corruption Unit arrested 11 suspects between the ages of 27 and 57 for alleged fraud at various Provinces during operation "SISFIKILE".

[SAPS] - Five suspects are appearing in the Kariega Magistrate's Court today, after they were arrested and found in possession of cycads with an estimated value of R1 Million on Friday 08 November 2024.

[SAPS] One hundred and seventy one (171) murder suspects, 261 attempted murder suspects and 250 suspected rapists were among 12 593 suspects who were arrested during various operations by police in KwaZulu-Natal in the month of October. During such operations police also managed to recover 345 firearms and 2 998 rounds of ammunition of various calibre of firearms. Among the recovered firearms were 23 rifles and 17 homemade illegal guns.

[SAPS] SAPS members' continued efforts to prevent and detect crime yielded the following successes within the Joe Gqabi District as part of Operation Shanela during the week and start of the weekend .

[allAfrica] We are excited to share the momentous news that Cape Town Pride has officially won the bid to host WorldPride 2028. This significant event is a global celebration of LGBTQ+ pride and rights, marking a pivotal milestone not only for the LGBTQ+ community in the city but also for the entire African continent. This victory positions Cape Town as a leading symbol of inclusivity and diversity, showcasing its commitment to advancing a welcoming environment for all.

[The Conversation Africa] South Africa's finance minister, Enoch Godongwana, announced in his October mid-term budget policy statement that cabinet had approved funding for an early retirement programme to reduce the public sector wage bill. R11 billion (about US$627 million) will be allocated over the next two years to pay for the exit costs of 30,000 civil servants while retaining critical skills and promoting the entry of younger talent.

[DA] Note to editors: Please find attached soundbite by Ian Cameron MP.

[SAnews.gov.za] Twenty-three people in Gauteng have died as a result of food borne-related poisoning after consuming food from spaza shops.

[SAnews.gov.za] With the United Nations Framework Convention on Climate Change (COP29) taking place this week, South Africa expects the COP29 Presidency to enhance efforts to finalise the New Collective Quantified Goal on Finance (NCQG), which is a matter of great importance for developing economies.

[Premium Times] In September, Tyla made headlines at the MTV Video Music Awards (VMAs) for winning the "Best Afrobeats," but she stirred debate by clarifying that she identified with the Amapiano genre rather than Afrobeats

[State Department] U.S. Ambassador-at-Large to Monitor and Combat Trafficking in Persons Cindy Dyer will travel to Madagascar November 13-16 and South Africa November 17-21.

[Daily Maverick] Water and Sanitation Minister Pemmy Majodina held an urgent meeting on Sunday with Gauteng Premier Panyaza Lesufi and Johannesburg Mayor Dada Morero to address severe water shortages affecting Johannesburg communities.

[Daily Maverick] Office of the Chief Justice reveals Constitutional Court has been unable to sit because of unreliable water supply. This article is free to read.Sign up for free or sign in to continue reading.Unlike our competitors, we don't force you to pay to read the news but we do need your email address to make your experience better.Create your free account or sign in FAQ | Contact Us Nearly there! Create a password to finish signing up with us: You want to receive First Thing, our flagship daily newsletter. Opt

[Namibian] Russian company Rosatom and South African AllWeld Nuclear and Industrial are joining forces to promote the sustainable development of nuclear energy in Africa.

[allAfrica]

[COSATU] The Congress of South African Trade Unions (COSATU) welcomes the slight drop in the expanded unemployment rate from 42.6% in the second quarter to 41.9% in the third quarter of this year.

[The Conversation Africa] Despite the flaws in the latest novel by South African writer Nthikeng Mohlele, there is something alluring about Revolutionaries' House. It is Mohlele's most political novel, and the parallels drawn between love and politics - and their pitfalls - are intriguing.

[GroundUp] The education department says there's only one SETA official assisting all nine provinces

PCI-SIG DevCon 2024 – 32^nd Anniversary

For more than a decade, Cadence has been well-known in the industry for its strong commitment and support for PCIe technology. We recognize the importance of ensuring a robust PCIe ecosystem and appreciate the leadership PCI-SIG provides. To honor the 32^nd anniversary of the PCI-SIG Developer’s Conference, Cadence is announcing a complete PCIe 7.0 IP solution for HPC/AI markets.

Why Are Standards Like PCIe So Important?

From the simplest building blocks like GPIOs to the most advanced high-speed interfaces, IP subsystems are the lifeblood of the chipmaking ecosystem. A key enabler for IP has been the collaboration between industry and academia in the creation of standards and protocols for interfaces. PCI-SIG drives some of the key definitions and compliance specifications and ensures the interoperability of interface IP.

HPC/AI markets continue to demand high throughput, low latency, and power efficiency. This is fueling technology advancements, ensuring the sustainability of PCIe technology for generations to come. As a close PCI-SIG member, we gain valuable early insights into the evolving specs and the latest compliance standards. PCIe 7.0 specifications and beyond will enable the market to scale, and we look forward to helping our customers build best-in-class cutting-edge SoCs using Cadence IP solutions.

Figure 1. Evolution of PCIe Data Rates (source PCI-SIG)

What’s New This Year at DevCon?

At DevCon ’24, the PCIe 7.0 standard will take center stage, and Cadence is showing off a full suite of IP subsystem solutions for PCIe 7.0 this year.

What Sets Cadence Apart?

At Cadence, we believe in building a full subsystem for our testchips with eight lanes of PHY along with a full 8-lane controller. Adding a controller to our testchip significantly increases the efficiency and granularity in characterization and stress testing and enables us to demonstrate interoperability with real-world systems. We are also able to test the entire protocol stack as an 8-lane solution that encompasses many of the applications our customers use in practice. This approach significantly reduces the risks in our customers’ SoC designs.

Figure 2: Piper - Cadence PHY IP for PCIe 7.0

Figure 3: Industry’s first IP subsystem for PCIe 7.0

Which Market Is This For?

At a time when accelerated computing has gone mainstream, PCIe links are going to take on a role of higher importance in systems. Direct GPU-to-GPU communication is crucial for scaling out complex computational tasks across multiple graphics processing units (GPUs) or accelerators within servers or computing pods. There is a growing recognition within the industry of a need for scalable, open architecture in high-performance computing. As AI and data-intensive applications evolve, the demand for such technologies will likely increase, positioning PCIe 7.0 as a critical component in the next generation of interface IP.

Here's a recent article describing a potential use case for PCIe 7.0.

Figure 4: Example use case for PCIe 7.0

Why Are Optical Links Important?

It takes multiple buildings of data centers to train AI/ML models today. These buildings are increasingly being distributed across geographies, requiring optical fiber networks that are great at handling the increased bandwidth over long distances. However, these optical modules soon hit a power wall where all the budgeted power is used to drive the signal from point A to point B, and there is not enough power left to run the actual CPUs and GPUs. Such scenarios create a need for non-retimed, linear topologies. Linear Pluggable Optics (LPO) links can significantly reduce module power consumption and latency when compared to traditional Digital Signal Processing (DSP) based retimed optical solutions, which is critical for accelerating AI performance. Swapping from DSP-based solutions to LPO results in significant cost savings that help drive down expenditure due to lower power and cooling requirements, but this requires a robust high-performance ASIC to drive the optics rather than retimers/DSP.

To showcase the robustness of Cadence IP, we have demonstrated that our subsystem testchip board for PCIe 7.0 can successfully transmit and receive 128GT/s signals through a non-retimed opto-electrical link configured in an external loopback mode with multiple orders of margin to spare.

Figure 5: Example of ASIC driving linear optics

Compliance Is Key

For PCIe 6.0, the official compliance program has not started yet; this is typical for the SIG where the official compliance follows a few years after the spec is ratified to give enough time for the ecosystem to have initial products ready, and for test and equipment vendors to get their hardware/software up and running. At this time, PCIe Gen6 implementations can only be officially certified up to PCIe 5.0 level (the highest official compliance test suite that the SIG supports). We have taken our PCIe 6.0 IP subsystem solution to the SIG for multiple process nodes, and they are all listed as compliant. You can run this query on the pcisig.com website under the Developers->Integrators list by making the following selections:

Due to space limitations, not all combinations could be tested at the May workshop (e.g., N3 root port) – this will be tested in the next workshop.

Also, the SIG just held an “FYI” compliance event this week to bring together the ecosystem for confidential testing (no results were reported, and data cannot be shared outside without violating the PCI-SIG NDA). We participated in the event with multiple systems and can report that our systems have done quite well. The test ecosystem is not mature yet, and a few more FYI workshops will be conducted before the official compliance for 6.0 is launched. We have collaborated with all the key test vendors for electrical and protocol testing throughout the year. As early as the middle of last year, we were able to provide test cards to all these vendors to demo PCIe 6.0 capabilities in their booths at various events. Many of them recorded these videos, and they can be found online.

• Cadence Subsystem IP for PCIe 6.0: Protocol and Electrical Testing
• Cadence Subsystem IP for CXL Protocol Test Demo
• Cadence Subsystem IP for CXL2.0/3.0 Protocol Test Demo
• Cadence Subsystem IP for PCIe 6.0: Protocol Stack Demo

More at the PCI-SIG Developers Conference

Check us out at the PCI-SIG Developer’s conference on June 12 and 13 to see the following demonstrations:

• Robust performance of Cadence IP for PCIe 7.0 transmitting and receiving 128GT/s signals over non-retimed optics
• Capabilities of Cadence IP for PCIe 7.0 measured using oscilloscope instrumentation detailing its stable electrical performance and margin
• The reliability of Cadence IP for PCIe 6.0 interface using Test Equipment to characterize the PHY receiver quality
• A PCI-SIG-compliant Cadence IP subsystem for PCIe 6.0 optimized for both power and performance

As a leader in PCI Express, Anish Mathew of Cadence will share his valuable insights on an important topic: “Impact of UIO ECN on PCIe Controller Design and Performance,” highlighting the strides made by the Cadence design team in achieving this implementation.

Figure 6: Cadence UIO Implementation Summary

Summary

Cadence showcased PCIe 7.0-ready IP at PCI-SIG Developers Conference 2023 and continues to lead in PCIe IP development, offering complete solutions in advanced nodes for PCIe 7.0 that will be generally available early next year. With a full suite of solutions encompassing PHYs, Controllers, Software, and Verification IP, Cadence is proud to be a member of the PCI-SIG community and is heavily invested in PCIe. Cadence was the first IP provider to bring complete subsystem solutions for PCIe 3.0, 4.0, 5.0, and 6.0 with industry-leading PPA and we are proud to continue this trend with our latest IP subsystem solution for PCIe 7.0, which sets new benchmarks for power, performance, area, and time to market.

The market is trending towards integrating and stacking multiple chiplets into a single package to meet the growing demands of speed, connectivity, and intelligence.  However, designing and signing off chiplets and packages individually is time-...(read more)

PCI-SIG DevCon 2024 was a great success for Cadence. We posted the blog, Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon ‘24 a day before the event to advertise our IP solutions for PCIe 7.0, which resulted in a lot of extra traffic at our booth. All of the attendees were excited to see Cadence demonstrate the robustness of 128GT/s PCIe 7.0 IP's TX and RX capabilities over a real-world, low-latency, non-retimed, linear optics connector. We achieved and maintained a consistent, impressive pre-FEC BER of ~3E-8 (PCIe spec requires 1E-6) for the entire duration of the event, spanning over two full days with no breaks. This provides an ample margin for RS FEC. As seen in the picture below, the receiver Eye PAM4 histograms have good linearity and margin. This is the world’s first stable demonstration of 128 GT/s TX and RX over off-the-shelf optical connectors—by far the main attraction of DevCon this year.

Cadence 128 GT/s TX and RX capability over optics

Block diagram of Cadence PHY for PCIe 7.0 128 GT/s demo setup with linear pluggable optics

As a leader in PCIe, our PCIe controller architect Anish Mathew shared his valuable insights on an important topic: “Impact of UIO ECN on PCIe Controller Design and Performance,” highlighting the strides made by the Cadence design team in achieving this implementation.

Anish Mathew presenting “Impact of UIO ECN on PCIe Controller Design and Performance”

In summary, Cadence had a dominating presence on the demo floor with a record number of PCIe demos:

• PCIe 7.0 over optics
• PCIe 7.0 electrical
• PCIe 6.0 RP/EP interop back-to back
• PCIe 6.0 protocol in FLIT mode with Lecroy Exerciser (at Cadence booth)
• PCIe 6.0 protocol in FLIT mode (at the Lecroy booth)
• PCIe 6.0 JTOL with Anritsu and Tektronix equipment (at Tektronix booth)
• PCIe 6.0 protocol with Viavi Protocol Analyzer (at Viavi booth)
• PCIe 6.0 System Level Interop Demo with Gen5 platform (at SerialTek booth)

The Cadence team and its partners did a great job in coordinating and setting up the demos that worked flawlessly. This was the culmination of many weeks of hard work and dedication. Four different vendors featured our IP for PCIe 6.0. They attracted a lot of attention and drove traffic back to us.

Highlights of Cadence demos for PCIe 7.0 and 6.0

Cadence team at the PCI-SIG Developers Conference 2024

Thanks to everyone who attended the 32nd PCI-SIG DevCon. We really appreciate your interest in Cadence IP, and a big thanks to our partners and customers for all the positive feedback and for creating so much buzz for the Cadence brand.

In the rapidly evolving landscape of automotive electronics, traditional monolithic design approaches are giving way to something more flexible and powerful—chiplets. These modular microchips, which are themselves parts of a whole silicon system, offer unparalleled potential for improving system performance, reducing manufacturing costs, and accelerating time-to-market in the automotive sector. However, the transition to working with chiplets in automotive electronics is not without its challenges.

Designers must now grapple with a new set of considerations, such as die-to-die interconnect standards, complex processes, and the integration of diverse IPs. Advanced toolsets and standardized design approaches are required to meet these challenges head-on and elevate the potential of chiplets in automotive innovation. In the following discourse, we will explore in detail the significance of chiplets in the context of automotive electronics, the obstacles designers face when working with this paradigm, and how Cadence comprehensive suite of IPs, tools, and flows is pioneering solutions to streamline the chiplet design process.

Unveiling Chiplets in Automotive Electronics

For automotive electronics, chiplets offer a methodology to modularize complex functionalities, integrate different chiplets into a package, and significantly enhance scalability and manufacturability. By breaking down semiconductor designs into a collection of chiplets, each fulfilling specific functions, automotive manufacturers can mix and match chiplets to rapidly prototype new designs, update existing ones, and specialize for the myriad of use cases found in vehicles today.

The increasing significance of chiplets in automotive electronics comes as a response to several industry-impacting phenomena. The most obvious among these is the physical restriction of Moore's Law, as large die sizes lead to poor yields and escalating production costs. Chiplets with localized process specialization can offer superior functionality at a more digestible cost, maintaining a growth trajectory where monolithic designs cannot. Furthermore, chiplets support the assembly of disparate technologies onto a single subsystem, providing a comprehensive yet adaptive solution to the diverse demands present in modern vehicles, such as central computing units, advanced driver-assistance systems (ADAS), infotainment units, and in-vehicle networks. This chiplet-based approach to functional integration in automotive electronics necessitates intricate design, optimization, and validation strategies across multiple domains.

The Complexity Within Chiplets

Yet, with the promise of chiplets comes a series of intricate design challenges. Chiplets necessitate working across multiple substrates and technologies, rendering the once-familiar 2-dimensional design space into the complex reality of multi-layered, sometimes even three-dimensional domains. The intricacies embedded within this design modality mandate devoting considerable attention to partitioning trade-offs, signal integrity across multiple substrates, thermal behavior of stacked dies, and the emergence of new assembly design kits to complement process design kits (PDKs).

To effectively address these complexities, designers must wield sophisticated tools that facilitate co-design, co-analysis, and the creation of a robust virtual platform for architectural exploration. Standardizations like the Universal Chip Interconnect Express (UCIe) have been influential, providing a die-to-die interconnect foundation for chiplets that is both standardized and automotive-ready. The availability of UCIe PHY and controller IP from Cadence and other leading developers further eases the integration of chiplets in automotive designs.

The Role of Foundries and Packaging in Chiplets

Foundries have also pivoted their services to become a vital part of the chiplet process, providing specialized design kits that cater to the unique requirements of chiplets. In tandem, packaging has morphed from being a mere logistical afterthought to a value-added aspect of chiplets. Organizations now look to packaging to deliver enhanced performance, reduced power consumption, and the integrity required by the diverse range of technologies encompassed in a single chip or package. This shift requires advanced multiscale design and analysis strategies that resonate across a spectrum of design domains.

Tooling Up for Chiplets with Cadence

Cadence exemplifies the rise of comprehensive tooling and workflows to facilitate chiplet-based automotive electronics design. Their integrations address the challenges that chiplet-based SoCs present, ensuring a seamless design process from the initial concept to production. The Cadence suite of tools is tailored to work across design domains, ensuring coherence and efficiency at every step of the chiplet integration process.

For instance, Cadence Virtuoso RF subflows have become critical in navigating radio frequency (RF) challenges within the chiplets, while tools such as the Integrity 3D-IC Platform and the Allegro Advanced Multi-Die Package Design Solution have surfaced to enable comprehensive multi-die package designs. The Integrity Signal Planner extends its capabilities into the chiplet ecosystem, providing a centralized platform where system-wide signal integrity can be proactively managed. Sigrity and Celsius, on the other hand, offer universally applicable solutions that take on the challenges of chiplets in signal integrity and thermal considerations, irrespective of the design domain. Each of these integrated analysis solutions underscores the intricate symphony between technology, design, and packaging essential in unlocking the potential of chiplets for automotive electronics.

Cadence portfolio includes solutions for system analysis, optimization, and signoff to complement these domain-specific tools, ensuring that the challenges of chiplet designs don't halt progress toward innovative automotive electronics. Cadence enables designers to engage in power- and thermal-aware design practices through their toolset, a necessity as automotive systems become increasingly sophisticated and power-efficient.

A Standardized Approach to Success with Chiplets

Cadence’s support for UCIe underscores the criticality of standardized approaches for heterogeneous integration by conforming to UCIe standards, which numerous industry stakeholders back. By co-chairing the UCIe Automotive working group, Cadence ensures that automotive designs have a universal and standardized Die-to-Die (D2D) high-speed interface through which chiplets can intercommunicate, unleashing the true potential of modular design.

Furthermore, Cadence champions the utilization of virtual platforms by providing transaction-level models (TLMs) for their UCIe D2D IP to simulate the interaction between chiplets at a higher level of abstraction. Moreover, individual chiplets can be simulated within a chiplet-based SoC context leveraging virtual platforms. Utilizing UVM or SCE-MI methodologies, TLMs, and virtual platforms serve as first lines of defense in identifying and addressing issues early in the design process before physical silicon even enters the picture.

Navigating With the Right Tools

The road to chiplet-driven automotive electronics is one paved with complexity, but with a commitment to standards, it is a path that promises significant rewards. By leveraging Cadence UCIe Design and Verification IP, tools, and methodologies, automotive designers are empowered to chart a course toward chiplets and help to establish a chiplet ecosystem. With challenges ranging from die-to-die interconnect to standardization, heterogeneous integration, and advanced packaging, the need for a seamless integrated flow and highly automated design approaches has never been more apparent. Companies like Cadence are tackling these challenges, providing the key technology for automotive designers seeking to utilize chiplets for the next-generation E/E architecture of vehicular technology.

In summary, chiplets have the potential to revolutionize the automotive electronics industry, breathing new life into the way vehicles are designed, manufactured, and operated. By understanding the significance of chiplets and addressing the challenges they present, automotive electronics is poised for a paradigm shift—one that combines the art of human ingenuity with the power of modular and scalable microchips to shape a future that is not only efficient but truly intelligent.

Learn more about how Cadence can help to enable automakers and OEMs with various aspects of automotive design.

LEF allows the same port with multiple shape definitions. Does anybody know if innovus can create multiple duplicate shapes associated with the same port? Assume they are connected outside the block with perfect timing synchronization. Thank you!

Hi,

Is there any way to instruct the tool to reduce the low metals effort and route more on top layers? 

Hi everyone,

I'm designing a digital chip that will be fabricated. I have a HDL top module that includes several submodules inside it. I want to define the position of some of the submodules during the PnR so that later I can specify there positions in the Micrograph photo after the IC fabrication. When I perform the PnR using Innovus, I always got a layout shape where the submodules seems to be flatted. I wonder if there is a way to specify the placement of each submodule in my top module  (maybe in the tcl file) during the PnR so later I can define there positions in the micrograph photo. 

Thanks in Advance!

I am trying to remove the cdn_loop_breaker cells from the netlist. 
When I tried the below 2 things, genus synthesis tool removing the cdn_loop_breaker cells but while connecting the cdn_loop_breaker cell input to its proper connection, its somehow misleading the connections

Things i tried:
1.  remove_cdn_loop_breaker -instances *cdn_loop_breaker*
then i just ran remove_cdn_loop_breaker  comand without the -instances switch
2. remove_cdn_loop_breaker  
     
both of the above things are not providing the proper connections after removing the loop_breaker_cells

can anyone suggest the best possible workaround for this please?

We are currently setting up the Tempus flow and have ran into some mismatched data regarding ECO and timing reports. I generated a timing report before running ECO and saw six total setup violations. When running opt_signoff -setup, the initial setup summary that was printed in the shell only showed one violation. I can see that violation from the initial setup summary in my pre-ECO timing report and it is not the worst path. Upon further investigation, I forced the tool to try to fix setup on one of the other five violations from the timing report using the opt_signoff_select_setup_endpoints attribute and the tool said that the endpoint had positive slack and would be ignored.

Has anyone experienced something like this before?

Hi all, 

I have made a custom cell in Innovus that I will be instantiating into a bigger block, which I will also be using Innovus to do the Place & Route. 

I understand that I can generate a *.lef file and a *.lib file using Innovus. However, I need to also create a *.db file (these format of files are often used in DC Compiler synthesis tool). 

Is there a way to create the *.db file from Innovus? Or, is there a tool that I can use to create this *.db file? 

Thank you for your time. 

I want to create sub tree of sub trees how can i do that?

I want to create another tree for the Sub parameter also.

I'm trying to do what I believe should be a very simple and straightforward thing but after much reading appears to be quite complicated.

I'm test-benching the digital portion of a mixed-signal circuit that's instantiated a few hundred times. Each instance has some digital controls, and an analog portion. To greatly speed up the simulation, I'd like to hide the analog portion, which is neatly contained in one or two cell views deep down the hierarchy, and then unhide it after simulation has ended so it doesn't mess up other peoples' sims

Just as an example, say there's an op-amp that from the top level is contained in instance "I<0:511>/I3/I15/I0". First off, I don't know how to iterate through the 512 instantiations of the top level cell, but let's say we're just working with the I0 instance. I thought it would just be

schIgnore(?objectId "I<0:511>/I3/I15/I0" ?setIgnore t)

Of course this doesn't work. I can get the top level cell dbId with

cv = dbOpenCellViewByType("library" "cell" "schematic" "" "a")

And then I can grab the instance ID with

inst = dbFindAnyInstByName(cv "I0")

This gives me something, but then I'm lost from here. If I use the ~>master to get an Id from inst, I cannot recursively use dbFindAnyInstByName to traverse down the hierarchy. Also the value this returned seems to be meaningless, it can't be used by the schIgnore command. I'm not sure what the schIgnore command is actually even looking for.

So I guess I'm trying to loop through two things, one is to traverse down the hierarchy and grab the ID of a child instance so I can schIgnore it, and another is to iterate through all the top level instances to hide the child instance within each of them.

Hello Community,

Is there any simple way how i can get the coordinates of all the shapes in a layout view?

Currently i'm flattening the layout, getting all the lpps from CV and using setof to get all the shapes of a layer and looping through them to get the coordinates.

Is there a way to do it without having to flatten the layout view and shapes merged or any other elegant way to do it if we flatten it?

Also, dbWriteSkill doesn't give output how i desired

Thanks,

Shankar

What is the variable to define via selection/type for vias

I want to be able to load via cut type in the via option when I use the leHiCreateVia() function

I want to select/load to the Via Option menu on which via I want to use

Cadence version IC23.1.64b.ISR7.27

Paul

Hi,all

  I want to remove some Tests form adexl automatically,there have any function to achieve that?

Hi,

My query is regarding importing of layout.

After importing, we see that the imported transistor instances and vias are all referring to the library in which they are imported, instead of referring to the technology library.

Please let me know how we can refer them to the technology library.

Will surely provide more details if my query is unclear.

Thanks,

Mallikarjun.

Hi guys,

I see that inside VNC I can’t resize window boxes by mouse. While pressing the arrow at the box edge and dragging it nothing happens:

is it a bug, or setup change require?

Noted, it only happens when trying to resize window box from left and right side..

Thx