An impedance tuning circuit includes a calibration unit and a post-processing unit. The calibration unit generates an initial pull-up code and an initial pull-down code by performing a calibration operation using an external resistor during an initial impedance tuning operation. The post-processing unit outputs the initial pull-up code and the initial pull-down code as a final pull-up code and a final pull-down code during the initial impedance tuning operation, and generates the final pull-up code and the final pull-down code by using the initial pull-up code and the initial pull-down code during a subsequent impedance tuning operation.

A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.

A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.

A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.

A transceiver includes a transmitter and receiver that form a series current path between two power-supply nodes. Powering both the transmitter and receiver with the same supply current saves power. The transmitter functions as a resistive load for the receiver, and thus performs useful work with power that would otherwise be dissipated as waste heat.

A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.

A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value.

A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

Embodiments of the invention are generally directed to a single-ended configurable multi-mode driver. An embodiment of an apparatus includes an input to receive an input signal, an output to transmit a driven signal generated from the input signal on a communication channel, a mechanism for independently configuring a termination resistance of the driver apparatus, and a mechanism for independently configuring a voltage swing of the driven signal without modifying a supply voltage for the apparatus.

A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.

A self-feedback random generator comprises a digital-to-analog converter, a digital oscillator, a frequency-modulating unit and a first D-type flip-flop. The digital-to-analog converter receives a digital random-code signal and the digital random-code signal is converted to corresponding analog random signal. The frequency-modulating unit modulates frequency of first digital oscillating signal so as to increase random of frequency of first digital oscillating signal according to voltage value of the analog random signal, and accordingly outputs a second digital oscillating signal. The first D-type flip-flop receives the second digital oscillating signal and a clock signal, and reads the second digital oscillating signal through utilizing the clock signal so as to outputs the digital random-code signal, wherein frequency of the clock signal is smaller than frequency of the first digital oscillating signal, and random of frequency of the second digital oscillating signal corresponds to random of the digital random-code signal.

A digitally controlled oscillator has a high-order ΔΣ modulator configured to be of at least an order higher than a first order and configured to input a digital control signal and output a pseudorandom digital output signal, a first-order ΔΣ modulator configured to input the pseudorandom digital output signal and generate a control pulse signal including a pulse width corresponding to the pseudorandom digital output signal, a low pass filter configured to pass a low frequency component of the control pulse signal, and an oscillator configured to generate a high-frequency output signal whose frequency is controlled based on the control pulse signal outputted by the low pass filter so as to be a frequency corresponding to the digital control signal.

An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.

A digitally-controlled oscillator includes a base frequency generator having an odd number of base inverters connected end-to-end to generate an output signal that oscillates at a predetermined frequency and a frequency-adjusting unit connected to the base frequency generator. The frequency-adjusting unit includes a first string of switchable inverters connected in series with each other, the switchable inverters having sizes that decrease from an input end of the first string to the output end of the first string.

Embodiments provide a multi-phase voltage controlled oscillator (VCO) that produces a plurality of output signals having a common frequency and different phases. In one embodiment, the VCO may include a passive conductive structure having a first ring and a plurality of taps spaced around the first ring. The VCO may further include a capacitive load coupled to the passive conductive structure, one or more feedback structures coupled between a pair of opposing taps of the plurality of taps, and one or more current injection devices coupled between a pair of adjacent taps of the plurality of taps.

The present invention discloses an Oven Controlled Crystal Oscillator and a manufacturing method thereof. The Oven Controlled Crystal Oscillator comprises a thermostatic bath, a heating device, a PCB and a signal generating element, where the signal generating element is used for generating a signal of a certain frequency, the heating device, the PCB and the signal generating element are mounted in the thermostatic bath, the signal generating element is mounted in a groove formed on one side of the PCB, while the heating device is mounted against the other side of the PCB that is opposite to the groove. The signal generating element may be a passive crystal resonator or an active crystal oscillator. The Oven Controlled Crystal Oscillator according to the invention is advantageous for a small volume and a high temperature control precision.

An integrated structure of compound semiconductor devices is disclosed. The integrated structure comprises from bottom to top a substrate, a first epitaxial layer, an etching-stop layer, a second epitaxial layer, a sub-collector layer, a collector layer, a base layer, and an emitter layer, in which the first epitaxial layer is a p-type doped layer, the second epitaxial layer is an n-type graded doping layer with a gradually increased or decreased doping concentration, and the sub-collector layer is an n-type doped layer. The integrated structure can be used to form an HBT, a varactor, or an MESFET.

Systems and methods for switching impedance are provided. In some aspects, a system includes first and second impedance elements and an impedance switch module, which includes a third impedance element coupled between the first and second impedance elements and a switch parallel to the third impedance element. The switch is coupled between the first and second impedance elements, and is configured to switch between an open configuration and a closed configuration. An electrical path is completed between the first impedance element and the second impedance element via the first switch in the closed configuration. The electrical path is not completed in the open configuration. A total impedance of the first impedance element, the second impedance element, and the impedance switch module is varied based on the switching between the open configuration and the closed configuration.

The present invention proposes a digital system and method of measuring (estimating) non-energy parameters of the signal (phase, frequency and frequency rate) received in additive mixture with Gaussian noise. The first embodiment of the measuring system consists of a PLL system tracking variable signal frequency, a block of NCO full phase computation (OFPC), a block of signal phase primary estimation (SPPE) and a first type adaptive filter filtering the signal from the output of SPPE. The second embodiment of the invention has no block SPPE, and NCO full phase is fed to the input of a second type adaptive filter. The present invention can be used in receivers of various navigation systems, such as GPS, GLONASS and GALILEO, which provide precise measurements of signal phase at different rates of frequency change, as well as systems using digital PLLs for speed measurements.

A method, an apparatus, and a computer program product are provided. The apparatus tunes a frequency provided by a VCO. The apparatus determines a relative capacitance change associated with a first frequency and a desired frequency from a look-up table. The apparatus adjusts a capacitor circuit in the VCO based on the determined relative capacitance change determined from the look-up table in order to tune from the first frequency to the desired frequency. The apparatus determines that the frequency provided by the VCO is a second frequency different than the desired frequency after adjusting the capacitor circuit. The apparatus performs an iterative search to further adjust the capacitor circuit when a difference between the second frequency and the desired frequency is greater than a threshold.

A system is disclosed for a voltage controlled oscillator (“VCO”) having a large frequency range and a low gain. Passive or active circuitry is introduced between at least one VCO cell in the voltage controlled oscillator and the voltage source for the VCO cell which reduces a gain value for the VCO to maintain stability of the system.

An injection locking oscillator (ILO) comprising a tank circuit having a digitally controlled capacitor bank, a cross-coupled differential transistor pair coupled to the tank circuit, at least one signal injection node, and at least one output node configured to provide an injection locked output signal; a digitally controlled injection-ratio circuit having an injection output coupled to the at least one signal injection node, configured to accept an input signal and to generate an adjustable injection signal applied to the at least one injection node; and, an ILO controller connected to the capacitor bank and the injection-ratio circuit configured to apply a control signal to the capacitor bank to adjust a resonant frequency of the tank circuit and to apply a control signal to the injection-ratio circuit to adjust a signal injection ratio.

Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.

Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.

A current output control device is provided that includes: a current cell array section including plural current cell circuits that are each connected in parallel between a first terminal (power source) and a second terminal (ground) that connect between the first terminal and the second terminal in by operation ON so as to increase control current flowing between the first terminal and the second terminal; and a code conversion section (decoder) that generates signals (row codes, column codes) to ON/OFF control current cells so as to change the number of current cells that connect the first terminal and the second terminal according to change in an externally input code and that inputs the generated signals to the current cell array section.

A ring-oscillator-based on-chip sensor (OCS) includes a substrate having a semiconductor surface upon which the OCS is formed. The OCS includes an odd number of digital logic stages formed in and on the semiconductor surface including a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack. A feedback connection is from an output of the last stage to an input of the first stage. At least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device is coupled between the first gate stack and a ground pad, and/or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device is coupled between the second gate stack a power supply pad.

An enhanced negative resistance voltage controlled oscillator (VCO) circuit is provided, in which a parallel connection of a capacitor and a resistor configured to provide frequency-dependent transconductance is present across source nodes of a first pair of field effect transistors in which gate nodes and drain nodes are cross-coupled. The source nodes of the first pair of field effect transistors are electrically shorted to drain nodes of a second pair of field effect transistors of which the gate nodes are electrically shorted to the gate nodes of the first pair of field effect transistors. The parallel connection of the capacitor and the resistor includes a parallel connection of a capacitor and a resistor such that the net transconductance of the first pair of field effect transistors is less at low frequencies where thermal noise and flicker noise are dominant part of the phase noise than at the operational frequency range.

A crystal controlled oscillator includes a crystal package and an IC chip board that includes an IC chip integrating an oscillator circuit. The crystal package includes a first container, a crystal resonator, a lid body, and an external terminal at an outer bottom surface of the first bottom wall layer of the first container. The IC chip integrates an oscillator circuit disposed at an outer bottom surface of the first bottom wall layer of the crystal package. The oscillator circuit connects to the lower side excitation electrode of the crystal resonator from the external terminal to an input side with high impedance. The oscillator circuit connects to the upper side excitation electrode to an output side with low impedance. The upper side excitation electrode is a shielding electrode of the crystal resonator.

An apparatus is disclosed that includes a first cross-coupled transistor pair, a second cross-coupled transistor pair, at least one capacitance unit, and an inductive unit. The first cross-coupled transistor pair and second cross-coupled transistor pair are coupled to a pair of first output nodes and a pair of second output nodes, respectively. The at least one capacitance unit is coupled to at least one of the pair of first output nodes and the pair of second output nodes. The inductive unit is coupled to the first cross-coupled transistor pair at the first output nodes and coupled to the second cross-coupled transistor pair at the second output nodes. The inductive unit generates mutual magnetic coupling between one of the first output nodes and one of the second output nodes and between the other of the first output nodes and the other of the second output nodes.

An actuator includes a first piston and a second piston. The first piston has a piston ring that separates a first chamber from a second chamber of the actuator. The first piston has an interior chamber that communicates with the first chamber. The second piston is disposed within the interior chamber of the first piston so as to be movable with respect thereto. The second piston has a surface that interfaces with the second chamber.

An apparatus includes a light foil device configured to move based on radiation pressure associated with light received by the light foil device. The apparatus includes a mechanism configured to transition between operational states in response to the movement of the light foil device, or includes a valve configured to control a flow of material through a conduit based, at least in part, on the movement of the light foil device.

Water valves and methods of regulating fluid flow for low ambient pressure water sources that reduce the amount of filtration needed for valve mechanisms operating in the water source.

In a control device for a technical processing plant, a pneumatically driven actuator having an actuator stem is provided together with a valve operated by the actuator, the valve having a valve stem. A valve element is attached to the valve stem. A stem connector connects the two stems to each other for a forced transmission of axial actuating movements and for modifying an axial distance between adjacent ends of the valve stem and the actuator stem to adjust a total axial length of the two stems. The stem connector comprises two half-shells connected to each other, and two positioning devices are provided for a friction-locking coupling of the half-shells to the respective ends. At least one of the positioning devices is designed to modify an axial attachment position of the half-shells along one of the stems.

A solenoid valve, the magnet armature of which is designed to be movable relative to a first valve-closing element, for which purpose the first valve-closing element is accommodated telescopically in a coupling element attached to the magnet armature, wherein the coupling element is guided along the inner wall of a guide sleeve inserted in the valve housing in order to align the magnet armature precisely with the first valve-closing element in the direction of a second valve-closing element which is likewise accommodated in the guide sleeve.

A flow control valve element has a generally spherical ball. An inlet is formed in the ball. An outlet is also formed in the ball, the outlet opposing the inlet. A hollowed-out portion extends between the inlet and the outlet. A pair of opposing flats are formed in the ball, the flats each having a first flat portion formed in an external portion of the ball and an opposing second flat portion formed in the hollowed-out portion of the ball.

A method for operating a collection system for printed products includes drawing off the printed products from discharge device(s) disposed at corresponding discharge point(s) in the collection system. The printed products are deposited on a collection section during a cycle period of the discharge device(s) so as to form a bundle of printed products. The bundle is transferred to a subsequent conveying mechanism having receiving pockets. It is determined whether at least one missing printed product exists due to an incorrect drawing off from the discharge point(s). A repair process is initiated and controlled in which the at least one missing printed product is drawn off from the corresponding discharge point(s) at a time corresponding to a subsequent recurrent pocket-related cycle of the subsequent conveying mechanism in a subsequent cycle period of the discharge device(s). The at least one missing printed product is inserted in the relevant receiving pocket.

A method for producing a bundle composed of book blocks includes gathering a plurality of printed sheets to form respective book blocks. The plurality of the book blocks are positioned with the same orientation and respectively positioned on lower edges of the printed sheets. Respectively two adjacent book blocks are offset from one another parallel to the lower edges of the printed sheets and transverse to a height of the bundle to be formed, such that a side edge of one of the two book block projects relative to a side edge of the adjacent book block. Thereafter the offset book blocks are combined to form the bundle and the bundle is compressed to fix the offset position of the book blocks.

A method for operating a processing system, in which product units of different formats are processed. The processing system contains a plurality of processing devices that are arranged one after the other in a processing line. In the event of a format changeover, certain component arrangements arranged in the processing system must be adapted to the new product format. In the event of an upcoming format change, a gap in the conveyed goods is generated while the conveying operation is maintained, wherein the gap in the conveyed goods runs through the processing system along the processing devices. As soon as the gap in the conveyed goods runs through a component arrangement to be adapted to the new format, the format is changed over at the component arrangement while the gap in the conveyed goods runs through the component arrangement.

A sheet handling apparatus includes a sheet folding unit configured to perform folding on a sheet; and a sheet stacking unit configured to stack the folded sheet on a sheet stacking surface having an inclined surface and a horizontal surface in order from upstream to downstream in a sheet conveying direction. A downstream end of the inclined surface is higher than an upstream end of the inclined surface with respect to a horizontal plane. The sheet handling apparatus also includes a discharging unit configured to discharge the folded sheet to the sheet stacking unit; a sheet conveying unit configured to convey the discharged sheet from the inclined surface to the horizontal surface; and a conveying force applying unit configured to apply a conveying force to the sheet in contact with an upper surface of the sheet from above the inclined surface.

In a first step, in a printed material web (1) moved in a feed direction, a first material web part (5) which is formed by a material web section (1a)is folded against the rest of the material web (6) that is formed from two material web portions (1b, 1c)).In the region of a connecting line (2b) extending between neighbouring material web sections (1b, 1c) the two material web parts (5,6) are connected to one another by a means of a bonding adhesive. In a subsequent step the material web (1) is folded again along a line (2b) extending between two neighbouring material web sections. (1b, 1c)All material web sections (1a, 1b, 1c) lie above one another. Subsequently, multi-page sub-products (11), the pages (12a, 12b, 12c) of which are connected to one another in the region of the spine (13) of the sub-product, are separated from the twice-folded material web (1). Finally, the sub-products (11) are placed on top of one another to form a stack (16) and are connected to one another in the region of the spine (13) thereof by means of a bonding adhesive.

This invention provides a technique of preventing a collision between an original document and a printing material on a conveyance path when an image forming apparatus executes both additional printing on the original document and printing on the printing material. In a case where both additional printing on an original document and printing on a printing material are executed, the image forming apparatus according to one aspect of the invention conveys a read original document to a transfer unit through a conveyance path commonly used for an original document and sheet, and prints an image to be added on the original document. After the original document is conveyed to the transfer unit through the conveyance path, the image forming apparatus feeds a sheet from a sheet feeding unit to the conveyance path, and performs copying on the sheet in the transfer unit.

A printing control apparatus according to one aspect of this invention controls to print images on sheets based on image data of a plurality of pages, generate a bookbinding product by executing folding processing for the image-printed sheets, and output the bookbinding product. The printing control apparatus further accepts the position of an insertion sheet to be inserted into the sheets for which the folding processing is executed, and controls to output a plurality of bookbinding products by using, as a reference, the accepted position of the insertion sheet.

The present invention is directed to providing a mechanism for allowing a user to easily take out print products discharged onto a plurality of sheet discharge trays in the discharge order. A control method for controlling a sheet processing apparatus for performing control to discharge sheets onto a plurality of sheet discharge trays includes storing, in a storage unit, the discharge order in which sheets have been discharged onto equal to or more than two sheet discharge trays by executing a job, and performing, upon reception of a take-out instruction for taking out in the discharge order the sheets discharged by executing the job, processing for allowing a user to take out the sheets discharged onto the equal to or more than two sheet discharge trays, in the discharge order stored in the storage unit.

An image recording apparatus includes: a recording unit for recording an image on a recording medium; a tray for supporting the recording medium recorded by the recording unit; a conveyor mechanism for conveying the recorded medium to the tray; and an alignment mechanism for aligning a plurality of recording media stacked on the tray, by application of an external force. In a period from a start to an end of recording based on one recording job, the alignment mechanism aligns the plurality of recording media stacked on the tray in a period in which image recording is not performed, and the alignment mechanism does not align the plurality of recording media stacked on the tray in a period in which image recording is being performed.

A sheet processing apparatus and a method of controlling the same align sheets stacked on a stacking unit, by causing a first alignment member and a second alignment member to come into contact with edges of a sheet stacked on the stacking unit in a sheet width direction. In a case that a second sheet that is different from a first sheet stacked on the stacking unit is to be stacked on the first sheet and aligned using the first alignment member and the second alignment member, control is performed to discharge a partition sheet onto the first sheet stacked on the stacking unit.

A puncher cylinder includes a puncher knife, the cylinder being arranged for cooperation with a paper web such that the cylinder when in use can be rolled longitudinally along and in contact with the paper web, punching holes in the paper web by way of the puncher knife. The holes are punched a longitudinal distance from each other essentially corresponding to the circumference of the cylinder. A system is further disclosed including the punching cylinder, as is a method utilizing the punching cylinder, and a newspaper partly produced by way of the punching cylinder.

An apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of the die; and a carrier including a plurality of layers of conductive material disposed on the device side of the die, a first one of the layers of conductive materials being formed on the insulating layer and patterned into traces at least a portion of which are connected to respective contact points on the die. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; disposing a mold on the sacrificial substrate around; introducing an insulating material into a chase of the mold; removing the mold; forming a carrier on the insulating material adjacent a device side of a die; and separating the die and the carrier from the sacrificial substrate.

An embodiment is an integrated circuit structure including a first die attached to a second die by a first connector. The first connector includes a solder joint portion between a first nickel-containing layer and a second nickel-containing layer, a first copper-containing layer between the first nickel-containing layer and the solder joint portion, and a second copper-containing layer between the second nickel-containing layer and the solder joint portion.