1 Jordanian Dinar = 170.4515 Nepalese Rupee

1 Lebanese Pound = 0.0799 Nepalese Rupee

1 Bahraini Dinar = 319.7851 Nepalese Rupee

1 Chilean Peso = 0.1464 Nepalese Rupee

1 Maldivian Rufiyaa = 7.8005 Nepalese Rupee

It's more than tossing bags at a cookout. KC Joyner looks at the deeper levels of strategy and skill.

1 Malaysian Ringgit = 27.9038 Nepalese Rupee

El virus se ha propagado rápidamente en prisiones sobrepobladas en el mundo, lo que ha llevado a los gobiernos a liberar a los reclusos en masa.

He amassed a vast trove of art and artifacts and built a castle-like repository so the public could see it, partly because his family wasn’t happy with his collecting.

1 Nicaraguan Cordoba Oro = 3.5152 Nepalese Rupee

The Bucs have never had more than four prime-time games in a year, but in 2020 they'll face the Bears, Raiders, Giants, Saints and Rams in prime time.

1 Netherlands Antillean Guilder = 67.3663 Nepalese Rupee

1 Estonian Kroon = 8.4793 Nepalese Rupee

1 Danish Krone = 17.5756 Nepalese Rupee

1 Fiji Dollar = 53.6768 Nepalese Rupee

1 New Zealand Dollar = 74.2303 Nepalese Rupee

1 Croatian Kuna = 17.4295 Nepalese Rupee

1 Peruvian Nuevo Sol = 35.5795 Nepalese Rupee

Contact Head Coach, Alta Malchoff for more information. Amalchoff@haskell.edu

Lawrence, Kansas – The Haskell men's golf team finished 8th out of 9 teams at the Ottawa Spring Invitational held at Eagle Bend Golf Course on Monday. The Indians finished with a round score of 344 and the second round was cancelled due to snow on the course. 

Both Women's and Men's Cross Country improved their overall standings this weekend at the bearcat Open.

This week Cross Country is training for their first home meet on Saturday October 12, 2019 at 9:15 & 10:00 am during Homcoming Weekend!

1 Dominican Peso = 2.1972 Nepalese Rupee

NCAA Division II, Emporia State University served as the 2^ndmeet of the Outdoor Track and Field season for the Indians.  Highlights from the meet include:

Ian Stand, a sophomore from Bay Point, California returned to the discus ring and completed a toss of 36.52 meters, an improvement from his first meet.  Stand, also earned a seventh place finish in the shot put with a distance of 10.76 meters. 

1 Papua New Guinean Kina = 35.2544 Nepalese Rupee

1 Brunei Dollar = 85.5724 Nepalese Rupee

Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components and calculation power to accommodate new performance-hungry applications such as machine learning and autonomous driving.  With increased number of SoC components, such as CPUs, GPUs, accelerators and I/O devices, comes increased demand to correctly model interoperability of various components. Traditional simulation of complex systems requires accurate models of all components comprising the system and normally results in very long simulation times. A better way is to create a set of typical traffic profiles which describe behavior of system’s masters and slaves. Such profiles should be abstract to be applied to various protocols and interfaces and be portable to be applied throughout different SoC design and verification cycles.

To address the challenges outlined above, Arm has recently announced availability of the AMBA® Adaptive Traffic Profiles (AMBA ATP) specification which lays foundation of a new synthetic traffic framework. The AMBA ATP specification includes detailed information of various transaction types and timing characteristics of those transactions. The traffic profiles defined in the specification are abstract in nature and thus could be used to generate stimuli for various standard AMBA protocols and in various environments such as RTL-based simulation, FPGA prototyping and final SoC verification. The traffic profiles outlined in the specification include a set of parameters to define timing relationships between transactions as well as timing relationships within individual transactions. Even though the traffic profile represents the behavior of a single agent it could be applied either in a concurrent manner (e.g. write and read traffic profiles running in parallel) or in a sequential manner (e.g. when one traffic completes before the next one start). Moreover, when simulating a reasonably complex system, it is possible to coordinate traffic profiles generated by multiple components. While providing abstract definition of traffic profiles, the AMBA ATP specification focuses on the use of traffic profiles with an AMBA AXI interface, outlining signaling, timing relationships between different transaction phases and between different transactions. The same application principles could be used to map the abstract traffic profiles to other AMBA protocols such as AMBA5 CHI protocol.  

To facilitate adoption of the AMBA Adaptive Traffic Profiles, Cadence has recently announced availability of SystemVerilog UVM ATP Sequence Layer which automatically implements mapping of an abstract ATP traffic to AMBA protocol specific traffic, generated by Cadence AMBA Verification IP. The ATP layer is implemented as a SystemVerilog UVM virtual sequence with the sequence item including all ATP transaction parameters as defined in the specification.

Using the provided sequence infrastructure, users can write tests to define and coordinate traffic profiles for various components in the system. The ATP Layer automatically converts the abstract traffic profile into AMBA protocol-specific traffic, e.g., AMBA5 CHI protocol traffic.

 A sample code below, shows an example of a read profile translated by Cadence ACE Verification IP in ACE protocol traffic.

   `uvm_do_with(ace_atp_vseq,                                            

                       {ace_atp_vseq.agentId == agent_id;                                // ATP agent id

                        ace_atp_vseq.atpDirection == ATP_READ;                    // direction of bursts issued by virtual sequence

                        ace_atp_vseq.startAddress == start_address;                // start of address range being accessed

                        ace_atp_vseq.endAddress == end_address;                  // end of address range being accessed

                        ace_atp_vseq.atpDomain == atp_domain;                      // domain to use for transactions

                        ace_atp_vseq.addressPattern == ATP_SEQUENTIAL;  // address pattern

                        ace_atp_vseq.transactionSize == 64;                             // number of bytes in each burst

                        ace_atp_vseq.dataSize == 4;                                          // number of bytes in each transfer

                        ace_atp_vseq.rate == 150.0/(50.0);                                // requestedBandwidth / clkFrequency

                        ace_atp_vseq.start == ATP_EMPTY;                              // start condition of the ATP FIFO

                        ace_atp_vseq.full == 128;                                               // full level of the ATP FIFO

                        ace_atp_vseq.numOfTransactions == 500;                    // number of bursts issued by this sequence

                        ace_atp_vseq.ARTV == 2;                                              // sub-transaction delay

                        ace_atp_vseq.RBR == 3;                                                // sub-transaction delay

                       });

In addition to the ATP Layer for Cadence Simulation-Based AMBA Verification IP, Cadence supports the ATP functionality in Acceleration-Based AMBA Verification IP. For detailed information about ATP support in Cadence Simulation-Based and Acceleration-Based Verification IP, visit ip.cadence.com.

The PCI-SIG finalized the PCIe 4.0 specification with doubling the data to 16GT/s from 8GT/s in PCIe 3.0 in 2017. Products implementing this technology have begun to hit the market in 2019. Earlier this year, AMD announced it X570 chipset would support the PCIe 4.0 interface and Phison also introduced the world’s first PCIe 4.0 SSD.  With the increasing companies are working on PCIe 4.0 related product development, Cadence, as the key and leading PCIe IP solution vendor in the market, has strived for continuous enhancement of its PCIe 4.0 to be the best in the class IP solution. From our initial PCIe 4.0 solution in 4 years ago (revealed in 2015), we have made many advancements and improvements adding features such as Multi-link with any lane assignment, U.2/U.3 connector, and Automotive support. The variety of applications that PCIe4 finds a home in require extensive robustness and reliability testing over and above the compliance tests mandated by the standard body, i.e., PCI-SIG.

PCIe 4.0 TX Eye-Diagram, Loop-back Test (Long-reach) and RX JTOL Margin Test

Cadence IP team has also implemented additional "stress tests" in conjunction to its already comprehensive IP characterization plan, covering electrical, functional, ESD, Latch-up, HTOL, and yield sorting. Take the Receiver Jitter Tolerance Test (JTOL) for instance. JTOL is a key index to test the quality of the receiver of a system. This test use data generator/analyzer to send data to a SerDes receiver which is then looped back through the transmitter back to the instrument. The data received is compared to the data generated and the errors are counted. The data generator introduce jitter into the transmit data pattern to see how well the receiver functions under non-ideal conditions. While PCI-SIG compliance can be obtained on a single lane implementation, real world scenarios require wider implementations under atypical operating conditions. Cadence’s PCIe 4.0 IP was tested against to additional stressed conditions, such as different combination of multi-lanes operations, “temperature drift” conditions, e.g., bring up the chip at room temperature and check the JTOL at high temperature. 

PCIe 4.0 Sub-system Stress Test Setup

Besides complying with electrical parameters and protocol requirements, real world systems have idiosyncrasies of their own. Cadence IP team also built a versatile “System test” setup in house to perform a system level stress test of its PCIe 4.0 sub-system. The Cadence PCIe 4.0 sub-system is connected to a large number of server and desktop motherboards. This set up is tested with 1000s of cycles of repeated stress under varying operating conditions. Stress tests include speed change from 2.5G all the way to 16G and down, link enable/disable, cold boot, warm boot, entering and exiting low power states, and BER test sweeping presets across different channels. Performing this level of stress test verifies that our IP will operate to spec robustly and reliably when presented with the occasional corner cases in the real world.

More Information

For the demonstration of Cadence PCIe4 PHY Receiver Test and Sub-system Stress Test, see the video:

• PCIe 4.0 Sub-system Stress Test
• PCIe 4.0 PHY Receiver JTOL Test

For more information on Cadence's PCIe IP offerings, see our PCI Express page.

For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website.

Related Posts

• Blog: PCIe Gen4: It’s Official, We’re Compliant
• Blog: PCIe 3.0 Still Shines While PCIe Keeps Evolving
• Blog: The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016

USB4 can simultaneously tunnel USB3, PCIe and DisplayPort native protocol traffic through a hierarchy of USB4 routers. The key to tunneling of these protocols is routing table programmed at each ingress adapter. An entry of a routing table maps an incoming HopID, called Input/Ingress HopID to a corresponding pair of Output/Egress Adapter and Egress/Output HopID.

The responsibility of programming routing tables lies with the Connection Manager. Connection Manager, having the complete view of the hierarchy of the routers, programs the routing tables at all relevant adapter ports. Accordingly, the USB3, PCIe and DisplayPort protocol tunneled packets are routed, and reach their respective intended destinations.

The diagrammatic representation below is an example of tunneling of USB3 protocol traffic from USB4 Host Router to USB4 Peripheral Device Router through a USB4 Hub Router. The path from USB3 Host to USB3 Device is depicted by routing tables indicated at A -> B -> C -> D, and the one from USB3 Device to USB3 Host by routing tables indicated at E -> F -> G -> H . Note that the Input HopID from and Output HopID to all three protocol adapters for USB3, PCIe and DisplayPort Aux traffic, are fixed as 8, and for DisplayPort Main Link traffic are fixed as 9.

Once the native protocol traffic come into the transport layer of a USB4 router, the transport layer of it does not know to which native protocol a tunneled packet belongs to. The only way a transport layer tunneled packet is routed through the hierarchy of the routers is using the HopID values and the information programmed in the routing tables.

The figure below shows an example of tunneling of all the three USB3, PCIe and DisplayPort protocol traffic together. The transport layer tunneled packets of each of these native protocols are transported simultaneously through the routers hierarchy.

 Cadence has a mature Verification IP solution for the verification of USB3, PCIe and DisplayPort tunneling. This solution also employs the industry proven VIPs of each of these native protocols for native USB3, PCIe and DisplayPort traffic.

This is the 16th installment of The Rationalist, my column for the Times of India.

Steven Pinker, in his book Enlightenment Now, relates an old Russian joke about two peasants named Boris and Igor. They are both poor. Boris has a goat. Igor does not. One day, Igor is granted a wish by a visiting fairy. What will he wish for?

“I wish,” he says, “that Boris’s goat should die.”

The joke ends there, revealing as much about human nature as about economics. Consider the three things that happen if the fairy grants the wish. One, Boris becomes poorer. Two, Igor stays poor. Three, inequality reduces. Is any of them a good outcome?

I feel exasperated when I hear intellectuals and columnists talking about economic inequality. It is my contention that India’s problem is poverty – and that poverty and inequality are two very different things that often do not coincide.

To illustrate this, I sometimes ask this question: In which of the following countries would you rather be poor: USA or Bangladesh? The obvious answer is USA, where the poor are much better off than the poor of Bangladesh. And yet, while Bangladesh has greater poverty, the USA has higher inequality.

Indeed, take a look at the countries of the world measured by the Gini Index, which is that standard metric used to measure inequality, and you will find that USA, Hong Kong, Singapore and the United Kingdom all have greater inequality than Bangladesh, Liberia, Pakistan and Sierra Leone, which are much poorer. And yet, while the poor of Bangladesh would love to migrate to unequal USA, I don’t hear of too many people wishing to go in the opposite direction.

Indeed, people vote with their feet when it comes to choosing between poverty and inequality. All of human history is a story of migration from rural areas to cities – which have greater inequality.

If poverty and inequality are so different, why do people conflate the two? A key reason is that we tend to think of the world in zero-sum ways. For someone to win, someone else must lose. If the rich get richer, the poor must be getting poorer, and the presence of poverty must be proof of inequality.

But that’s not how the world works. The pie is not fixed. Economic growth is a positive-sum game and leads to an expansion of the pie, and everybody benefits. In absolute terms, the rich get richer, and so do the poor, often enough to come out of poverty. And so, in any growing economy, as poverty reduces, inequality tends to increase. (This is counter-intuitive, I know, so used are we to zero-sum thinking.) This is exactly what has happened in India since we liberalised parts of our economy in 1991.

Most people who complain about inequality in India are using the wrong word, and are really worried about poverty. Put a millionaire in a room with a billionaire, and no one will complain about the inequality in that room. But put a starving beggar in there, and the situation is morally objectionable. It is the poverty that makes it a problem, not the inequality.

You might think that this is just semantics, but words matter. Poverty and inequality are different phenomena with opposite solutions. You can solve for inequality by making everyone equally poor. Or you could solve for it by redistributing from the rich to the poor, as if the pie was fixed. The problem with this, as any economist will tell you, is that there is a trade-off between redistribution and growth. All redistribution comes at the cost of growing the pie – and only growth can solve the problem of poverty in a country like ours.

It has been estimated that in India, for every one percent rise in GDP, two million people come out of poverty. That is a stunning statistic. When millions of Indians don’t have enough money to eat properly or sleep with a roof over their heads, it is our moral imperative to help them rise out of poverty. The policies that will make this possible – allowing free markets, incentivising investment and job creation, removing state oppression – are likely to lead to greater inequality. So what? It is more urgent to make sure that every Indian has enough to fulfil his basic needs – what the philosopher Harry Frankfurt, in his fine book On Inequality, called the Doctrine of Sufficiency.

The elite in their airconditioned drawing rooms, and those who live in rich countries, can follow the fashions of the West and talk compassionately about inequality. India does not have that luxury.

© 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

This is the 19th installment of The Rationalist, my column for the Times of India.

A friend of mine was very impressed by the interview Narendra Modi granted last week to Akshay Kumar. ‘Such a charming man, such great work ethic,’ he gushed. ‘He is the kind of uncle I would want my kids to have.’ And then, in the same breath, he asked, ‘How can such a good man be such a bad prime minister?”

I don’t want to be uncharitable and suggest that Modi’s image is entirely manufactured, so let’s take the interview at face value. Let’s also grant Modi his claims about the purity of his neeyat (intentions), and reframe the question this way: when it comes to public policy, why do good intentions often lead to bad outcomes? To attempt an answer, I’ll refer to a story a friend of mine, who knows Modi well, once told me about him. 

Modi was chilling with his friends at home more than a decade ago, and told them an incident from his childhood. His mother was ill once, and the young Narendra was tending to her. The heat was enervating, so the boy went to the switchboard to switch on the fan. But there was no electricity. My friend said that as he told this story, Modi’s eyes filled with tears. Even after all these years, he was moved by the memory.

My friend used this story to make the point that Modi’s vision of the world is experiential. If he experiences something, he understands it. When he became chief minister of Gujarat, he made it his stated mission to get reliable electricity to every part of Gujarat. No doubt this was shaped by the time he flicked a switch as a young boy and the fan did not budge. Similarly, he has given importance to things like roads and cleanliness, since he would have experienced the impact of those as a young man.

My term for him, inspired by Rajat Kapoor’s 2014 film, is ‘the ankhon dekhi prime minister’. At one level, this is a good thing. He sees a problem and works for the rest of his life to solve it. But what of things he cannot experience?

The economy is a complex beast, as is society itself, and beyond a certain level, you need to grasp abstract concepts to understand how the world works. You cannot experience them. For example, spontaneous order, or the idea that society and markets, like language, cannot be centrally directed or planned. Or the positive-sum nature of things, which is the engine of our prosperity: the idea that every transaction is a win-win game, and that for one person to win, another does not have to lose. Or, indeed, respect for individual rights and free speech.

One understands abstract concepts by reading about them, understanding them, applying them to the real world. Modi is not known to be a reader, and this is not his fault. Given his background, it is a near-miracle that he has made it this far. He wasn’t born into a home with a reading culture, and did not have either the resources or the time when he was young to devote to reading. The only way he could learn about the world, thus, was by experiencing it.

There are two lessons here, one for Modi himself and others in his position, and another for everyone.

The lesson in this for Modi is a lesson for anyone who rises to such an important position, even if he is the smartest person in the world. That lesson is to have humility about the bounds of your knowledge, and to surround yourself with experts who can advise you well. Be driven by values and not confidence in your own knowledge. Gather intellectual giants around you, and stand on their shoulders.

Modi did not do this in the case of demonetisation, which he carried out against the advice of every expert he consulted. We all know the damage it caused to the economy.

The other learning from this is for all of us. How do we make sense of the world? By connecting dots. An ankhon-dekhi approach will get us very few dots, and our view of the world will be blurred and incomplete. The best way to gather more dots is reading. The more we read, the better we understand the world, and the better the decisions we take. When we can experience a thousand lives through books, why restrict ourselves to one?

A good man with noble intentions can make bad decisions with horrible consequences. The only way to hedge against this is by staying humble and reading more. So when you finish reading this piece, think of an unread book that you’d like to read today – and read it!

© 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

This is the 21st installment of The Rationalist, my column for the Times of India.

When all political parties agree on something, you know you might have a problem. Giriraj Singh, a minister in Narendra Modi’s new cabinet, tweeted this week that our population control law should become a “movement.” This is something that would find bipartisan support – we are taught from school onwards that India’s population is a big problem, and we need to control it.

This is wrong. Contrary to popular belief, our population is not a problem. It is our greatest strength.

The notion that we should worry about a growing population is an intuitive one. The world has limited resources. People keep increasing. Something’s gotta give.

Robert Malthus made just this point in his 1798 book, An Essay on the Principle of Population. He was worried that our population would grow exponentially while resources would grow arithmetically. As more people entered the workforce, wages would fall and goods would become scarce. Calamity was inevitable.

Malthus’s rationale was so influential that this mode of thinking was soon called ‘Malthusian.’ (It is a pejorative today.) A 20th-century follower of his, Harrison Brown, came up with one of my favourite images on this subject, arguing that a growing population would lead to the earth being “covered completely and to a considerable depth with a writhing mass of human beings, much as a dead cow is covered with a pulsating mass of maggots.”

Another Malthusian, Paul Ehrlich, published a book called The Population Bomb in 1968, which began with the stirring lines, “The battle to feed all of humanity is over. In the 1970s hundreds of millions of people will starve to death in spite of any crash programs embarked upon now.” Ehrlich was, as you’d guess, a big supporter of India’s coercive family planning programs. ““I don’t see,” he wrote, “how India could possibly feed two hundred million more people by 1980.”

None of these fears have come true. A 2007 study by Nicholas Eberstadt called ‘Too Many People?’ found no correlation between population density and poverty. The greater the density of people, the more you’d expect them to fight for resources – and yet, Monaco, which has 40 times the population density of Bangladesh, is doing well for itself. So is Bahrain, which has three times the population density of India.

Not only does population not cause poverty, it makes us more prosperous. The economist Julian Simon pointed out in a 1981 book that through history, whenever there has been a spurt in population, it has coincided with a spurt in productivity. Such as, for example, between Malthus’s time and now. There were around a billion people on earth in 1798, and there are around 7.7 billion today. As you read these words, consider that you are better off than the richest person on the planet then.

Why is this? The answer lies in the title of Simon’s book: The Ultimate Resource. When we speak of resources, we forget that human beings are the finest resource of all. There is no limit to our ingenuity. And we interact with each other in positive-sum ways – every voluntary interactions leaves both people better off, and the amount of value in the world goes up. This is why we want to be part of economic networks that are as large, and as dense, as possible. This is why most people migrate to cities rather than away from them – and why cities are so much richer than towns or villages.

If Malthusians were right, essential commodities like wheat, maize and rice would become relatively scarcer over time, and thus more expensive – but they have actually become much cheaper in real terms. This is thanks to the productivity and creativity of humans, who, in Eberstadt’s words, are “in practice always renewable and in theory entirely inexhaustible.”

The error made by Malthus, Brown and Ehrlich is the same error that our politicians make today, and not just in the context of population: zero-sum thinking. If our population grows and resources stays the same, of course there will be scarcity. But this is never the case. All we need to do to learn this lesson is look at our cities!

This mistaken thinking has had savage humanitarian consequences in India. Think of the unborn millions over the decades because of our brutal family planning policies. How many Tendulkars, Rahmans and Satyajit Rays have we lost? Think of the immoral coercion still carried out on poor people across the country. And finally, think of the condescension of our politicians, asserting that people are India’s problem – but always other people, never themselves.

This arrogance is India’s greatest problem, not our people.

© 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

There has been so much hype about the “Internet of Things” (IoT) that it is refreshing to hear about a cutting-edge development project that can bring concrete benefits to millions of people. That project is the ongoing development of the Google Smart Contact Lens, and it was detailed in a keynote speech June 8 at the Design Automation Conference (DAC 2015).

The keynote speech was given by Brian Otis (right), a director at Google and a research associate professor at the University of Washington. The “smart lens” that the project envisions is essentially a disposable contact lens that fits on an eye and continuously monitors blood glucose levels. This is valuable information for anyone who has, or may someday have, diabetes.

Since he was speaking to an engineering audience, Otis focused on the challenges behind building such a device, and described some of the strategies taken by Google and its partner, Novartis. The project required new approaches to miniaturization, low-power design, and connectivity, as well as a comfortable and reliable silicon-to-human interface. Otis discussed the “why” as well and showed how the device could potentially save or improve millions of lives.

Millions of Users

First, a bit of background. Google announced the smart lens project in a blog post in January 2014. Since then it has been featured in news outlets including Forbes, Time, and the Wall Street Journal. In March 2015, Time reported that Google has been granted a patent for a smart contact lens.

The smart lens monitors the level of blood glucose by looking at its concentration in tears. The lens includes a wireless system on chip (SoC) and a miniaturized glucose sensor. A tiny pinhole in the lens allows tear fluid to seep into the sensor, and a wireless antenna handles communications to the wireless devices.

“We figure that if we can solve a huge problem, it is probably worth doing,” Otis said. “Diabetes is one example.” He noted 382 million people worldwide have diabetes today, and that 35% of the U.S. population may be pre-diabetic. Today, diabetics must *** their fingers to test blood glucose levels, a procedure that is invasive, painful, and subject to infrequent monitoring.

According to Otis, the smart contact lens represents a “new category of wearable devices that are comfortable, inexpensive, and empowering.” The lens does sensor data logging and uses a portable instrument to measure glucose levels. It is thin, cheap, and disposable, he said.

Moreover, the lens is not just for people already diagnosed with diabetes—it’s for anyone who is pre-diabetic, or may be at risk due to genetic predisposition. “If we are pro-active rather than re-active,” Otis said, “Instead of waiting until a person has full-fledged diabetes, we could make a huge difference in peoples’ lives and lower the costs of treating them.”

Technical Challenges

No one has built anything quite like the smart lens, so researchers at Google and Novartis are treading new ground. Otis identified three key challenges:

• Miniaturization: Everything must be really small—the SoC, the passive components, the power supply. Components must be flexible and cheap, and support thin-film integration.
• Platform: Google has developed a reusable platform that includes tiny, always-on wireless sensors, ultra low-power components, and standards-based interfaces.
• Data: Researchers are looking for the best ways to get the resulting data into a mobile device and onto the cloud.

Comfort is another concern. “This is not intended to be for the most severe cases,” Otis said. “This is intended to be for all of us as a pro-active way of improving our lifestyles.”

The platform provides a bidirectional encrypted wireless link, integrated power management, on-chip memory, standards-based RFID link, flexible sensor interface, high-resolution potentiostat sensor, and decoupling capacitors. Most of these capabilities are provided by the standard CMOS SoC, which is a couple hundred microns on a side and only “tens of microns” thick.

Otis noted that unpackaged ICs are typically 250 microns thick when they come back from the foundry. Thus, post-processing is needed so the IC will fit into a contact lens.

Furthermore, the design requires precision analog circuitry and additional environmental sensors. “Some of this stuff sounds mundane but it is really hard, especially when you find out you can’t throw large decoupling capacitors and bypass capacitors onto a board, and all that has to be re-integrated into the chip,” Otis said.

Sensor Challenges

Getting information from the human body is challenging. The smart lens sensor does a direct chemical measurement on the surface of the eye. The sensor is designed to work with very low glucose concentrations. This is because the concentration of glucose in tears is an order of magnitude lower than it is in blood.

In brief, the sensor has two parallel plates that are coated with an enzyme that converts glucose into hydrogen peroxide, which flows around the electrodes of the sensor. This is actually a fairly standard way of doing glucose monitoring. However, the smart lens sensor has two electrodes compared to the typical three.

In manufacturing, it is essential to keep costs low. Otis outlined a three-step manufacturing process:

• Start with the bottom layer, and mold a contact lens in the way you typically would.
• Add the electronics package on top of that layer.
• Build a second layer that encapsulates the electronics and provides the curvature needed for comfort and vision correction.

Beyond the technical challenges are the “clinical” challenges of working with human beings. The human body “is messy and very variable,” Otis said. This variability affects sensor performance and calibration, RF/electro-magnetic performance, system reliability, and comfort.

The final step is making use of the data. “We need to get the data from the device into a phone, and then display it so users can visualize the data,” Otis said. This provides “actionable feedback” to the person who needs it. Eventually, the data will need to be stored in the cloud.

As he concluded his talk, Otis noted that the platform his group developed may have many applications beyond glucose monitoring. “There is a lot you can do with a bunch of logic and sensing capability,” he said, “and there are hundreds of biomarkers beyond glucose.” Clearly this will be an interesting technology to watch.

Richard Goering

Related Blog Post

- Gary Smith at DAC 2015: How EDA Can Expand Into New Directions

As a leading venture capitalist in the electronics technology, as well as CEO of Cadence, Lip-Bu Tan has unique insights into ongoing changes that will impact EDA providers and users. Tan shared some of those insights in a “fireside chat” with Ed Sperling, editor in chief of Semiconductor Engineering, at the Design Automation Conference (DAC 2015) on June 9.

Topics of this discussion included industry consolidation, the need for more talent and more startups, Internet of Things (IoT) opportunities and challenges, the shift from ICs to full product development, and the challenges of advanced nodes. Following are some excerpts from this conversation, held at the DAC Pavilion theater on the exhibit floor.

Ed Sperling (left) and Lip-Bu Tan (right) discuss trends in semiconductors and EDA

Q: As you look out over the semiconductor and EDA industries these days, what worries you most?

Tan: At the top of my list is all the consolidation that is going on. Secondly, chip design complexity is increasing substantially. Time-to-market pressure is growing and advanced nodes have challenges.

The other thing I worry about is that we need to have more startups. There’s a lot of innovation that needs to happen. And this industry needs more top talent. At Cadence, we have a program to recruit over 10% of new hires every year from college graduates. We need new blood and new ideas.

Q: EDA vendors were acquiring companies for many years, but now the startups are pretty much gone. Where does the next wave of innovation come from?

Tan: I’ve been an EDA CEO for the last seven years and I really enjoy it because so much innovation is needed. System providers have very big challenges and very different needs. You have to find the opportunities and go out and provide the solutions.

The opportunities are not just in basic tools. Massive parallelism is critical, and the power challenge is huge. Time to market is critical, and for the IoT companies, cost is going to be critical. If you want to take on some good engineering challenges, this is the most exciting time.

Q: You live two lives—you’re a CEO but you’re also an investor. Where are the investments going these days and where are we likely to see new startups?

Tan: Clearly everybody is chasing the IoT. There is a lot of opportunity in the cloud, in the data center. Also, I’m a big believer in video, so I back companies that are video related. A big area is automotive. ADAS [Advanced Driver Assistance Systems] is a tremendous opportunity.

These companies can help us understand how the industry is transforming, and then we can provide solutions, either in terms of IP, tools, or the PCB. Then we need to connect from the system level down to semiconductors. I think it’s a different way to design.

Q: What happens as we start moving from companies looking to design a semiconductor to system companies who are doing things from the perspective that we have this purpose for our software?

Tan: We are extending from EDA to what we call system design enablement, and we are becoming more application driven. The application at the system level will drive the silicon design. We need to help companies look at the whole system including the power envelope and signal integrity. You don’t want to be in a position where you design a chip all the way to fabrication and then find the power is too high.

We help the customers with hardware/software co-design and co-verification. We have a design suite and a verification suite that can provide customers with high-level abstractions, as well as verify IP blocks at the system level. Then we can break things down to the component level with system constraints in mind, and drive power-aware, system-aware design.

We are starting to move into vertical markets. For example, medical is a tremendous opportunity.

Q: How does this approach change what you provide to customers?

Tan: Every year I spend time meeting with customers. I think it is very important to understand what they are trying to design, and it is also important to know the customer’s customer requirements. We might say, “Wait a minute, for this design you may want to think about power or the library you’re using.” We help them understand what foundry they should use and what process they should use. They don’t view me as a vendor—they view me as a partner.

We also work very closely with our IP and foundry partners. We work as one team—the ultimate goal is customer success.

Q: Is everybody going to say, FinFETs are beautiful, we’re going to go down to 10nm or 7nm—or is it a smaller number of companies who will continue down that path?

Tan: Some of the analog/mixed-signal companies don’t need to go that far. We love those customers—we have close to 50% of that business. But we also have customers in the graphics or processor area who are really pushing the envelope, and need to be in 16nm, 14nm, or 10nm. We work very closely with those guys to make sure they can go into FinFETs.

We always want to work with the customer to make sure they have a first-time silicon success. If you have to do a re-spin, you miss the opportunity and it’s very costly.

Q: There’s a new market that is starting to explode—IoT. How real is that world to you? Everyone talks about large numbers, but is it showing up in terms of tools?

Tan: Everybody is talking about huge profits, but a lot of the time I think it is just connecting old devices that you have. Billions of units, absolutely yes, but if you look close enough the silicon percentage of that revenue is very tiny. A lot of the profit is on the service side. So you really need to look at the service killer app you are trying to provide.

What’s most important to us in the IoT market is the IP business. That’s why we bought Tensilica—it’s programmable, so you can find the killer app more quickly. The other challenges are time to market, low power, and low cost.

Q: Where is system design enablement going? Does it expand outside the traditional market for EDA?

Tan: It’s not just about tools. IP is now 11% of our revenue. At the PCB level, we acquired a company called Sigrity, and through that we are able to drive system analysis for power, signal integrity, and thermal. And then we look at some of the verticals and provide modeling all the way from the system level to the component level. We make sure that we provide a solution to the end customer, rather than something piecemeal.

Q: What do you think DAC will look like in five years?

Tan: It’s getting smaller. We need to see more startups and innovative IP solutions. I saw a few here this year, and that’s good. We need to encourage small startups.

Q: Where do we get the people to pull this off? I don’t see too many people coming into EDA.

Tan: I talk to a lot of university students, and I tell them that this small industry is a gold mine. A lot of innovation is needed. We need them to come in [to EDA] rather than join Google or Facebook. Those are great companies, but there is a lot of fundamental physical innovation we need.

Richard Goering

Related Blog Posts

- Gary Smith at DAC 2015: How EDA Can Expand Into New Directions

- DAC 2015: Google Smart Contact Lens Project Stretches Limits of IC Design

- Q&A with Nimish Modi: Going Beyond Traditional EDA

Hi All,

I have 1 huge project(day X) which has different reference power supply designs.

Now I start a new project and I require 1 specific reference power supply from X.

What is the easist way to do this, other than a copy paste.

Is there a way to create say symbols or something similar, so that multiple different people could use it if they need, in their projects

Thanks for your help and suggestions.

For a netlist vs. netlist LEC flow we have to solve the following problem:

- in the RTL code we replicate a large array of N x M all-identical hard-macros, let call them MACRO_A

- MACRO_A is pre-assembled in Innovus and contains digital parts and analog parts (bottom-up hierarchical flow)

- at top-level (full-chip) we instantiate this array of all-identical macros

- in the top-level place-and-route flow we perform ecoChangeCell to remaster the top row of this array with MACRO_B

- MACRO_B is just a copy of the original MACRO_A cell containing same pins position, same internal digital functionality and also same digital layout, only slight differences in one analog block inside the macro

- MACRO_A and MACRO_B have the same .lib file generated with the do_extract_model command at the end of the Innovus flow, they only differ in the name of the macro

- when performing post-synthesis netlist vs post-place-and-route we load .lib files of both macros in Conformal LEC

- the LEC flow fails because Conformal LEC sees only MACRO_A instantiated in the post-synthesis netlist and both MACRO_A and MACRO_B in the post-palce-and-route netlist

Since both digital functionality and STD cells layout are the same between MACRO_A and MACRO_B we don't want to keep track of this difference already at RTL stage, we just want to perform this ECO change in place-and-route and force Conformal to assume equivalence between MACRO_A and MACRO_B .

Basically what I'm searching for is something similar to the add_instance_equivalences Conformal command but that works between Golden and Revised designs on cell primitives/black-boxes .

Is this flow supported ?

Thanks in advance

Luca

I have been working on a an ASA 17.2 project for the last 6 months.

When I go to Project --> Settings, the settings window does not open. 

The tool indicates that a window is open, as I cannot click on anything else in the project. But it does not show the Settings window.

This has been happening only for the last 2 months. Before that it was working fine.

If I send the project to my colleague, the settings window shows up for him.

Hello Spectre RF Users, Next week is my all time favorite technical conference - the International Microwave Symposium IMS2016 , May 22-27 in San Francisco, CA at the Moscone Center. If you're at the conference, please stop by the Cadence booth and...(read more)

Did you check out the new Pnoise and Hbnoise Choosing Analyses forms in the MMSIM 15.1 and IC6.1.7 /ICADV12.2 releases? These forms have been significantly improved and simplified. The Direct Plot Form has also been enhanced and is much easy to use....(read more)

Hi,

I am trying to use "sed -e 's " from SKILL code to edit unix file "FileA", to replace 3 words in the 2nd line.

How to run below multiple commands using  ipcBeginProcess, Should I use ipcWait or ipcCloseProcess ?

Using && to combine , will that work as I have to work serially on each command. ?

With below code only the first command gets executed. Please advise.

FileA="/user/tmp/text1.txt"

sprintf(Command1 "sed -e '2s/%s/%s/g' %s > %s" comment1 get(form concat("dComment" RDWn))->value FileA FileA)
cid = ipcBeginProcess(Command1)


sprintf(Command2 "sed -e '2s/%s/%s/g' %s > %s"  Time getCurrentTime() FileA FileA)
cid1 = ipcBeginProcess(Command2)


sprintf(Command3 "sed -e '2s/%s/%s/g' %s > %s"  comment2 get(form concat("Duser" RDWn))->value FileA FileA)
cid2 = ipcBeginProcess(Command3)

Thanks,

Ajay

Inside the scope of isCallable there is code which I don't want to be executed.

The procedure named in isCallable to-day is callable.

I want to make that procedure so it cannot be called.  How do I do that?

I can't change the isCallable line or the scope.  I want to change its behavior by making sure that the procedure does not exist (obviously this would be done before the code is executed).

Hi,

I am running simulation in ADEXL and need a custom function for VIVA to apply same procedure to all signals saved in output. For instance, I have clock nets and I want to get all of them and look at the duty-cycle, edge rate etc.

It is a little more involved than about part since I have some regex and setof to filter before processing but if I can get all signals for current history, I can postprocess them later.

In ocean, I am just doing outputs() and getting all saved signals but I was able to do this in VIVA calculator due to the difficulties in getting current history, test name and opening result directory

thanks

yayla

Version Info:

ICADV12.3 64b 500.21

spectre -W =>

Tool 'cadenceMMSIM' Current project version '16.10.479'
sub-version  16.1.0.479.isr9

When I place a pcell and do not change the W parameter (default is used) the value is not saved in the OA cell property.

When I change the default value of the super master now, the old pcell will get the new default value automatically because there is nothing saved inside the OA cell for this parameter.

Do you have any Idea, that how we can save the default values in the OA cell properties so that this value doesn't get updated if the default values are updated in the new PDKs

The Accellera Portable Stimulus Working Group met at the DVCon 2018 to move the process forward towards ratification. While we can't predict exactly when it will be ratified, the goal is now more clearly in sight! Cadence booth was busy with a lo...(read more)

Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...(read more)

A little bit of everything in the blog today: PSS is All Over As someone that was involved with UVM and PSS, both becoming Accellera standards, it is exciting to see both growing independently and together. With PSS we had a massive amount of papers ...(read more)

Hi, I want to add values to components in my SiP design such as 1nF or 15nH. There is already in existence a COMP_VALUE property reserved for this as shown during BOM generation. This property is not visible under the Edit/Properties dialog for component or symbol find filters. We have already created user properties called COMP_MFG and COMP_MFG_PN that it editable at a component level. When we try to add COMP_VALUE it is reported as a reserved name in Cadence but this name is not listed in the properties dialog. Is there a way to turn on the visibility and editablility of this or other hidden reserved Cadence property names? How can I assign a string value to the COMP_VALUE property?

Thanks