A field-sequential display panel, a field-sequential display apparatus and a driving method are provided. The field-sequential display apparatus includes a liquid crystal display panel and an OLED light source arranged at one side of the liquid crystal display panel where light is incident to provide trichromatic light for pixel cells of the liquid crystal display panel. The OLED light source includes multiple groups of trichromatic light sources, each of the groups of trichromatic light sources includes a first color sub-light source, a second color sub-light source and a third color sub-light source, and each sub-light source includes an anode, a cathode and a light emitting layer between the anode and the cathode.

The general field of the invention is that of the graphical representation of a synthetic three dimensional view of the exterior landscape in an onboard visualisation system for aircraft, said graphical representation being displayed on a visualisation screen comprising the piloting and navigation information of said aircraft superposed onto said three-dimensional synthetic representation of the exterior landscape, said synthetic representation being computed up to a first determined distance, characterised in that said three-dimensional synthetic representation is tilted at a tilt angle about an axiom positioned at the level of the terrain in a substantially horizontal plane, and substantially perpendicularly to an axis between the flight direction and the heading of the aircraft, said axis moving with the aircraft.

A lifter assembly includes first and second lifter segments movably attached to one another and defining a lifting channel having an expandable bladder contained therein. Each lifter segment has an arm extending away from a base of the lifter segment and a travel stop at a distal end of the arm. Each lifter segment further has a keyway opening. The keyway opening of the first lifter segment receives the arm of the second lifter segment and the keyway opening of the second lifter segment receives the arm the first lifter segment.

A unit for transferring and up-ending at least one sealed package containing a pourable food product and having a first axis, comprising: at least one push member which cooperates with package to feed it along a first path from an in-feed station to an out-feed station; the path extending about a second axis; the unit further comprising a guide cooperating with a first side of package along first path to up-end it from an in-feed position, in which it is positioned with first axis oriented in a first direction, to an out-feed position, in which it is positioned with first axis oriented in a second direction crosswise to first direction; and an anti-rotating mechanism cooperating with package along path to prevent package from rotating about first axis; an anti-rotating mechanism comprising a pressure element rotatable about second axis and adapted to cooperate, in use, with package.

A buffer section for a conveying system in a high rack warehouse comprises a slide rod inclined relative to the horizontal for sliding conveyance along a conveying path in a conveying direction, which is parallel to a slide rod longitudinal axis, of a plurality of suspended conveyed goods, which are in each case suspended by means of a hook on the slide rod, and a stopper element in the conveying path at the end of at least one portion of the slide rod to stop the conveyed goods with the formation of a group of conveyed goods, wherein the stopper element has a contact face, which can be displaced between a stopper arrangement to stop the conveyed goods and a passing arrangement for allowing the conveyed goods through, for the conveyed goods, and wherein exclusively the stopper element is used to stop the conveyed goods.

A center loading assembly for a conveyor belt having a carriage support attached to a belt conveyor main frame and having a carriage within the carriage support. The carriage has a center member with side members extending at an angle therefrom, each having an upward extension. The upward extensions have side rollers and conveyor belt covering skirts and keep the conveyor belt centered between the conveyor belt covering skirts. The carriage support has vertical bearings to support the carriage and side bearings to hold the carriage on the vertical bearings. The carriage and conveyor belt covering skirts follow a trough angle of the conveyor belt as the conveyor belt shifts. Material deposited onto the conveyor belt is deflected to the center portion of the conveyor belt by the conveyor belt covering skirts.

A belt tracking system for adjusting displacement of a movable belt in an axial direction of a plurality of rollers about which the movable belt is entrained includes a slope member and a roller shaft support. The slope member is disposed at least at one end of at least one of the plurality of rollers in the axial direction, to tilt the roller due to movement of the belt. The roller shaft support rotates about a predetermined shaft and includes a shaft recovery member to recover a tilt of the slope member. The shaft recovery member is disposed within a shortest circumference of a closed curve among closed curves within which the slope member and the roller shaft support are disposed in a state in which the roller shaft support is rotated.

A tensioning assembly for a cable drag conveyor. The conveyor includes a head pulley mounted on a head pulley shaft positioned in a head pulley housing and a tail pulley mounted on a tail pulley shaft positioned in a tail pulley housing, infeed and discharge conveyor tubes interconnecting the head pulley housing and the tail pulley housing, and an endless rope having conveying disks attached to the rope positioned in the infeed and discharge conveyor tubes and around the head pulley and tail pulley. The tail pulley housing is positioned in a stationary position in relation to the head pulley and the head pulley housing. The tail pulley shaft and tail pulley is positioned on the tail pulley housing for movement in relation to the tail pulley housing, the head pulley and the head pulley housing. A tensioner moves the tail pulley to maintain the tail pulley at a distance in relation to the head pulley that results in correct tension on the rope during its travel through the cable drag conveyor.

An assembly line, wherein at least one operating branch of fixed length accommodates a number of platforms aligned with one another and with a given travelling direction; each platform being designed to receive a respective vehicle body, feed it in the travelling direction, and subject it to a succession of n assembly operations along the operating branch; each platform being designed for connection to at least one longitudinal extension to assume a total length, which depends on the length of the body carried, and ranges between a minimum length equal to the length of the platform with no extension, and a maximum length; and the length of the operating branch being equal to n times the maximum length.

In some embodiments, apparatus useful for assisting in controlling the discharge of material onto a conveyor from a material dispenser includes a carrier, first and second side restrictors extending downwardly from the carrier and at least one wiper extending downwardly from the carrier and transverse to the side restrictors. The side restrictors are configured to assist in preventing at least some material from overflowing off the sides of the conveyor, while the wiper is configured to level the top of at least some of the material dispensed on the conveyor.

A door transportation method in a vehicle body assembly line, in which the vehicle body is placed and transported on a vehicle body transportation carriage of a floor conveyer, and thereby components are assembled to the vehicle body, includes: placing and transporting the door, which is detached from the vehicle body, on a door placing section arranged on a base stand of the vehicle body transportation carriage.

A mobile platform has a separate and independent linear actuator pivotally connected near each opposite end of the platform where there is a contact limit switch that when triggered by contact with the side of a flatbed, stops movement of the actuator, and thus stops movement of the platform, toward the side of the flatbed. Because each of the two actuators is pivotally connected to its respective end of the platform and moves independently of the other, each end of the platform can stop moving toward the flatbed before or after, depending on how the flatbed is misaligned, the other end of the platform stops moving toward the flatbed. In this way the platform self-aligns to the alignment of the flatbed and avoids the need to reposition a flatbed that is not precisely aligned parallel to the central axis of the loading bay.

A climbing safety assembly for securing a ladder to a stanchion includes a plate that may abut a stanchion so the plate extends laterally away from the stanchion. The plate selectively engages a ladder. The ladder is retained proximate the stanchion so the ladder may be safely climbed by a user. A hook is operationally coupled to the plate. The hook may selectively engage the stanchion so the hook retains the plate on the stanchion. A belt is operationally coupled to the plate. The belt may be extendable around the stanchion so the plate is retained on the stanchion.

A tether device includes a magnetic base; a pole having a first end attached to the magnetic base; and a connector or clip attached at a second end of the pole, for removably connecting the tethering device to a user. Also, a method for tethering a user to a hull of a vessel including the steps of providing a tether device having a magnetic base, a pole having a first end attached to the magnetic base, and a connector or clip attached at a second end of the pole; connecting the connector or clip to the user; and engaging the magnetic base with the hull of the vessel.

This disclosure describes embodiments of novel line dispensing devices and methods for dispensing and retracting a line of a line dispensing device.

A retractable step assembly for a vehicle includes a track assembly mounted on a vehicle frame beneath a workbed, a step assembly, and a pivot assembly that engages the track and step assemblies together. The step assembly moves between a storage position where it is disposed between tracks of the track assembly, and an operational position where it extends outwardly from the tracks, through an aperture in the vehicle's wall panel, and angles downwardly toward the ground. A foldable handrail on the step assembly is selectively movable between a collapsed position and an extended position. The handrail is in the extended position when the step assembly is operational and folds to the collapsed position when the step assembly is stored. First and second supports are provided for the step assembly to rest upon when in either of the storage position and the operational position.

Self-locking bi-foldable load bearing segments are disclosed that can be used in applications such as ladders or ramp. First and second sections of the segment are foldably coupled to transition between an open configuration and a folded configuration. The first and second sections can include rungs pivotally attached to rails that can be further transitioned from the folded configuration to a collapsed configuration, but not transitioned from the open configuration to the collapsed configuration. Openings in the side walls of the rails allow the rungs to pivot in one direction, but not an opposite direction. In the open configuration, the openings of the first and second sections may be oriented opposite, and the direction of allowed rotation of the rungs of the first section and second section are opposite, restricting compression of the rails together. In the folded configuration, the openings of the first and second sections can be oriented the same to allow rotation of the rungs and compression of the rails together.

An improved ladderway system 30 for an underground raise. The system comprises an elongate tube 32 made of a suitably rigid plastics material and adapted to be received in the raise. The tube has a series of steps 34 moulded into an interior side wall thereof so as to form a ladder extending substantially the full length of the tube 32.

A sensor signal processing device includes an AD conversion section, a filter section, a timing signal generation section, and an arithmetic section. The timing signal generation section generates a signal synchronized with a crank angle of an engine based on a signal indicating the crank angle and generates a data acquisition timing signal by compensating the signal synchronized with the crank angle with a delay time of the filter. The arithmetic section acquires a plurality of sensor signals, which is transmitted from a sensor, converted from an analog signal to a digital signal by the AD conversion section, and filtered by the filter section, in a term before and after receiving the data acquisition timing signal and generates a data synchronized with the data acquisition timing signal.

A linear alternator assembly is provided that includes a block defining a cylinder. The cylinder block has inlet ports at which fluid enters the cylinder, exhaust ports at which fluid is exhausted from the cylinder, and a fuel port. Energizable coils surround the cylinder. A first and a second magnetic or magnetizable piston are contained within the cylinder and are positionable within the cylinder in response to energization of selective ones of the coils and combustion of fuel within the cylinder to selectively establish a four-stroke working cycle having an intake stroke, a compression stroke, an expansion stroke, and an exhaust stroke, producing at least one of compressed gas and electrical energy. The four-stroke working cycle may be varied to adapt to changes in power demanded, thereby balancing required output power with efficiency considerations.

A venturi mixing valve assembly includes three open-ended tubular sections. A first section, coupled to a supply of a first gas and a supply of a second gas, has a sleeve defined therein wherein an annular channel open on one end thereof is defined between the sleeve and an inner surface of the first section. A second section defines an annular region with a plurality of holes and a venturi region coupled to the annular region. The annular region circumscribes at least a portion of the first section's sleeve. A third section is threadably coupled to outer surfaces of the first and second sections such that rotation of the third section in a first direction causes the first and second sections to move axially towards one another, while rotation of the third section in a second direction causes the first and second sections to move axially away from one another.

A lubricating configuration in a two-stroke cycle, opposed-piston engine for a piston wristpin minimizes losses in oil pressure at the wristpin as the piston approaches bottom center and reduces the required oil supply pressure to the engine. The wristpin is constructed to absorb and store oil pressure energy when oil pressure at the wristpin is high, and to release that stored energy to pressurize the oil at the wristpin when connecting rod oil pressure is low.

A flow limiter for a fuel system is provided. The flow limiter includes a self-contained portion that enables testing of the flow limiter prior to assembly into a fuel system. A housing of the flow limiter is arranged to provide reduced or no pressure differential across a wall of the housing, permitting the housing to be reduced in size and thickness and providing improved consistency of operation.

A vapor purge valve in an engine is provided. The vapor purge valve includes a purge valve inlet, a purge valve outlet, and a muffler including a housing at least partially enclosing a diffuser in fluidic communication with the purge valve inlet and the purge valve outlet.

As one example, a fuel rail assembly for supplying pressurized fuel to a plurality of cylinders of an engine is provided. The fuel rail assembly includes a fuel rail housing defining an internal fuel rail volume having at least a first region and a second region; a fuel separation membrane element disposed within the fuel rail housing that segregates the first region from the second region. The membrane element can be configured to pass a first component of a fuel mixture such as an alcohol through the membrane element from the first region to the second region at a higher rate than a second component of the fuel mixture such as a hydrocarbon. The separated alcohol and hydrocarbon components can be provided to the engine in varying relative amounts based on operating conditions.

A system for a cylinder head is provided. The system comprises a cam cover mounted on the cylinder head and including an oil separator and a coil on plug (COP) coupled to the oil separator via a snap-fit connection. The snap-fit connection holds the coil-on-plug in position and may provide a lower cost alternative to existing systems of retaining coil-on-plugs on a cam cover.

Embodiments of systems and methods for tuning a turbine are provided. In one embodiment, a method may include receiving at least one of a measured operating parameter or a modeled operating parameter of a turbine during operation; and tuning the turbine during operation. The turbine may be tuned during operation by applying the measured operating parameter or modeled operating parameter or parameters to at least one operational boundary model, applying the measured operating parameter or modeled operating parameter or parameters to at least one scheduling algorithm, comparing the output of the operational boundary model or models to the output of the scheduling algorithm or algorithms to determine at least one error term, and closing loop on the one error term or terms by adjusting at least one turbine control effector during operation of the turbine.

A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.

A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

Various systems and methods for implementing fuse-based integrity protection are described herein. A system for validating a read-only memory (ROM), the system comprising a ROM reader logic, implemented at least partly in hardware, to: access a read-only memory (ROM) having a plurality of permanently programmable electric couplings (PPECs), the PPECs having been programmed; survey a number of permanently altered PPECs in the set of PPECs to produce a counter value; read a binary representation of the counter value from PPEC values stored as a PPEC signature; and read a binary representation of the binary complement of the counter value from PPEC values in the PPEC signature; and a ROM validation logic, implemented at least partly, in hardware, to verify the integrity of the ROM using a combination of at least two of: the counter value, the binary representation of the counter value, and the binary representation of the binary complement of the counter value.

A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit lines. Firstly, a selected memory cell of the memory array is determined, wherein one of the plural bit lines connected with the selected memory cell is a selected bit line and the other bit lines are unselected bit lines. Then, the unselected bit lines are precharged to a precharge voltage. Then, the selected bit line is connected with the data line, and the data line is discharged to a reset voltage. After a cell current from the selected memory cell is received, a voltage level of the data line is gradually changed from the reset voltage. According to at least one result of comparing a voltage level of the data line with a comparing voltage, an output signal is generated.

The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

A compact CMOS anti-fuse memory cell. In one aspect, an apparatus includes an N− well and an anti-fuse cell formed on the N− well. The anti-fuse cell includes a lightly doped drain (LDD) region deposited in the N− well, an oxide layer deposited on the N− well and having an overlapping region that overlaps the LDD region, and a control gate deposited on the oxide layer, wherein a bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the LDD region exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the LDD region, and wherein the leakage path is confined to occur in the overlapping region.

A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.

A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a memory element. In the case where the transistor is an n-channel transistor, a negative potential is supplied to a back gate in holding memory. The supply of the negative potential is stopped while the negative potential is held in the back gate. In the case where an increase in the potential of the back gate is detected, the negative potential is supplied to the back gate.

A semiconductor memory device may include: a plurality of memory mats; and a plurality of sense amplifier arrays arranged alternately with the memory mats, each sense amplifier array being suitable for sensing and amplifying data of memory mats adjacent thereto, wherein during a data sensing operation to a memory mat among the plurality of memory mats, in addition to a sense amplifier for the memory mat and sense amplifiers positioned immediately above and below the sense amplifier for the memory mat, at least one additional sense amplifier closest to the sense amplifier for the memory mat is also activated for providing additional amplification.

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.

According to one embodiment, a semiconductor storage apparatus includes a memory cell array and a read circuit. The memory cell array includes a memory cell which is connected to a word line. A threshold voltage of the memory cell corresponds to a data value of multiple bits. The read circuit receives designation of one bit among the multiple bits, applies a first reading voltage and a second reading voltage corresponding to the designated bit to the word line, senses ON or OFF of the memory cell for each reading voltage, and outputs a first sensed value and a second sensed value after performing the sensing for each reading voltage. The first sensed value is a sensing result in a case where the first reading voltage is applied. The second sensed value is a sensing result in a case where the second reading voltage is applied.

A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.

A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit line. The second string includes third and fourth transistors and second cell transistors coupled in series between the source line and the bit line. During a read, a gate of the fourth transistor is applied with a voltage to turn off the transistor, and after start of application of voltages to the first cell transistors, the gate of the fourth transistor is applied with a voltage substantially the same as a voltage applied to the source line.

According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

According to one embodiment, a semiconductor storage device includes a memory cell array having memory cell capable of holding N-bit data; and a sense amplifier comprising a first latch holding information on a threshold distribution, a second latch holding write data, and a third latch holding lower information of the N-bit data, and supplying a first to a fourth voltages to the memory cell to write the data to the memory cell using the first to fourth voltages. The sense amplifier supplies the first to third voltages to the memory cell based on information in the second and the third latches, and based on a result of transfer of the information held by the first latch to the second latch, supplies the fourth voltage or the first voltage to the memory cell.

According to one embodiment, a semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.

A memory system may include a memory device including 0th to N-1th memory blocks, wherein N is a positive integer; and a controller having a first list and a second list, wherein the first list includes 0th to N-1th erase count values respectively for the 0th to N-1th memory blocks, wherein the second list includes 0th to N-1th difference values respectively for the 0th to N-1th memory blocks, wherein each of the 0th to N-1th difference values is a difference between an average value of the 0th to N-1th erase count values and each of the 0th to N-1th erase count values, wherein the controller selects a source block and a target block among the 0th to N-1th memory blocks depending on the 0th to N-th erase count values included in the first list and the 0th to N-1th difference values included in the second list to perform a wear leveling between the source block and the target block.

A array of electrically programmable fuse (eFuse) units includes at least one connecting switch connecting two adjacent eFuse units. Each eFuse unit includes an eFuse, a write switch for passing through a first portion of a write current, a read/write switch for passing through a second portion of the write current or a read current, and a common node. The eFuse, the write switch, the read/write switch, and the at least one connecting switch are connected to each other at the common node. By turning on and off the at least one connecting switch, the current is split among the eFuse units, so that the size of the write switch can be reduced, thus reducing the total area of the array.

Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The input/output (I/O) drive controller generates drive control signals and an input control signal for driving first and second global I/O lines in a first test mode or a second test mode. The data I/O unit drives the first global I/O line in response to an input data when a write operation is executed in the first test mode and to drive the first and second global I/O lines in response to the drive control signals when the write operation is executed in the second test mode. The data transmitter transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line in a memory cell array portion when the write operation is executed in the first test mode. The data transmitter also transfers the data on the first and second global I/O lines onto the first and second local I/O lines to store the data on the first and second global I/O lines in the memory cell array portion when the write operation is executed in the second test mode. Related methods are also provided.

Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.

A method for fabricating a semiconductor device and a method for operating the semiconductor device are provided. The method for fabricating a semiconductor device includes forming a first electrode layer; forming a material layer, including conductive path components, over the first electrode layer; forming a second electrode layer over the material layer; performing a forming operation, which includes initially creating, in the material layer, a conductive path that electrically connects the first electrode layer to the second electrode layer by applying one of a predetermined voltage and a predetermined current between the first and second electrode layers, the conductive path including the conductive path components; and performing a first heat-treatment process at a predetermined temperature that removes some of the conductive path components from the conductive path, wherein a resistance state of the material layer changes based on the creation or dissolution of the conductive paths.