A vehicle notification sound emitting apparatus is basically provided with a first sound emitting device, a second sound emitting device and a notification sound control device. The first sound emitting device emits a first intermittent notification sound inside a cabin interior of a vehicle. The second sound emitting device emits a second intermittent notification sound outside of the cabin interior of the vehicle. The notification sound control device operates the first and second sound emitting devices to separately emit the first and second intermittent notification sounds in at least a partially overlapping pattern in response to occurrence of a vehicle condition to convey a same type of vehicle information to both inside and outside of the cabin interior of the vehicle. The notification sound control device includes a cabin interior-exterior notification sound synchronizing section that is configured to synchronize the first and second intermittent notification sounds.

A method of patterning a plurality of layers of a work piece in a series of writing cycles in one or a plurality of write machines, the workpiece being deviced to have a number of N layers and layers of the workpiece having one or a plurality of boundary condition(s) for pattern position, the method comprising the steps of: determining the boundary conditions of layers 1 to N, calculating deviations due to the boundary conditions and calculating a compensation for the deviation of the first transformation added with the assigned part of the deviation due to the boundary conditions.

A plurality of Field Programmable Gate Arrays (FPGA), high performance transceivers, and memory devices provide a verification module for timing and state debugging of electronic circuit designs. Signal value compression circuits and gigabit transceivers embedded in each FPGA increase the fanout of each FPGA. Ethernet communication ports enable remote software debugging of processor instructions.

A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.

A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.

This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation effect(s) in a circuit simulation, a simulated defect signal level is produced. More specifically, the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and a simulated input signal level of a simulated input signal. As such, the charge degradation effect(s) are simulated externally with respect to the in silico active semiconductor component. In this manner, the in silico active semiconductor component does not need to be reprogrammed in order to simulate charge degradation effects.

A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

A method includes providing a design of a semiconductor device such as a stacked CMOS device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based on at least one predetermined criterion. Each respective one of the at least one first type of circuit element is to be assigned to a respective designated one of the plurality of tiers. The method further includes dividing the remainder of the plurality of circuit elements into at least two groups of circuit elements based on circuit density, and assigning the at least one first type of circuit element and the at least two groups of circuit elements to respectively different ones of the plurality of tiers of the semiconductor device.

An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

In a method for fracturing or mask data preparation or mask process correction for charged particle beam lithography, a plurality of shots are determined that will form a pattern on a surface, where shots are determined so as to reduce sensitivity of the resulting pattern to changes in beam blur (βf). In some embodiments, the sensitivity to changes in βf is reduced by varying the charged particle surface dosage for a portion of the pattern. Methods for forming patterns on a surface, and for manufacturing an integrated circuit are also disclosed, in which pattern sensitivity to changes in βf is reduced.

A method for mask data preparation or mask process correction is disclosed in which a set of charged particle beam shots is determined which is capable of forming a pattern on a surface, wherein critical dimension uniformity (CDU) of the pattern is optimized. In some embodiments the CDU is optimized by varying at least two factors. In other embodiments, model-based techniques are used. In yet other embodiments, the surface is a reticle to be used in an optical lithographic process to form a pattern on a wafer, and CDU on the wafer is optimized.

A method of creating a datasheet includes obtaining integrated circuit data from at least one data source, creating a data structure including the integrated circuit data obtained from the at least one data source, and creating a datasheet using data contained in the data structure. The datasheet is created in a human-readable format.

A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least partly on the generated signal behaviour description, and performing gate-level simulation using the generated gate-level stimuli to generate gate-level activity data for the IC design. In one embodiment, generating the signal behaviour description includes performing Register Transfer Level (RTL) simulation of the IC design, and generating the gate-level netlist includes performing RTL synthesis. The RTL simulation and RTL synthesis are performed on RTL data for the IC design.

A method and system for optical proximity correction (OPC) is disclosed in which a set of shaped beam shots is determined which, when used in a shaped beam charged particle beam writer, will form a pattern on a reticle, where some of the shots overlap, where the pattern on the reticle is an OPC-corrected version of an input pattern, and where the sensitivity of the pattern on the reticle to manufacturing variation is reduced. A method for fracturing or mask data preparation is also disclosed.

A circuit-design support method includes obtaining information for a circuit having a logic circuit in which signal lines are connected to input terminals, signals of the signal lines being output via the logic circuit; obtaining information concerning a control circuit that has a first flip-flop for scanning and that can control a value of a given signal line by a value set by the first flip-flop; selecting, based on the circuit information, a second flip-flop at an output destination of a signal from the logic circuit, among second flip-flops of the circuit; and generating, based on the control circuit information, information indicating a serial connection of the control circuit between an output source of the signal of the given signal line and the given signal line and a connection of a data input terminal of the first flip-flop and an output terminal of the selected second flip-flop.

A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective assertions for each of the identified clock signals and identifying potential glitchy logic in respective clock paths for each of the identified clock signals. Finally, the technique includes inserting, at the potential glitchy logic, glitches in each of the respective clock paths of the original RTL file to provide a modified RTL file and executing an RTL simulation using the modified RTL file and the respective assertions.

Methods and systems are described for placing arithmetic operators on a programmable integrated circuit device (e.g., a PLD). Placement of arithmetic operators of a data flow graph in one of multiple regions (e.g., a region of DSP circuitry blocks or a region of logic fabric circuitry) on the programmable integrated circuitry device may be determined (e.g., randomly). A score related to the performance of the graph (e.g., a score related to data flow graph routing delays or area consumed by the data flow graph) may be determined and this process may be repeated after one of the arithmetic operators of the data flow graph is moved. The placement of arithmetic operators that corresponds to the best value for the score related to the performance of the data flow graph may be stored. Accordingly, more arithmetic operators may be included on a programmable integrated device than in conventional devices.

A layout-legalizing system modifies a portion of a circuit layout that is selected by a user to generate a modified portion that satisfies a set of technology constraints and a set of design constraints. The system receives as input the set of technology constraints which a semiconductor manufacturing foundry requires the circuit layout to satisfy for manufacturability purposes. The system also receives a set of design constraints from the user which restricts how objects in the portion of the circuit layout can be modified to satisfy the set of technology constraints. The system can further receive a selection input from the user which identifies the portion of the circuit layout which is to be legalized. The system then modifies the identified portion of the circuit layout to obtain a modified portion which satisfies the set of design constraints and at least a subset of the set of technology constraints.

Disclosed are methods, systems, and articles of manufactures for implementing physical designs by using multiple force models to iteratively morph a layout decomposition. In addition to attractive force model(s) or repulsive force model(s), the physical implementation also uses a containment force model for grouping multiple design blocks or for confining a node of a cell within the boundary of a container. Another aspect is directed at deriving a first force model at the first hierarchical level from a second force model at the second hierarchical level by directly modifying the second model based at least in part on characteristic(s) of the first hierarchical level and of the second hierarchical level. In a design with multiple hierarchies, a cell-based force model is also used to ensure child nodes of a parent cell stay within a close proximity of the parent node of the parent cell.

Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value.

The present invention is directed to provide a resist remover composition for semiconductor substrate which enables to remove a resist simply and easily in the photolithography process in the semiconductor field, and a method for removing a resist comprising that the composition is used. The present invention relates to a resist remover composition for semiconductor substrate, comprising [I] a carbon radical generating agent, [II] an acid, [III] a reducing agent, and [IV] an organic solvent, and having pH of lower than 7, and a method for removing a resist, comprising that the composition is used.

A cleaning composition for sanitizing and/or disinfecting hard surfaces, comprising: a cationic biocide, surfactant and low levels of VOC solvents. The cleaning composition is adapted to clean a variety of hard surfaces without leaving behind a visible residue and creates low levels of streaking and filming on the treated surface. The cleaning composition contains less than 5% by weight of VOCs. The cleaning composition may be used alone as a liquid or spray formulation or in combination with a substrate, for example, a pre-loaded cleaning wipe.

A composition is described containing a branched nonionic surfactant of Formula (I): (I) wherein x is a real number from 1 to 11, y is a real number from 1 to 20, R 1 is an alkyl group having 1 to 3 carbon atoms, R 2 is an alkyl group having 4 to 6 carbon atoms, and a primary 5 alcohol ethoxylate.

Provided is an aqueous cleaning composition comprising at least one surfactant, xanthan gum, and a carbonate salt, wherein the composition has a turbidity of less than 16 NTU. Also provided is a method of cleaning a substrate by applying the cleaning composition to the substrate.

The present invention provides personal care compositions comprising a carrier and a mixture of essential oil components having specific levels of eucalyptol, terpene materials and auxiliary fragrance materials. The compositions herein gentle to skin and have a fragrance and activity similar if the composition were made using the pure extracted essential oil.

The present invention is a solid rinse aid composition and methods of making and using the same. Applicants have surprisingly found that the crystal modifier sodium xylene sulfonate (short chain alkyl benzene or alkyl naphthalene sulfonates) at higher percentage can act as a solidification agent. The solid rinse aid composition generally includes an short chain alkyl benzene or alkyl naphthalene sulfonates solidification agent and an effective amount of a surfactant which can include a sheeting agent component, defoamer component and/or association disruption agent. The solid rinse aid composition may be phosphate-free, aminocarboxylate-free, and GRAS if desired.

Resist stripping agents useful for fabricating circuits and/or forming electrodes on semiconductor devices for semiconductor integrated circuits and/or liquid crystals with reduced metal and metal alloy etch rates (particularly copper etch rates and TiW etch rates), are provided with methods for their use. The preferred stripping agents contain low concentrations of resorcinol or a resorcinol derivative, with or without an added copper salt, and with or without an added amine to improve solubility of the copper salt. Further provided are integrated circuit devices and electronic interconnect structures prepared according to these methods.

A gel surfactant composition suitable for hard surface cleaning, washing clothes and dishes, and which can be employed for household, institutional and/or industrial applications, composed by water and a) nonionic surfactants in the range of 1 to 50%, b) a cationic surfactant or association of cationic surfactants in the range of 20 to 50% and c) optionally amphoteric surfactants.

The invention relates to compositions and methods of treatment employing compositions comprising polyelectrolyte complexes. The compositions include a water-soluble first polyelectrolyte bearing a net cationic charge or capable of developing a net cationic charge and a water-soluble second polyelectrolyte bearing a net anionic charge or capable of developing a net anionic charge. The total polyelectrolyte concentration of the first solution is at least 110 millimolar. The composition is free of coacervates, precipitates, latex particles, synthetic block copolymers, silicone copolymers, cross-linked poly(acrylic) and cross-linked water-soluble polyelectrolyte. The composition may be a concentrate, to be diluted prior to use to treat a surface.

A new general purpose foaming agent having application as drilling fluid foaming agents or as any foaming agent needed an a wide variety of applications is disclosed, where the agent includes at least one anionic surfactant, at least one cationic surfactant, and mixtures thereof and one or more zwitterionic compounds. A method for using the foaming agent in capillary coiled tubing application is also disclosed. The foaming agents can also include additive to augment the properties of the foaming agent for a given application.

Disclosed is a cleansing composition containing from about 6% to about 20% of at least one nonionic surfactant; from about 3% to about 10% of at least one amphoteric surfactant; from about 2% to about 8% of at least one anionic surfactant; and from about 0.1% to about 5% of at least one cationic conditioning surfactant, cationic conditioning amine, or a mixture thereof; wherein the amount of nonionic surfactant present in the final composition is greater than the amount of the amphoteric surfactant, and the ratio of the nonionic surfactant (a) to anionic surfactant (c) is at least about 1.9 as much as the anionic surfactant, based on the weight percent of each surfactant in the final composition.

A liquid detergent composition containing (A) 10 to 70 mass % of a nonionic surfactant, (B) 1 to 15 mass % of an anionic surfactant, (C) 0.01 to 2 mass % of a protease, and (D) 0.001 to 0.1 mass % of at least one compound selected from the group consisting of thiazole-based compounds and sulfur-containing amino acids.

The invention relates to compositions including a hypohalite or hypochlorous acid and a soluble salt of 2,4,6 mesitylene sulfonate. The compositions may include a surfactant, a buffer, or combinations thereof. Other adjuvants may also be present. Such compositions do not require the inclusion of high concentrations of sodium hydroxide or other soluble hydroxide salts to drastically increase pH (and thus stability), although such hydroxides may be present if desired.

A method for softening laundry employs a softening composition, which includes at least one thickener containing a cationic polymer obtained by polymerization: of a cationic monomer;of a monomer with a hydrophobic nature, of formula (I): wherein R1=H or CH3 R2=alkyl chain having at least 16 carbon atomsX═O, m≧5, y=z=0, orX═NH, m≧z≧5, y=0, orX═NH, m≧y≧5, z=0, of a nonionic monomer.

A rinse-off composition, such as a shampoo, hair conditioner or shower gel, comprising a rinse-off composition base, lactoyl ethanolamine and at least one compound selected from the group consisting of N-(4-cyanomethylphenyl) p-menthanecarboxamide and N-(2-pyridin-2-ylethyl) p-menthanecarboxamide. The compositions provide a pleasant, long-lasting cooling sensation.

An elongated segmented soap bar is segmented longitudinally into a plurality of soap bodies separate and discrete from one another. Adjacent soap bodies are movable with respect to one another between at least two different configurations including at least an arc configuration with the plurality of soap bodies disposed in an arc. At least one coupler couples the plurality of soap bodies together to allow the adjacent soap bodies to move with respect to one another between the at least two different configurations.

Methods employing detergent compositions effective for reducing soil redeposition and accumulation on hard surfaces are disclosed. The detergent compositions employ phosphinosuccinic acid adducts in combination with an alkalinity source and gluconic acid or salts thereof, copolymers of acrylic acid and maleic acids or salts thereof, sodium hypochlorite, sodium dichloroisocyanurate or combinations thereof.

Gemini surfactants of bis-N-alkyl polyether, bis-N-alkenyl polyether, bis-N-cycloalkyl polyether, bis-N-aryl polyether bis-beta or alpha-amino acids or their salts, are produced for use as multifunctional corrosion inhibitors, which protect and prevent corrosion of ferrous metals exposed to acidic, basic and neutral liquids when transporting or storing crude oil and liquid fuels. The surfactants are also used to inhibit corrosion of equipment and pipes used in cooling systems in petroleum and petrochemical equipment. The Gemini surfactants have the structural formula:

The present invention relates to an enzyme composition comprising enzyme containing polymer particles, which is useful for detergent compositions, in particular for liquid detergent compositions. In these enzyme containing particles, the particles comprise i) at least one enzyme, and ii) at least one polymer P, which is selected from homo- and copolymers having a C—C-backbone, wherein the C—C-backbone carries carboxylgroups, which may be present in the acidic form or in the neutralized form, and wherein the C—C-backbone comprises hydrophobic repeating units.

This invention relates to extend the benefits of using hypochlorite compounds such as sodium hypochlorite to clean and disinfect articles while reducing or eliminating the side effects of treating an article with a strong oxidant material. The invention relates to a single step process involving mixing of precursor compositions of a suitable hypohalite or hypohalous acid with a solution of a reducing agent. Optionally a buffer may be present in either or both precursor compositions, such that at time of use such active hypohalous acid concentration in the resulting aqueous mixture remains at a sufficient activity level to effect one or more desired benefits against a target substrate for a desired period of time. The oxidant is substantially consumed by reaction with the reducing agent after the time needed for achieving the desired benefit has passed.

A non-aqueous liquid cleaning composition for applicators used for applying non-aqueous hair removal compositions to the skin. The composition includes a solubilizing oil effective for solubilizing the non-aqueous hair removal composition, e.g., mineral oil, and an effective antibacterial amount of an antibacterial agent, e.g., triclosan. The composition may also include fragrances and additional bacteriocides, e.g., phenoxyethanol. When the applicator is contacted with the heated cleaning composition any hair removal composition and bacteria on the applicator are removed therefrom and the applicator is ready for reuse. It is preferred to use surgical stainless steel applicators. Also provided are methods of using these compositions and kits containing, among other items, such compositions and applicators.

Acidic viscoelastic cleaning compositions are disclosed which use non polymer thickening agents. According to the invention, cleaning compositions have been developed using viscoelastic surfactants in acidic cleaning formulations. These provide the dual benefit of thickening as well as an additional cleaning, thereby improving performance. Applicants have also identified several pseudo linking agents which when, used with viscoelastic surfactants provide enhanced viscoelasticity and cleaning.

The present invention is directed to provide a semiconductor surface treating agent; composition which is capable of stripping an anti-reflection coating layer, a resist layer, and a cured resist layer in the production process of a semiconductor device and the like easily and in a short time, as well as a method for treating a semiconductor surface, comprising that the composition is used. The present invention relates to a semiconductor surface treating agent; composition, comprising [I] a compound generating a fluorine ion in water, [II] a carbon radical generating agent; , [III] water, [IV] an organic solvent, and [V] at least one kind of compound selected from a group consisting of hydroxylamine and a hydroxylamine derivative represented by the general formula [1], as well as a method for treating the semiconductor surface, comprising that the composition is used: (wherein R1 represents a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups; R2 represents a hydrogen atom, a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups).

Compositions and methods for treating biofilm formation and growth on a substrate are provided. The composition comprises 1 ppb to 1,000 ppm of at least one D-amino acid and 1 ppm to 60,000 ppm of at least one biocide. The method comprises contacting the substrate with 1 ppb to 1,000 ppm of at least one D-amino acid and 1 ppm to 60,000 ppm of at least one biocide. The compositions and methods are effective for preventing, reducing or eliminating biofilm formation or biofilm growth or both, as well as eradicating established, recalcitrant biofilms, particularly biofilms comprising sulfate reducing bacteria that are known to cause microbiologically influenced corrosion, biofouling, or both.

An aqueous compressed gas aerosol formulation in combination with a lined steel can, which may also optionally be tin plated, to provide corrosion stability, fragrance stability and color stability. An aerosol formulation of particular advantage for use is an air and/or fabric treatment formulation. The combination provides a compatibility which allows for the ability to use a broader fragrance pallet for the air and/or fabric treatment formulation which is aqueous based in major proportion. The formulation includes, in addition to an aqueous carrier, a fragrance, nonionic surfactant(s) or a blend of nonionic surfactant(s) and cationic surfactant(s), a compressed gas propellant(s), pH adjuster(s), and corrosion inhibitor(s). The formulation has a pH of about 8 to less than 10. The corrosion inhibitor(s) is (are) mild in strength and used in a minor amount.

A granulated foam control composition comprises a foam control agent based on a polydiorganosiloxane fluid, an organic additive of melting point 45″17C to 100° C. comprising a polyol ester, a water-soluble particulate inorganic carrier and a polymer having a net cationic charge. The mean number of carbon atoms in the organo groups of the polydiorganosiloxane fluid is at least 1.3. The foam control agent includes a hydrophobic filler dispersed in the polydiorganosiloxane fluid, and optionally an organosilicone resin. The polyol ester is miscible with the polydiorganosiloxane fluid.

The invention relates to compositions, methods of use, and methods of manufacture for an intercalated bleach compound and compositions thereof. The intercalated bleach compound has the formula Mx(OCl)y(O)m(OH)n where M is an alkaline earth metal such as magnesium, calcium or mixture thereof. The values of x and y independently equal any number greater than or equal to 1 (e.g., 1, 2, 3, 4, etc.), and m and n independently equal any number greater than or equal to 0 (e.g., 0, 1, 2, 3, 4, etc.), but m and n are not both 0. In addition, the molar ratio of the alkaline earth metal (e.g., magnesium or calcium) to hypochlorite is at least 3:1. In other words, x is ≧3y. The compounds exhibit excellent stability, little or no chlorine bleach odor, exhibit excellent pH buffering characteristics, and less reactivity with organic materials as compared to alternative chlorine bleach products.

The present invention relates to a skin cleanser composition capable of providing an excellent frictional resistance feeling during rinsing and capable of giving an excellent silky feeling with moisturization to the skin after drying, and to a method for producing the composition. The skin cleanser composition contains a cat ionized hydroxypropyl cellulose (A) and a surfactant (B), and the cationized hydroxypropyl cellulose (A) has an anhydroglucose-derived main chain, and has a degree of substitution with cationized ethyleneoxy group of from 0.01 to 3.0 and a degree of substitution with propyleneoxy group of from 0.01 to 2.9.

A structured soap composition contains, based on 100 parts by weight of said composition, (i) from greater than 0 to about 27 parts by weight of a neutralized fatty acid,(ii) from greater than 0 to about 18 parts by weight of one or more structurant selected from alkanolamide surfactants, fatty alcohols, alkoxylated fatty alcohols, fatty acids, and fatty acid esters,(iii) from 0 to about 15 parts by weight of one or more compounds selected from amphoteric surfactants and zwitterionic surfactants, provided that the total amount of components (i), (ii), and (iii) is greater than or equal to 5 parts by weight, (iv) an amount of electrolyte effective to, in combination with components (i), (ii), and (iii) provide a structured soap composition having an opaque visual appearance and exhibiting a yield strength of greater than 0 Pascals, and(v) water.