When in Constraint Manager, Physical Domain, one can create a new Physical Constraint Class defining specific attributes for a custom rule set. One can then assing this new rule set to a set of nets. To do that it is instructed to create a new Net Class with menu Objects > Create > Net Class. Also on that same menu is available Net Group. Both options create a group that appear in the Constraint Manager Objects Name Column. I have triied both  options and cant really see the difference. 

The Question: What is the difference between creating a Net Class and a Net Group ?  What are the implications ?

Thanks for your help.

Please include a brief summary of how to use it.

Hi, I am uploading a register class, which can be used for modeling hardware registers. I am uploading the source code and examples on how to run it. I also have a user guide which has all the APIs listed and explained. The user guide is ARV.pdf in the attached tar file. I have named the class ARV, which stands for Architect's Register View. It has got very good randomization and coverage features. Users have told me that its better than RAL. You can download it from http://verisilica.info/ARV.php
. There is a limit of 750KB in this cadence website. The ARV file is 4MB. That is why, I am uploading it at this site. I have a big pdf documentation and a doxygen documentation there. That is the reason for the bigger file size. The password to open the ZIP file is ovm_arv. I hope, everyone will use these classes.

Please contact me for any help.
Regards ANil

Just in time for the holidays, inside the posted tar ball is some code to solve 9x9 Sudoku puzzles with the Assertion-Driven Simulation (ADS) capability of Incisive Enterprise Verifier (IEV). Enjoy! Joerg Mueller Solutions Engineer for Team Verify

Hi,

I am currently struggling with measuring the delay between two clocks with a sufficient accuracy. The reference one is a fixed-phase clock, and the other one is a squared clock resulting of a circuit (kind of PLL) synthesis.
As I need to run a large amount of Monte-Carlo simulations in transient noise, I need to improve the simulation speed, while keeping a satisfactory delay measurement accuracy (<0.1ps), more specifically at 0V-crossings of the differential clocks. So I cannot simply set a max timestep <0.1ps as it would be far too long to simulate.
To sum up, I would need a very relaxed timestep on clock up and down levels, and a very short timestep only at rise/fall transitions.

For this purpose, I wrote a Verilog-A script
- using a timmer function to accurately emulate the reference clock 0V-crossing times (and get the related times with $abstime)
- using @(cross to get the 0V-crossing times of the synthesized clock: but this is not accurate enough (I see simulation noise around 3ps in Conservative). Indeed, the "cross" event occures at the simulation time following the effective 0V-crossing time; this could be sometimes >3ps, far not enough accurate for my purpose.
- I have tried to replace the cross with the "above" function, but it hasn't changed anything, whatever the time_tol value I put (<0.1ps for instance), the result is the same as with the "cross" function and the points are larger than >>0.1ps, weirdly.

So I have decided to give up Verilog-A to measure the delay between my two clocks.
I am currently trying to use the "delay" function of the Cadence Calculator as I guess it will "extrapolate" the time between two simulation points and therefore give a more accurate measurement of the 0V-crossing events, but when I try to compute the delay difference between the synthesized clock and the reference clock, it returns "0".

...

Could you please give me hints to dramatically improve my 0V-crossing time measurements while relaxing the simulation time?
- either by helping me in writing a more suitable Verilog-A script
- or by helping me in using the "delay" function of the calculator
- or maybe by providing me a "magic" Skill function?
Using AMS+Multithread simulator...

Thanks a lot in advance for your help and best regards.

Hello,

I find a strange issue when using design variable -> right-click -> copy from cellview in assembler. Cadence version is IC618-64b. 500.9

In fact, I set the value of variable (e.g., AAA = 100), then after I right-click -> copy from cellview, AAA's is updated to other value. In my opinion "copy from cellview" should only update the missing variable to the list, but not change any variable value. 

Is there any mechanism could change variable value when using "copy from cellview"?

Thanks

Hello,

I am using ultrasim Version 18.1.0.314.isr5  64bit 03/26/2019 06:33 (csvcm20c-2).

When I run my netlist, ultrasim is blocked in the first DC stage and takes forever. Then it will fail or never progress. I am using a 22nm BSIMBULK model. I tried to tune different accuracy and convergence aids options but noting works.

 When I run the same netlist with spectre it works fine with no problem.

Also, If I use another model (not BULKSIM), ultrasim will work and converge with no problem.

My first feeling is that ultrasim has a problem with using BSIMBULK model.

Could you please advice,

Thank you,

Kotb

Hi,

This question is related to the constraint measurement criteria used by the Liberate inside view. I am trying to characterize a specific D flip-flop for low voltage operation (0.6V) using Cadence Liberate (V16). 

When the "define_arcs" are not explicitly specified in the settings for the circuit (but the input/outputs are indeed correct in define_cell), the inside view seems to probe an internal node (i.e. master latch output)  for constraint measurements instead of the Q output of the flip flop. So to force the tool to probe Q output I added following coder in constraint arcs :

# constraint arcs from CK => D
define_arc
-type hold
-vector {RRx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type hold
-vector {RFx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type setup
-vector {RRx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type setup
-vector {RFx}
-related_pin CP
-pin D
-probe Q
DFFXXX

with -probe Q liberate identifies Q as the output, but uses Glitch-Peak criteria instead of delay degradation method. So what could be the exact reason for this unintended behavior ? In my external (spectre) spice simulation, the Flip-Flop works well and it does not show any issues in the output delay degradation when the input sweeps.

Thanks

Anuradha

Cadence Liberate Trio Characterization Suite, ARM-based Graviton Processors, and Amazon Web Services (AWS) Cloud have joined forces to cater to the High-Performance Computing, Machine Learning/Artificial Intelligence, and Big Data Analytics sectors. (read more)

Key Findings: Advantest, in mixed-signal SoC design, sees 50X speedup, 25 day test reduced to 12 hours, dramatic test coverage increase.

Trolling through the CDNLive archives, I discovered another gem. At the May 2013 CDNLive in Munich, Thomas Henkel and Henriette Ossoinig of Advantest presented a paper titled “Timing-accurate emulation of a mixed-signal SoC using Palladium XP”. Advantest makes advanced electronics test equipment. Among the semiconductor designs they create for these products is a test processor chip with over 100 million logic transistors, but also with lots of analog functions.They set out to find a way to speed up their full-chip simulations to a point where they could run the system software. To do that, they needed about a 50X speed-up. Well, they did it!

Figure 1: Advantest SoC Test Products

To skip the commentary, read Advantest's paper here. 

Problem Statement

Software is becoming a bigger part of just about every hardware product in every market today, and that includes the semiconductor test market. To achieve high product quality in the shortest amount of time, the hardware and software components need to be verified together as early in the design cycle as possible. However, the throughput of a typical software RTL simulation is not sufficient to run significant amounts of software on a design with hundreds of millions of transistors.  

Executing software on RTL models of the hardware means long runs  (“deep cycles”) that are a great fit for an emulator, but the mixed-signal content posed a new type of challenge for the Advantest team.  Emulators are designed to run digital logic. Analog is really outside of the expected use model. The Advantest team examined the pros and cons of various co-simulation and acceleration flows intended for mixed signal and did not feel that they could possibly get the performance they needed to have practical runtimes with software testbenches. They became determined to find a way to apply their Palladium XP platform to the problem.

Armed with the knowledge of the essential relationship between the analog operations and the logic and software operations, the team was able to craft models of the analog blocks using reduction techniques that accurately depicted the essence of the analog function required for hardware-software verification without the expense of a continuous time simulation engine.

The requirements boiled down to the following:

• Generation of digital signals with highly accurate and flexible timing

• Complete chip needs to run on Palladium XP platform

• Create high-resolution timing (100fs) with reasonable emulation performance, i.e. at least 50X faster than simulation on the fastest workstations

Solution Idea

The solution approach chosen was to simplify the functional model of the analog elements of the design down to generation of digital signal edges with high timing accuracy. The solution employed a fixed-frequency central clock that was used as a reference.Timing-critical analog signals used to produce accurately placed digital outputs were encoded into multi-bit representations that modeled the transition and timing behavior. A cell library was created that took the encoded signals and converted them to desired “regular signals”. 

Automation was added to the process by changing the netlisting to widen the analog signals according to user-specified schematic annotations. All of this was done in a fashion that is compatible with debugging in Cadence’s Simvision tool.  Details on all of these facets to follow.

The Timing Description Unit (TDU) Format

The innovative thinking that enabled the use of Palladium XP was the idea of combining a reference clock and quantized signal encoding to create offsets from the reference. The implementation of these ideas was done in a general manner so that different bit widths could easily be used to control the quantization accuracy.

Figure 2: Quantization method using signal encoding

Timed Cell Modeling

You might be thinking – timing and emulation, together..!?  Yes, and here’s a method to do it….

The engineering work in realizing the TDU idea involved the creation of a library of cells that could be used to compose the functions that convert the encoded signal into the “real signals” (timing-accurate digital output signals). Beyond some basic logic cells (e.g., INV, AND, OR, MUX, DFF, TFF, LATCH), some special cells such as window-latch, phase-detect, vernier-delay-line, and clock-generator were created. The converter functions were all composed from these basic cells. This approach ensured an easy path from design into emulation.

The solution was made parameterizable to handle varying needs for accuracy.  Single bit inputs need to be translated into transitions at offset zero or a high or low coding depending on the previous state.  Single bit outputs deliver the final state of the high-resolution output either at time zero, the next falling, or the next rising edge of the grid clock, selectable by parameter. Output transitions can optionally be filtered to conform to a configurable minimum pulse width.

Timed Cell Structure

There are four critical elements to the design of the conversion function blocks (time cells):

                Input conditioning – convert to zero-offset, optional glitch preservation, and multi-cycle path

                Transition sorting – sort transitions according to timing offset and specified precedence

                Function – for each input transition, create appropriate output transition

                Output filtering – Capability to optionally remove multiple transitions, zero-width, pulses, etc.

Timed Cell Caveat

All of the cells are combinational and deliver a result in the same cycle of an input transition. This holds for storage elements as well. For example a DFF will have a feedback to hold its state. Because feedback creates combinational loops, the loops need a designation to be broken (using a brk input conditioning function in this case – more on this later). This creates an additional requirement for flip-flop clock signals to be restricted to two edges per reference clock cycle.

Note that without minimum width filtering, the number of output transitions of logic gates is the sum of all input transitions (potentially lots of switching activity). Also note that the delay cell has the effect of doubling the number of output transitions per input transition.

Figure 3: Edge doubling will increase switching during execution

SimVision Debug Support

The debug process was set up to revolve around VCD file processing and directed and viewed within the SimVision debug tool. In order to understand what is going on from a functional standpoint, the raw simulation output processes the encoded signals so that they appear as high-precision timing signals in the waveform viewer. The flow is shown in the figure below.

Figure 4: Waveform post-processing flow

The result is the flow is a functional debug view that includes association across representations of the design and testbench, including those high-precision timing signals.

Figure 5: Simvision debug window setup

Overview of the Design Under Verification (DUV)

Verification has to prove that analog design works correctly together with the digital part. The critical elements to verify include:

• Programmable delay lines move data edges with sub-ps resolution

• PLL generates clocks with wide range of programmable frequency

• High-speed data stream at output of analog is correct

These goals can be achieved only if parts of the analog design are represented with fine resolution timing.

Figure 6: Mixed-signal design partitioning for verification

How to Get to a Verilog Model of the Analog Design

There was an existing Verilog cell library with basic building blocks that included:

- Gates, flip-flops, muxes, latches

- Behavioral models of programmable delay elements, PLL, loop filter, phase detector

With a traditional simulation approach, a cell-based netlist of the analog schematic is created. This netlist is integrated with the Verilog description of the digital design and can be simulated with a normal workstation. To use Palladium simulation, the (non-synthesizable) portions of the analog design that require fine resolution timing have to be replaced by digital timing representation. This modeling task is completed by using a combination of the existing Verilog cell library and the newly developed timed cells.

Loop Breaking

One of the chief characteristics of the timed cells is that they contain only combinational cells that propagate logic from inputs to outputs. Any feedback from a cell’s transitive fanout back to an input creates a combinational loop that must be broken to reach a steady state. Although the Palladium XP loop breaking algorithm works correctly, the timed cells provided a unique challenge that led to unpredictable results.  Thus, a process was developed to ensure predictable loop breaking behavior. The user input to the process was to provide a property at the loop origin that the netlister recognized and translated to the appropriate loop breaking directives.

Augmented Netlisting

Ease of use and flow automation were two primary considerations in creating a solution that could be deployed more broadly. That made creating a one-step netlisting process a high-value item. The signal point annotation and automatic hierarchy expansion of the “digital timing” parameter helped achieve that goal. The netlister was enriched to identify the key schematic annotations at any point in the hierarchy, including bit and bus signals.

Consistency checking and annotation reporting created a log useful in debugging and evolving the solution.

Wrapper Cell Modeling and Verification

The netlister generates a list of schematic instances at the designated “netlister stop level” for each instance the requires a Verilog model with fine resolution timing. For the design in this paper there were 160 such instances.

The library of timed cells was created; these cells were actually “wrapper” cells comprised of the primitives for timed cell modeling described above. A new verification flow was created that used the behavior of the primitive cells as a reference for the expected behavior of the composed cells. The testing of the composed cells included had the timing width parameter set to 1 to enable direct comparison to the primitive cells. The Cadence Incisive Enterprise Simullator tool was successfully employed to perform assertion-based verification of the composed cells versus the existing primitive cells.

Mapping and Long Paths

Initial experiments showed that inclusion of the fine resolution timed cells into the digital emulation environment would about double the required capacity per run. As previously pointed out, the timed cells having only combinational forward paths creates a loop issue. This fact also had the result of creating some such paths that were more than 5,000 steps of logic. A timed cell optimization process helped to solve this problem. The basic idea was to break the path up by adding flip-flops in strategic locations to reduce combinational path length. The reason that this is important is that the maximum achievable emulation speed is related to combinational path length.

Results

Once the flow was in place, and some realistic test cases were run through it, some further performance tuning opportunities were discovered to additionally reduce runtimes (e.g., Palladium XP tbrun mode was used to gain speed). The reference used for overall speed gains on this solution was versus a purely software-based solution on the highest performance workstation available.

The findings of the performance comparison were startlingly good:

• On Palladium XP, the simulation speed is 50X faster than on Advantest’s fastest workstation

• Software simulation running 25 days can now be run in 12 hours -> realistic runtime enables long-running tests that were not feasible before

• Now have 500 tests that execute once in more than 48 hours

• They can be run much more frequently using randomization and this will increase test coverage dramatically

Steve Carlson

Key Findings: Many more design teams will be reaching the mixed-signal methodology tipping point in 2015. That means you need to have a (verification) plan, and measure and execute against it.

As 2014 draws to a close, it is time to look ahead to the coming years and make a plan. While the macro view of the chip design world shows that is has been a mixed-signal world for a long time, it is has been primarily the digital teams that have rapidly evolved design and verification practices over the past decade. Well, I claim that is about to change. 2015 will be a watershed year for many more design teams because of the following factors:

• 85% of designs are mixed signal, and it is going to stay that way (there is no turning back)
• Advanced node drives new techniques, but they will be applied on all nodes
• Equilibrium of mixed-signal designs being challenged, complexity raises risk level
• Tipping point signs are evident and pervasive, things are going to change
• The convergence of “big A” and “big D” demands true mixed-signal practices

Reason 1: Mixed-signal is dominant

To begin the examination of what is going to change and why, let’s start with what is not changing. IBS reports that mixed signal accounts for over 85% of chip design starts in 2014, and that percentage will rise, and hold steady at 85% in the coming years. It is a mixed-signal world and there is no turning back!

Figure 1. IBS: Mixed-signal design starts as percent of total

The foundational nature of mixed-signal designs in the semiconductor industry is well established. The reason it is exciting is that a stable foundation provides a platform for driving change. (It’s hard to drive on crumbling infrastructure.  If you’re from California, you know what I mean, between the potholes on the highways and the earthquakes and everything.)

Reason 2: Innovation in many directions, mostly mixed-signal applications

While the challenges being felt at the advanced nodes, such as double patterning and adoption of FinFET devices, have slowed some from following onto to nodes past 28nm, innovation has just turned in different directions. Applications for Internet of Things, automotive, and medical all have strong mixed-signal elements in their semiconductor content value proposition. What is critical to recognize is that many of the design techniques that were initially driven by advanced-node programs have merit across the spectrum of active semiconductor process technologies. For example, digitally controlled, calibrated, and compensated analog IP, along with power-reducing mutli-supply domains, power shut-off, and state retention are being applied in many programs on “legacy” nodes.

Another graph from IBS shows that the design starts at 45nm and below will continue to grow at a healthy pace.  The data also shows that nodes from 65nm and larger will continue to comprise a strong majority of the overall starts. 

Figure 2.  IBS: Design starts per process node

TSMC made a comprehensive announcement in September related to “wearables” and the Internet of Things. From their press release:

TSMC’s ultra-low power process lineup expands from the existing 0.18-micron extremely low leakage (0.18eLL) and 90-nanometer ultra low leakage (90uLL) nodes, and 16-nanometer FinFET technology, to new offerings of 55-nanometer ultra-low power (55ULP), 40ULP and 28ULP, which support processing speeds of up to 1.2GHz. The wide spectrum of ultra-low power processes from 0.18-micron to 16-nanometer FinFET is ideally suited for a variety of smart and power-efficient applications in the IoT and wearable device markets. Radio frequency and embedded Flash memory capabilities are also available in 0.18um to 40nm ultra-low power technologies, enabling system level integration for smaller form factors as well as facilitating wireless connections among IoT products.

Compared with their previous low-power generations, TSMC’s ultra-low power processes can further reduce operating voltages by 20% to 30% to lower both active power and standby power consumption and enable significant increases in battery life—by 2X to 10X—when much smaller batteries are demanded in IoT/wearable applications.

The focus on power is quite evident and this means that all of the power management and reduction techniques used in advanced node designs will be coming to legacy nodes soon.

Integration and miniaturization are being pursued from the system-level in, as well as from the process side. Techniques for power reduction and system energy efficiency are central to innovations under way.  For mixed-signal program teams, this means there is an added dimension of complexity in the verification task. If this dimension is not methodologically addressed, the level of risk adds a new dimension as well.

Reason 3: Trends are pushing the limits of established design practices

Risk is the bane of every engineer, but without risk there is no progress. And, sometimes the amount of risk is not something that can be controlled. Figure 3 shows some of the forces at work that cause design teams to undertake more risk than they would ideally like. With price and form factor as primary value elements in many growing markets, integration of analog front-end (AFE) with digital processing is becoming commonplace.  

Figure 3.  Trends pushing mixed-signal out of equilibrium

The move to the sweet spot of manufacturing at 28nm enables more integration, while providing excellent power and performance parameters with the best cost per transistor. Variation becomes great and harder to control. For analog design, this means more digital assistance for calibration and compensation. For greatest flexibility and resiliency, many will opt for embedding a microcontroller to perform the analog control functions in software. Finally, the first wave of leaders have already crossed the methodology bridge into true mixed-signal design and verification; those who do not follow are destined to fall farther behind.

Reason 4: The tipping point accelerants are catching fire

The factors cited in Reason 3 all have a technical grounding that serves to create pain in the chip-development process. The more factors that are present, the harder it is to ignore the pain and get the treatment relief  afforded by adopting known best practices for truly mixed-signal design (versus divide and conquer along analog and digital lines design).

In the past design performance was measured in MHz with simple static timing and power analysis. Design flows were conveniently partitioned, literally and figuratively, along analog and digital boundaries. Today, however, there are gigahertz digital signals that interact at the package and board level in analog-like ways. New, dynamic power analysis methods enabled by advanced library characterization must be melded into new design flows. These flows comprehend the growing amount of feedback between analog and digital functions that are becoming so interlocked as to be inseparable. This interlock necessitates design flows that include metrics-driven and software-driven testbenches, cross fabric analysis, electrically aware design, and database interoperability across analog and digital design environments.

Figure 4.  Tipping point indicators

Energy efficiency is a universal driver at this point.  Be it cost of ownership in the data center or battery life in a cell phone or wearable device, using less power creates more value in end products. However, layering multiple energy management and optimization techniques on top of complex mixed-signal designs adds yet more complexity demanding adoption of “modern” mixed-signal design practices.

Reason 5: Convergence of analog and digital design

Divide and conquer is always a powerful tool for complexity management.  However, as the number of interactions across the divide increase, the sub-optimality of those frontiers becomes more evident. Convergence is the name of the game.  Just as analog and digital elements of chips are converging, so will the industry practices associated with dealing with the converged world.

Figure 5. Convergence drivers

Truly mixed-signal design is a discipline that unites the analog and digital domains. That means that there is a common/shared data set (versus forcing a single cockpit or user model on everyone). 

In verification the modern saying is “start with the end in mind”. That means creating a formal approach to the plan of what will be test, how it will be tested, and metrics for success of the tests. Organizing the mechanics of testbench development using the Unified Verification Methodology (UVM) has proven benefits. The mixed-signal elements of SoC verification are not exempted from those benefits.

Competition is growing more fierce in the world for semiconductor design teams. Not being equipped with the best-known practices creates a competitive deficit that is hard to overcome with just hard work. As the landscape of IC content drives to a more energy-efficient mixed-signal nature, the mounting risk posed by old methodologies may cause causalities in the coming year. Better to move forward with haste and create a position of strength from which differentiation and excellence in execution can be forged.

Summary

2015 is going to be a banner year for mixed-signal design and verification methodologies. Those that have forged ahead are in a position of execution advantage. Those that have not will be scrambling to catch up, but with the benefits of following a path that has been proven by many market leaders.

Typically, analog designers verify their AMS IP in schematic driven, interactive environment, while SoC designers use a UVM SystemVerilog testbench ran from a command line. In our last MS blog, we talked about automation for reusing SystemVerilog testbench by analog designers in order to verify AMS IP in exactly same context as in its SoC integration, hence reducing surprises and unnecessary iterations.

But, what about other direction: selecting proper AMS IP views for SoC Verification? Manually export netlist from Virtuoso and then manually assemble together all of the files for use with in command line driven flow? Often, there are multiple views for the same instance (RNM, analog behavioral model, transistor netlist). Which one to pick? Who is supposed to update configuration files? We often work concurrently and update the AMS IP views frequently. Obviously, manually selecting correct and most up-to-date AMS IP views for SoC Verification is tedious and error prone. Thanks to Cadence Innovation, there is a better way!

Cadence has developed a Command-Line IP Selector (CLIPS) product as part of the Virtuoso^® environment, which:

• Bridges the gap between MS SoC command-line setup and the Virtuoso-based analog mixed-signal configuration
• Allows seamless importing of AMS IP from the Virtuoso environment into an existing digital verification setup
• Provides a GUI-based and command-line use model, flexible to fit into an existing design flow methodologyCLIPS reads MS SoC command (irun) files, identifies required AMS IP modules, uses Virtuoso ADE setup files to properly netlist required modules, and pulls the AMS IP out of the Virtuoso environment. All necessary files are properly extracted/prepared and package as required for the MS SoC command line verification run. CLIPS setup can be saved and rerun as a batch process to ensure the latest IP from the hierarchy is being simulated.

For more details, please see CLIPS Rapid Adoption Kit at Cadence Online Support page

Cadence_SPB_17.4-2019 + Matlab R2019a

请参考本文档中的步骤进行操作

1，打开BJT_AMP.opj

2，设置Matlab路径

3，打开BJT_AMP_SLPS.slx

4，打开后，设置PSpiceBlock，出现或CEFSimpleUI.exe停止工作

5，添加模块

6，相同

7，打开pspsim.slx

8，相同

9，打开C： Cadence Cadence_SPB_17.4-2019 tools bin

orCEFSimpleUI.exe和orCEFSimple.exe

10，相同

我想问一下如何解决，非常感谢！

If you have one of those Die layouts, which doesn’t have bumps, but rather uses pad shapes and labels to identify I/O locations, then you might be feeling a bit left out of all of this jazz and tango. Hence, today, I am writing to tell you that, fear not, we have a solution for your Die as well.(read more)

The way you need blocks of different sizes and styles to build great Lego masterpieces, a complex WSP-based design requires stitching together routing regions with multiple patterns that follow different WSSPDef periods. Let's see how you can achieve this. (read more)

visit News18 Urdu for latest news, breaking news, news headlines and updates from South 24 Parganas on politics, sports, entertainment, cricket, crime and more.

visit News18 Urdu for latest news, breaking news, news headlines and updates from Prakasam on politics, sports, entertainment, cricket, crime and more.

visit News18 Urdu for latest news, breaking news, news headlines and updates from Chaibasa on politics, sports, entertainment, cricket, crime and more.

visit News18 Urdu for latest news, breaking news, news headlines and updates from Samastipur on politics, sports, entertainment, cricket, crime and more.

મહેસાણાઃમહેસાણામાં યોજાયેલ મહિલા સંમેલનના આયોજક ઉત્તર ગુજરાત પાસ કન્વીનર નરેન્દ્ર પટેલ પર એવો આક્ષેપ થઇ રહ્યો છે કે, સંમેલન માટે કોંગ્રેસ પાસેથી નરેન્દ્ર પટેલે રૂ.૨૫ લાખ લીધા છે. અને આ આક્ષેપ વંદનાબેન પટેલ નામની પાટીદાર મહિલા દ્વારા જ કરવામાં આવ્યો છે.

visit News18 Gujarati for latest news, breaking news, news headlines and updates from Borasad on politics, sports, entertainment, cricket, crime and more.

visit News18 Urdu for latest news, breaking news, news headlines and updates from Balasore on politics, sports, entertainment, cricket, crime and more.

visit News18 Urdu for latest news, breaking news, news headlines and updates from Washim on politics, sports, entertainment, cricket, crime and more.

પાટણ: મહેસાણા ખાતે પાટીદારો દ્વારા આગામી 28મીએ યોજાનાર મહિલા સંમેલનની તડામાર તૈયારીઓ કરાઇ રહી છે ત્યારે મંગળવારેરાત્રે પાટણના સંડેર ગામે પાટીદારો દ્વારા આયોજન માટે બેઠકનું આયોજન કરાયું હતું. ત્યારે બીજી તરફ સંમેલનને નિષ્ફળ બનાવવાના પ્રયાસો પણ ચાલી રહ્યા છે. અને ઉ.ગુ.ના પાસ કન્વિનર નરેન્દ્ર પટેલને ફોન કરી મહેસાણાના શખ્સ દ્વારા મારી નાખવાની ધમકી અપાતા ચકચાર મચી છે.

CDS Bipin Rawan: Air Force રવિવારે કોરોના યોદ્ધાઓને સલામ કરવા Flypast કરશે

Jammu and Kashmirના હંદવાડામાં 5 જવાન શહીદ, આતંકી અથડામણમાં 2 આતંકી ઠાર

Rajasthanમાં BSFના વધુ 12 જવાન પોઝિટિવ, STC સેન્ટરમાં હતા ક્વોરોન્ટાઇન

ઓપરેશન સમુદ્ર સેતુ: INS Jalashwa માલદીવથી 698 ફસાયેલા ભારતીયોને લઈ રવાના

visit News18 Urdu for latest news, breaking news, news headlines and updates from Kolasib on politics, sports, entertainment, cricket, crime and more.

visit News18 Gujarati for latest news, breaking news, news headlines and updates from Sarasvati on politics, sports, entertainment, cricket, crime and more.

visit News18 Urdu for latest news, breaking news, news headlines and updates from Varanasi on politics, sports, entertainment, cricket, crime and more.

જ્યોતિષના જણાવ્યા પ્રમાણે આ પ્રકારની આદતો જીવનમાં સમસ્યાઓ ઊભી કરે છે. આવી સ્થિતિમાં જરૂરી છે કે આપણે રોજિંદી જીંદગીમાં આદતોમાં સુધારો કરવાથી ગ્રહો પણ સારા થશે અને શુભ પરિણામ પણ આપવાનું શરુ કરશે.

વાસ્તુ શાસ્ત્ર પ્રમાણે ઘરમાં ધન સાથે સંકળાયેલી સમસ્યાઓને દૂર કરવા માટે કેટલાક નિયમો છે. આ નિયમોને અપનાવીને ઘરમાં પૈસાની પરેશાની રહેતી નથી.

વાસ્તુ શાસ્ત્ર પ્રમાણે તમારા ઘરમાં વાસ્તુના યોગ્ય નિયમોનું પાલન ન થાય તો ઘરમાં સકારાત્મક ઉર્જાની જગ્યાએ નકારાત્મક ઉર્જા વધારે થઈ જાય છે.

વાસ્તુશાસ્ત્રમાં અગ્ની દિશાનો વિશે, દોષ માનવામાં આવે છે. અગ્ની દેશમાં દોષ હોવાથી વ્યક્તિને અનેક પ્રકારની સમસ્યાનો સામનો કરવો પડે છે. વાસ્તુના જાણકાર પ્રમાણે અગ્ની ખૂામાં દોષને ખતમ કરવા માટે આ દિશમાં લાલ રંગનો એક બલ્બ અથવા તો દીવો એક પહોર અથવા આશરે ત્રણ કલાક સુધી ચાલે.

Fake Message: જનતા કર્ફ્યૂ સમયે તાળી અને થાળી વગાડવાના અવાજ બાદ એક સાઉન્ડ વેબ ક્રિએટ થયો અને કોરોના ભારતમાં નબળો પડી ગયો

નાસાને આવો ત્રીજો ગ્રહ મળ્યો છે જ્યાં જીવન હોવાની સંભાવના છે.

visit News18 Urdu for latest news, breaking news, news headlines and updates from Kasaragod on politics, sports, entertainment, cricket, crime and more.