I'm trying to re-install ORCAD 17.2  in a PC from a DVD which I have upgraded from Win 7 to Win 10 and  now has a new 500GB SSD. While installing I got a Windows Application Error  0xc000007b. When I try to run ORCAD I get the same Error.

Looking for ways to fix this problem.

Hello All,

I'm currently using OrCAD PCB Designer Professional w/ PSpice (version 16.6-2015).  In the 'Design Object Find Filter' side bar, all options are grayed out and unselectable.  I did attempt to 'Reset UI to Cadence Default' without any luck.  A colleague has no issues with the identical file on his computer.  Any guidance would be much appreciated.  Thanks!

George

Hi everybody,

I've created a symbol with custom pad shapes. Everything looks correct in the symbol editor.

And the 3d view looks correct (upside down to show placement)

But when I try to place it on the pcb the 2 "T" shaped pads aren't in the correct location.

I have the pad shape centered on the pad...

with no offset on the padstack editor.

Does anybody know how to fix this?

Thank you!

Hi

i have generated a BOM of my design and one of the parts is showing wrong information than what I specified in the database. I can see that in CIS database that part has been specified a correct information  but when I exported it to bom it shows wrong values.

Hi There,

The variant bom I set gone dissapear. Is there any way to recover this back from the old design file? 

This is the second time it happen to me. Not really sure what could cause this. 

Thanks,

Pornchai

Can anyone tell me how i can supress few strings or integers while reading with $sscanf.

I read a line from a file into a string. there are few strings and integers seperated by white spaces in the line. I am interested in one string which comes at postion 5 in the line. how can i suppress all other strings and integers with $scanf.

i tried the following syntax but it dint work.

 $sscanf(line,"* * * * %s",string_arg);

i am tring to supress first 4 integers/strings in the line.

I want to write a transition coverage on an enumeration. One of the parts of that transition is a queue of the enum. I construct this queue in my constructor. Considering the example below, how would one go about it.

In my coverage bin I can create a range like this A => [queue1Enum[0]:queue1Enum[$]] => [queue2Enum[0]:queue2Enum[$]]. But I only get first and last element then.

typedef enum { red, d_green, d_blue, e_yellow, e_white, e_black } Colors;
 Colors dColors[$];
 Colors eColors[$];
 Lcolors = Colors.first();
 do begin
  if (Lcolors[0].name=='d') begin
   dColors.push_back(Lcolors);
  end
  if (Lcolors[0].name=='e') begin
   eColors.push_back(Lcolors);
  end
 end while(Lcolors != Lcolors.first())

 covergroup cgTest with function sample(Colors c);
   cpTran : coverpoint c{
      bins t[] = (red => dColors =>eColors);   
   }
 endgroup

Hi all,

Is there any tutorial which explains the process of plotting the ISF function for a certain oscillator ?

Thank you.

Hi ,

     I have designed analog IP in cadence ADE and simulated in spectre. All corner results looks good. when i run monte carlo 1000 runs have high current in 125C two runs. Simulated with same setup in different user, all clean.Need to know what type sampling method used and why its not clean with my setup.

Thanks,

Anbarasu

Hello,

I am trying to import multiple verilog modules defined in a single file with "`define" directive in the top using Verilog In. The code below is an example of what my file contains.

When I use the settings below to import the modules into a library, it imports it correctly but completely ignores all `define directive; hence when I simulate using any of the modules below the simulator errors out requesting these variables.

My question: Is there a way to make Verilog In consider `define directives in every module cell created? 

Code to be imported by Cadence Verilog In:

--------------------------------------------------------

`timescale 1ns/1ps
`define PROP_DELAY 1.1
`define INVALID_DELAY 1.3

`define PERIOD 1.1
`define WIDTH 1.6
`define SETUP_TIME 2.0
`define HOLD_TIME 0.5
`define RECOVERY_TIME 3.0
`define REMOVAL_TIME 0.5
`define WIDTH_THD 0.0

`celldefine
module MY_FF (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF
`endcelldefine

`timescale 1ns/1ps
`celldefine
module MY_FF2 (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF2
`endcelldefine

--------------------------------------------------------

I am using the following Cadence versions:

MMSIM Version: 13.1.1.660.isr18

Virtuoso Version: IC6.1.8-64b.500.1

irun Version: 14.10-s039

Spectre Version: 18.1.0.421.isr9

Hello,

I am trying to use calcVal for creating a spec condition from a simulated parameter and although this works perfectly fine in corner simulations, I am having some difficulties in Monte-Carlo (and I will explain).

(I have also read "Using calcVal() and its arguments with ADE Assembler" in Resources > Rapid Adoption Kits but couldn't find any relevant information that would help me address the "issue").

In the above example I am performing a MC simulation which has 2 corners of 10 runs each. I would like to get the minimum value of variable "OC_limit_thres" out of those 10 runs and pass it as my upper limit to a range argument for variable "OC_flag_thres", so the CPK can be calculated.

So the range statement should in reality be like this:

range 32m 44.34m (for corner 0)

range 32m 43.14m (for corner 1)

If I open the Detail - Transpose view in the Results tab, the calcVal("OC_limit_thres" "Currlim_TurnOn_C11") is calculated perfectly fine for each run but here I need one single value out of those 10 runs - in this case the minimum - in order for calcVal to evalute on multiple runs of 1 corner.

How can this be done please?

Thank you in advance for your time.

Hi, 

I want my layout verified by Quantus QRC. But, I can't find the tool bar on the option list ( as show in the picture)

I have tried to install EXT182 and configured it with iscape already, and also make some path settings on .bashrc, .cshrc. But, when I re-source .cshrc and run virtuoso again, I just can't find the toolbar. 

If you have some methods, please let me know.

Thanks a lot!

Appreciated

My virtuoso version is: ICADV12.3

Hi,

I tried to open my layout by Library Manager, but the Virtuoso CIW window sometimes pops up the follow WARNING messages( as picture depicts). Thus, layout can't open.

Sometimes, I try to reconfigure ICADV12.3 by the iscape and restart my VM and then it incredibly works! But, often not!

So, If anyone knows what it is going on. Please let me know! Thanks!

Appreciated so much   

Hello,

I am trying to import (in spectre) an spice model of a ceramic capacitor manufactured by Samsung EM. The link that includes the model is here :-

http://weblib.samsungsem.com/mlcc/mlcc-ec.do?partNumber=CL05A156MR6NWR

They proved static spice model and interactive spice model.

I had no problem while including the static model.

However, the interactive model which models voltage and temperature coefficients seems to not be an ordinary spice model. They provide HSPICE, LTSPICE, and PSPICE model files and I failed to include any of them.

Any suggestions ?

Hello,

I am using Virtuoso 6.1.7.

I am performing the parasitic extraction of a MOM cap array of 32 caps. I use Quantus QRC and I enable field solver. I select “QRCFS” for field solver type and “High” for field solver accuracy. The unit MOM cap is horizontally and vertically symmetric. The array looks like the sketch below and there are no other structures except the unit caps:

Rationally speaking, the capacitance values of the unit caps should be symmetric with respect to a vertical symmetry axis that is between cap16 and cap17 (shown with dashed red line). For example,

the capacitance of cap1 should be equal to the capacitance of cap32

the capacitance of cap2 should be equal to the capacitance of cap31

etc. as there are no other structures around the caps that might create some asymmetry.

Nevertheless, what I observe is the following after the parasitic extraction:

As it can be seen, the result is not symmetric contrary to what is expected. I should also add that I do not observe this when I perform parasitic extraction with no filed solver.

Why do I get this result? Is it an artifact resulting from the field solver tool (my conclusion was yes but still it must be verified)? If not, how can something like this happen?

Many thanks in advance.

Best regards,

Can

Hi,

This question is related to the constraint measurement criteria used by the Liberate inside view. I am trying to characterize a specific D flip-flop for low voltage operation (0.6V) using Cadence Liberate (V16). 

When the "define_arcs" are not explicitly specified in the settings for the circuit (but the input/outputs are indeed correct in define_cell), the inside view seems to probe an internal node (i.e. master latch output)  for constraint measurements instead of the Q output of the flip flop. So to force the tool to probe Q output I added following coder in constraint arcs :

# constraint arcs from CK => D
define_arc
-type hold
-vector {RRx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type hold
-vector {RFx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type setup
-vector {RRx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type setup
-vector {RFx}
-related_pin CP
-pin D
-probe Q
DFFXXX

with -probe Q liberate identifies Q as the output, but uses Glitch-Peak criteria instead of delay degradation method. So what could be the exact reason for this unintended behavior ? In my external (spectre) spice simulation, the Flip-Flop works well and it does not show any issues in the output delay degradation when the input sweeps.

Thanks

Anuradha

Cadence Liberate Trio Characterization Suite, ARM-based Graviton Processors, and Amazon Web Services (AWS) Cloud have joined forces to cater to the High-Performance Computing, Machine Learning/Artificial Intelligence, and Big Data Analytics sectors. (read more)

Several tools can generate power reports based on libraries & stimulus. The issue is what's NEXT?

• Is there any scope to improve power consumption of my design?
• What is the best-case power?
• Pin-point hot spots in my design?
• How to recover wasted power?

And here is the solution in form of Joules RTL Power Exploration. Joules’ framework for power exploration and power implementation/recovery is stimulus based, where analysis is done by Joules and is explored/implemented by user.

Power Exploration capabilities include:

• Efficiency metrics
• Pin point RTL location
• Cross probe to stim
• Centralize all power data

 Do you want to explore more? What is the flow? What commands can be used?

There is a ONE-STOP solution to all these queries in the form of videos on Joules Power Exploration features on https://support.cadence.com (Cadence login required).

Video Links:

How to Analyze Ideal Power Using Joules RTL Power Solution GUI? (Video)

What is Ideal Power Analysis Flow in Joules RTL Power Solution? (Video)

How to Apply Observability Don’t Care (ODC) Technique in Joules? (Video)

How to Debug Wasted Power Using Ideal Power Analyzer Window in Joules GUI? (Video)

Related Resources

Enhance the Joules experience with videos: Joules RTL Power Solution: Video Library

For any questions, general feedback, or future blog topic suggestions, please leave a comment. 

Key Findings: Advantest, in mixed-signal SoC design, sees 50X speedup, 25 day test reduced to 12 hours, dramatic test coverage increase.

Trolling through the CDNLive archives, I discovered another gem. At the May 2013 CDNLive in Munich, Thomas Henkel and Henriette Ossoinig of Advantest presented a paper titled “Timing-accurate emulation of a mixed-signal SoC using Palladium XP”. Advantest makes advanced electronics test equipment. Among the semiconductor designs they create for these products is a test processor chip with over 100 million logic transistors, but also with lots of analog functions.They set out to find a way to speed up their full-chip simulations to a point where they could run the system software. To do that, they needed about a 50X speed-up. Well, they did it!

Figure 1: Advantest SoC Test Products

To skip the commentary, read Advantest's paper here. 

Problem Statement

Software is becoming a bigger part of just about every hardware product in every market today, and that includes the semiconductor test market. To achieve high product quality in the shortest amount of time, the hardware and software components need to be verified together as early in the design cycle as possible. However, the throughput of a typical software RTL simulation is not sufficient to run significant amounts of software on a design with hundreds of millions of transistors.  

Executing software on RTL models of the hardware means long runs  (“deep cycles”) that are a great fit for an emulator, but the mixed-signal content posed a new type of challenge for the Advantest team.  Emulators are designed to run digital logic. Analog is really outside of the expected use model. The Advantest team examined the pros and cons of various co-simulation and acceleration flows intended for mixed signal and did not feel that they could possibly get the performance they needed to have practical runtimes with software testbenches. They became determined to find a way to apply their Palladium XP platform to the problem.

Armed with the knowledge of the essential relationship between the analog operations and the logic and software operations, the team was able to craft models of the analog blocks using reduction techniques that accurately depicted the essence of the analog function required for hardware-software verification without the expense of a continuous time simulation engine.

The requirements boiled down to the following:

• Generation of digital signals with highly accurate and flexible timing

• Complete chip needs to run on Palladium XP platform

• Create high-resolution timing (100fs) with reasonable emulation performance, i.e. at least 50X faster than simulation on the fastest workstations

Solution Idea

The solution approach chosen was to simplify the functional model of the analog elements of the design down to generation of digital signal edges with high timing accuracy. The solution employed a fixed-frequency central clock that was used as a reference.Timing-critical analog signals used to produce accurately placed digital outputs were encoded into multi-bit representations that modeled the transition and timing behavior. A cell library was created that took the encoded signals and converted them to desired “regular signals”. 

Automation was added to the process by changing the netlisting to widen the analog signals according to user-specified schematic annotations. All of this was done in a fashion that is compatible with debugging in Cadence’s Simvision tool.  Details on all of these facets to follow.

The Timing Description Unit (TDU) Format

The innovative thinking that enabled the use of Palladium XP was the idea of combining a reference clock and quantized signal encoding to create offsets from the reference. The implementation of these ideas was done in a general manner so that different bit widths could easily be used to control the quantization accuracy.

Figure 2: Quantization method using signal encoding

Timed Cell Modeling

You might be thinking – timing and emulation, together..!?  Yes, and here’s a method to do it….

The engineering work in realizing the TDU idea involved the creation of a library of cells that could be used to compose the functions that convert the encoded signal into the “real signals” (timing-accurate digital output signals). Beyond some basic logic cells (e.g., INV, AND, OR, MUX, DFF, TFF, LATCH), some special cells such as window-latch, phase-detect, vernier-delay-line, and clock-generator were created. The converter functions were all composed from these basic cells. This approach ensured an easy path from design into emulation.

The solution was made parameterizable to handle varying needs for accuracy.  Single bit inputs need to be translated into transitions at offset zero or a high or low coding depending on the previous state.  Single bit outputs deliver the final state of the high-resolution output either at time zero, the next falling, or the next rising edge of the grid clock, selectable by parameter. Output transitions can optionally be filtered to conform to a configurable minimum pulse width.

Timed Cell Structure

There are four critical elements to the design of the conversion function blocks (time cells):

                Input conditioning – convert to zero-offset, optional glitch preservation, and multi-cycle path

                Transition sorting – sort transitions according to timing offset and specified precedence

                Function – for each input transition, create appropriate output transition

                Output filtering – Capability to optionally remove multiple transitions, zero-width, pulses, etc.

Timed Cell Caveat

All of the cells are combinational and deliver a result in the same cycle of an input transition. This holds for storage elements as well. For example a DFF will have a feedback to hold its state. Because feedback creates combinational loops, the loops need a designation to be broken (using a brk input conditioning function in this case – more on this later). This creates an additional requirement for flip-flop clock signals to be restricted to two edges per reference clock cycle.

Note that without minimum width filtering, the number of output transitions of logic gates is the sum of all input transitions (potentially lots of switching activity). Also note that the delay cell has the effect of doubling the number of output transitions per input transition.

Figure 3: Edge doubling will increase switching during execution

SimVision Debug Support

The debug process was set up to revolve around VCD file processing and directed and viewed within the SimVision debug tool. In order to understand what is going on from a functional standpoint, the raw simulation output processes the encoded signals so that they appear as high-precision timing signals in the waveform viewer. The flow is shown in the figure below.

Figure 4: Waveform post-processing flow

The result is the flow is a functional debug view that includes association across representations of the design and testbench, including those high-precision timing signals.

Figure 5: Simvision debug window setup

Overview of the Design Under Verification (DUV)

Verification has to prove that analog design works correctly together with the digital part. The critical elements to verify include:

• Programmable delay lines move data edges with sub-ps resolution

• PLL generates clocks with wide range of programmable frequency

• High-speed data stream at output of analog is correct

These goals can be achieved only if parts of the analog design are represented with fine resolution timing.

Figure 6: Mixed-signal design partitioning for verification

How to Get to a Verilog Model of the Analog Design

There was an existing Verilog cell library with basic building blocks that included:

- Gates, flip-flops, muxes, latches

- Behavioral models of programmable delay elements, PLL, loop filter, phase detector

With a traditional simulation approach, a cell-based netlist of the analog schematic is created. This netlist is integrated with the Verilog description of the digital design and can be simulated with a normal workstation. To use Palladium simulation, the (non-synthesizable) portions of the analog design that require fine resolution timing have to be replaced by digital timing representation. This modeling task is completed by using a combination of the existing Verilog cell library and the newly developed timed cells.

Loop Breaking

One of the chief characteristics of the timed cells is that they contain only combinational cells that propagate logic from inputs to outputs. Any feedback from a cell’s transitive fanout back to an input creates a combinational loop that must be broken to reach a steady state. Although the Palladium XP loop breaking algorithm works correctly, the timed cells provided a unique challenge that led to unpredictable results.  Thus, a process was developed to ensure predictable loop breaking behavior. The user input to the process was to provide a property at the loop origin that the netlister recognized and translated to the appropriate loop breaking directives.

Augmented Netlisting

Ease of use and flow automation were two primary considerations in creating a solution that could be deployed more broadly. That made creating a one-step netlisting process a high-value item. The signal point annotation and automatic hierarchy expansion of the “digital timing” parameter helped achieve that goal. The netlister was enriched to identify the key schematic annotations at any point in the hierarchy, including bit and bus signals.

Consistency checking and annotation reporting created a log useful in debugging and evolving the solution.

Wrapper Cell Modeling and Verification

The netlister generates a list of schematic instances at the designated “netlister stop level” for each instance the requires a Verilog model with fine resolution timing. For the design in this paper there were 160 such instances.

The library of timed cells was created; these cells were actually “wrapper” cells comprised of the primitives for timed cell modeling described above. A new verification flow was created that used the behavior of the primitive cells as a reference for the expected behavior of the composed cells. The testing of the composed cells included had the timing width parameter set to 1 to enable direct comparison to the primitive cells. The Cadence Incisive Enterprise Simullator tool was successfully employed to perform assertion-based verification of the composed cells versus the existing primitive cells.

Mapping and Long Paths

Initial experiments showed that inclusion of the fine resolution timed cells into the digital emulation environment would about double the required capacity per run. As previously pointed out, the timed cells having only combinational forward paths creates a loop issue. This fact also had the result of creating some such paths that were more than 5,000 steps of logic. A timed cell optimization process helped to solve this problem. The basic idea was to break the path up by adding flip-flops in strategic locations to reduce combinational path length. The reason that this is important is that the maximum achievable emulation speed is related to combinational path length.

Results

Once the flow was in place, and some realistic test cases were run through it, some further performance tuning opportunities were discovered to additionally reduce runtimes (e.g., Palladium XP tbrun mode was used to gain speed). The reference used for overall speed gains on this solution was versus a purely software-based solution on the highest performance workstation available.

The findings of the performance comparison were startlingly good:

• On Palladium XP, the simulation speed is 50X faster than on Advantest’s fastest workstation

• Software simulation running 25 days can now be run in 12 hours -> realistic runtime enables long-running tests that were not feasible before

• Now have 500 tests that execute once in more than 48 hours

• They can be run much more frequently using randomization and this will increase test coverage dramatically

Steve Carlson

Key Findings: Many more design teams will be reaching the mixed-signal methodology tipping point in 2015. That means you need to have a (verification) plan, and measure and execute against it.

As 2014 draws to a close, it is time to look ahead to the coming years and make a plan. While the macro view of the chip design world shows that is has been a mixed-signal world for a long time, it is has been primarily the digital teams that have rapidly evolved design and verification practices over the past decade. Well, I claim that is about to change. 2015 will be a watershed year for many more design teams because of the following factors:

• 85% of designs are mixed signal, and it is going to stay that way (there is no turning back)
• Advanced node drives new techniques, but they will be applied on all nodes
• Equilibrium of mixed-signal designs being challenged, complexity raises risk level
• Tipping point signs are evident and pervasive, things are going to change
• The convergence of “big A” and “big D” demands true mixed-signal practices

Reason 1: Mixed-signal is dominant

To begin the examination of what is going to change and why, let’s start with what is not changing. IBS reports that mixed signal accounts for over 85% of chip design starts in 2014, and that percentage will rise, and hold steady at 85% in the coming years. It is a mixed-signal world and there is no turning back!

Figure 1. IBS: Mixed-signal design starts as percent of total

The foundational nature of mixed-signal designs in the semiconductor industry is well established. The reason it is exciting is that a stable foundation provides a platform for driving change. (It’s hard to drive on crumbling infrastructure.  If you’re from California, you know what I mean, between the potholes on the highways and the earthquakes and everything.)

Reason 2: Innovation in many directions, mostly mixed-signal applications

While the challenges being felt at the advanced nodes, such as double patterning and adoption of FinFET devices, have slowed some from following onto to nodes past 28nm, innovation has just turned in different directions. Applications for Internet of Things, automotive, and medical all have strong mixed-signal elements in their semiconductor content value proposition. What is critical to recognize is that many of the design techniques that were initially driven by advanced-node programs have merit across the spectrum of active semiconductor process technologies. For example, digitally controlled, calibrated, and compensated analog IP, along with power-reducing mutli-supply domains, power shut-off, and state retention are being applied in many programs on “legacy” nodes.

Another graph from IBS shows that the design starts at 45nm and below will continue to grow at a healthy pace.  The data also shows that nodes from 65nm and larger will continue to comprise a strong majority of the overall starts. 

Figure 2.  IBS: Design starts per process node

TSMC made a comprehensive announcement in September related to “wearables” and the Internet of Things. From their press release:

TSMC’s ultra-low power process lineup expands from the existing 0.18-micron extremely low leakage (0.18eLL) and 90-nanometer ultra low leakage (90uLL) nodes, and 16-nanometer FinFET technology, to new offerings of 55-nanometer ultra-low power (55ULP), 40ULP and 28ULP, which support processing speeds of up to 1.2GHz. The wide spectrum of ultra-low power processes from 0.18-micron to 16-nanometer FinFET is ideally suited for a variety of smart and power-efficient applications in the IoT and wearable device markets. Radio frequency and embedded Flash memory capabilities are also available in 0.18um to 40nm ultra-low power technologies, enabling system level integration for smaller form factors as well as facilitating wireless connections among IoT products.

Compared with their previous low-power generations, TSMC’s ultra-low power processes can further reduce operating voltages by 20% to 30% to lower both active power and standby power consumption and enable significant increases in battery life—by 2X to 10X—when much smaller batteries are demanded in IoT/wearable applications.

The focus on power is quite evident and this means that all of the power management and reduction techniques used in advanced node designs will be coming to legacy nodes soon.

Integration and miniaturization are being pursued from the system-level in, as well as from the process side. Techniques for power reduction and system energy efficiency are central to innovations under way.  For mixed-signal program teams, this means there is an added dimension of complexity in the verification task. If this dimension is not methodologically addressed, the level of risk adds a new dimension as well.

Reason 3: Trends are pushing the limits of established design practices

Risk is the bane of every engineer, but without risk there is no progress. And, sometimes the amount of risk is not something that can be controlled. Figure 3 shows some of the forces at work that cause design teams to undertake more risk than they would ideally like. With price and form factor as primary value elements in many growing markets, integration of analog front-end (AFE) with digital processing is becoming commonplace.  

Figure 3.  Trends pushing mixed-signal out of equilibrium

The move to the sweet spot of manufacturing at 28nm enables more integration, while providing excellent power and performance parameters with the best cost per transistor. Variation becomes great and harder to control. For analog design, this means more digital assistance for calibration and compensation. For greatest flexibility and resiliency, many will opt for embedding a microcontroller to perform the analog control functions in software. Finally, the first wave of leaders have already crossed the methodology bridge into true mixed-signal design and verification; those who do not follow are destined to fall farther behind.

Reason 4: The tipping point accelerants are catching fire

The factors cited in Reason 3 all have a technical grounding that serves to create pain in the chip-development process. The more factors that are present, the harder it is to ignore the pain and get the treatment relief  afforded by adopting known best practices for truly mixed-signal design (versus divide and conquer along analog and digital lines design).

In the past design performance was measured in MHz with simple static timing and power analysis. Design flows were conveniently partitioned, literally and figuratively, along analog and digital boundaries. Today, however, there are gigahertz digital signals that interact at the package and board level in analog-like ways. New, dynamic power analysis methods enabled by advanced library characterization must be melded into new design flows. These flows comprehend the growing amount of feedback between analog and digital functions that are becoming so interlocked as to be inseparable. This interlock necessitates design flows that include metrics-driven and software-driven testbenches, cross fabric analysis, electrically aware design, and database interoperability across analog and digital design environments.

Figure 4.  Tipping point indicators

Energy efficiency is a universal driver at this point.  Be it cost of ownership in the data center or battery life in a cell phone or wearable device, using less power creates more value in end products. However, layering multiple energy management and optimization techniques on top of complex mixed-signal designs adds yet more complexity demanding adoption of “modern” mixed-signal design practices.

Reason 5: Convergence of analog and digital design

Divide and conquer is always a powerful tool for complexity management.  However, as the number of interactions across the divide increase, the sub-optimality of those frontiers becomes more evident. Convergence is the name of the game.  Just as analog and digital elements of chips are converging, so will the industry practices associated with dealing with the converged world.

Figure 5. Convergence drivers

Truly mixed-signal design is a discipline that unites the analog and digital domains. That means that there is a common/shared data set (versus forcing a single cockpit or user model on everyone). 

In verification the modern saying is “start with the end in mind”. That means creating a formal approach to the plan of what will be test, how it will be tested, and metrics for success of the tests. Organizing the mechanics of testbench development using the Unified Verification Methodology (UVM) has proven benefits. The mixed-signal elements of SoC verification are not exempted from those benefits.

Competition is growing more fierce in the world for semiconductor design teams. Not being equipped with the best-known practices creates a competitive deficit that is hard to overcome with just hard work. As the landscape of IC content drives to a more energy-efficient mixed-signal nature, the mounting risk posed by old methodologies may cause causalities in the coming year. Better to move forward with haste and create a position of strength from which differentiation and excellence in execution can be forged.

Summary

2015 is going to be a banner year for mixed-signal design and verification methodologies. Those that have forged ahead are in a position of execution advantage. Those that have not will be scrambling to catch up, but with the benefits of following a path that has been proven by many market leaders.

Key Findings:  There are a host of issues that arise in mixed-signal verification.  As discussed in earlier blogs, the industry trends indicate that teams need to prepare themselves for a more mixed world.  The good news is that these top five pitfalls are all avoidable.

It’s always interesting to study the human condition.  Watching the world through the lens of mixed-signal verification brings an interesting microcosm into focus.  The top 5 items that I regularly see vexing teams are:

1. When there’s a bug, whose problem is it?
2. Verification team is the lightning rod
3. Three (conflicting) points of view
4. Wait, there’s more… software
5. There’s a whole new language

Reason 1: When there’s a bug, whose problem is it?

It actually turns out to be a good thing when a bug is found during the design process.  Much, much better than when the silicon arrives back from the foundry of course. Whether by sheer luck, or a structured approach to verification, sometimes a bug gets discovered. The trouble in mixed-signal design occurs when that bug is near the boundary of an analog and a digital domain.

Figure 1.   Whose bug is it?

Typically designers are a diligent sort and make sure that their block works as desired. However, when things go wrong during integration, it is usually also project crunch time. So, it has to be the other guy’s bug, right?

A step in the right direction is to have a third party, a mixed-signal verification expert, apply rigorous methods to the mixed-signal verification task.  But, that leads to number 2 on my list.

Reason 2: Verification team is the lightning rod

Having a dedicated verification team with mixed-signal expertise is a great start, but what can typically happen is that team is hampered by the lack of availability of a fast executing model of the analog behavior (best practice today being a SystemVerilog real number model – SV_RNM). That model is critical because it enables orders of magnitude more tests to be run against the design in the same timeframe. 

Without that model, there will be a testing deficit. So, when the bugs come in, it is easy for everyone to point their finger at the verification team.

Figure 2.  It’s the verification team’s fault

Yes, the model creates a new validation task – it’s validation – but the speed-up enabled by the model more than compensates in terms of functional coverage and schedule.

The postscript on this finger-pointing is the institutionalization of SV-RNM. And, of course, the verification team gets its turn.

Figure 3.  Verification team’s revenge

Reason 3: Three (conflicting) points of view

The third common issue arises when the finger-pointing settles down. There is still a delineation of responsibility that is often not easy to achieve when designs of a truly mixed-signal nature are being undertaken.  

Figure 4.  Points of view and roles

Figure 4 outlines some of the delegated responsibility, but notice that everyone is still potentially on the hook to create a model. It is questions of purpose, expertise, bandwidth, and convention that go into the decision about who will “own” each model. It is not uncommon for the modeling task to be a collaborative effort where the expertise on analog behavior comes from the analog team, while the verification team ensures that the model is constructed in such a manner that it will fit seamlessly into the overall chip verification. Less commonly, the digital design team does the modeling simply to enable the verification of their own work.

Reason 4: Wait, there’s more… software

As if verifying the function of a chip was not hard enough, there is a clear trend towards product offerings that include software along with the chip. In the mixed-signal design realm, many times this software has among its functions things like calibration and compensation that provide a flexible way of delivering guards against parameter drift. When the combination of the chip and the software are the product, they need to be verified together. This puts an enormous premium on fast executing SV-RNM.

Figure 5.   There’s software analog and digital

While the added dimension of software to the verification task creates new heights of complexity, it also serves as a very strong driver to get everyone aligned and motivated to adopt best known practices for mixed-signal verification.  This is an opportunity to show superior ability!

Figure 6.  Change in perspective, with the right methodology

Reason 5: There’s a whole new language

Communication is of vital importance in a multi-faceted, multi-team program.  Time zones, cultures, and personalities aside, mixed-signal verification needs to be a collaborative effort.  Terminology can be a big stumbling block in getting to a common understanding. If we take a look at the key areas where significant improvement can usually be made, we can start to see the breadth of knowledge that is required to “get” the entirety of the picture:

• Structure – Verification planning and management
• Methodology – UVM (Unified Verification Methodology – Accellera Standard)
• Measure – MDV (Metrics-driven verification)
• Multi-engine – Software, emulation, FPGA proto, formal, static, VIP
• Modeling – SystemVerilog (discrete time) down to SPICE (continuous time)
• Languages – SystemVerilog, Verilog, Verilog-AMS, VHDL, SPICE, PSL, CPF, UPF

Each of these areas has its own jumble of terminology and acronyms. It never hurts to create a team glossary to start with. Heck, I often get my LDO, IFV, and UDT all mixed up myself.

Summary

Yes, there are a lot of things that make it hard for the humans involved in the process of mixed-signal design and verification, but there is a lot that can be improved once the pain is felt (no pain, no gain is akin to no bugs, no verification methodology change). If we take a look at the key areas from the previous section, we can put a different lens on them and describe the value that they bring:

• Structure – Uniformly organized, auditable, predictable, transparency
• Methodology – Reusable, productive, portable, industry standard
• Measure – Quantified progress, risk/quality management, precise goals
• Multi-engine – Faster execution, improved schedule, enables new quality level
• Modeling – Enabler, flexible, adaptable for diverse applications/design styles
• Languages – Flexible, complete, robust, standard, scalability to best practices

With all of this value firmly in hand, we can turn our thoughts to happier words:

…  stay tuned for more!

 Steve Carlson

The complexity and size of mixed-signal designs in wireless, power management, automotive, and other fast growing applications requires continued advancements in a mixed-signal verification methodology. An SoC, in these fast growing applications, incorporates a large number of analog and mixed-signal (AMS) blocks/IPs, some acquired from IP providers, some designed, often concurrently. AMS IP must be verified independently, but this is not sufficient to ensure an SoC will function properly and all scenarios of interaction among many different AMS IP blocks at full chip / SoC level must be verified thoroughly. To reduce an overall verification cycle, AMS IP and SoC verification teams must work in parallel from early stages of the design. Easier said than done! We will outline a methodology than can help.

AMS designers verify their IP meets required specifications by running a testbench they develop for standalone / out of-context verification. Typically, an AMS IP as analog-centric, hierarchal design in schematic, composed of blocks represented by transistor, HDL and behavioral description verified in Virtuoso® Analog Design Environment (ADE) using Spectre AMS Designer simulation. An SoC verification team typically uses UVM SystemVerilog testbech at full chip level where the AMS IP is represented with a simple digital or real number model running Xcelium /DMS simulation from the command line.

Ideally, AMS designers should also verify AMS IP function properly in the context of full-chip integration, but reproducing an often complex UVM SystemVerilog testbench and bringing over top-level design description to an analog-centric environment is not a simple task.

Last year, Cadence partnered with Infineon on a project with a goal to automate the reuse of a top-level testbench in AMS verification. The automation enabled AMS verification engineers to automatically configure setup for verification runs by assembling all necessary options and files from the AMS IP Virtuoso GUI and digital SoC top-level command line configurations. The benefits of this method were:

• AMS verification engineers did not need to re-create complex stimuli representing interaction of their IP at the top level
• Top-level verification stays external to the AMS IP verification environment and continues to be managed by the SoC verification team, but can be reused by the AMS IP team without manual overhead
• AMS IP is verified in-context and any inconsistencies are detected earlier in the verification process
• Improved productivity and overall verification time

For more details, please see Infineon’s CDNLlive presentation.

Typically, analog designers verify their AMS IP in schematic driven, interactive environment, while SoC designers use a UVM SystemVerilog testbench ran from a command line. In our last MS blog, we talked about automation for reusing SystemVerilog testbench by analog designers in order to verify AMS IP in exactly same context as in its SoC integration, hence reducing surprises and unnecessary iterations.

But, what about other direction: selecting proper AMS IP views for SoC Verification? Manually export netlist from Virtuoso and then manually assemble together all of the files for use with in command line driven flow? Often, there are multiple views for the same instance (RNM, analog behavioral model, transistor netlist). Which one to pick? Who is supposed to update configuration files? We often work concurrently and update the AMS IP views frequently. Obviously, manually selecting correct and most up-to-date AMS IP views for SoC Verification is tedious and error prone. Thanks to Cadence Innovation, there is a better way!

Cadence has developed a Command-Line IP Selector (CLIPS) product as part of the Virtuoso^® environment, which:

• Bridges the gap between MS SoC command-line setup and the Virtuoso-based analog mixed-signal configuration
• Allows seamless importing of AMS IP from the Virtuoso environment into an existing digital verification setup
• Provides a GUI-based and command-line use model, flexible to fit into an existing design flow methodologyCLIPS reads MS SoC command (irun) files, identifies required AMS IP modules, uses Virtuoso ADE setup files to properly netlist required modules, and pulls the AMS IP out of the Virtuoso environment. All necessary files are properly extracted/prepared and package as required for the MS SoC command line verification run. CLIPS setup can be saved and rerun as a batch process to ensure the latest IP from the hierarchy is being simulated.

For more details, please see CLIPS Rapid Adoption Kit at Cadence Online Support page

Cadence_SPB_17.4-2019 + Matlab R2019a

请参考本文档中的步骤进行操作

1，打开BJT_AMP.opj

2，设置Matlab路径

3，打开BJT_AMP_SLPS.slx

4，打开后，设置PSpiceBlock，出现或CEFSimpleUI.exe停止工作

5，添加模块

6，相同

7，打开pspsim.slx

8，相同

9，打开C： Cadence Cadence_SPB_17.4-2019 tools bin

orCEFSimpleUI.exe和orCEFSimple.exe

10，相同

我想问一下如何解决，非常感谢！

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રિલાયન્સ ઇન્ડસ્ટ્રીઝ ગુજરાત અને મહારાષ્ટ્ર મુખ્યમંત્રી રાહતનિધી ફંડમાં 5-5 કરોડ રૂપિયા આપશે. આગામી 10 દિવસ માટે 5 લાખ લોકોના ભોજનની પણ વ્યવસ્થા કરશે.

પ્રોસસે વર્ષ 2005માં પાંચ અબજ ડૉલર (આશરે 37,900 કરોડ રૂપિયા)નું ભારતીય ટેક્નોલોજી કંપનીઓમાં રોકાણ કર્યું હતું.

ચાલો જરૂરિયાતના આવા સમયે એકબીજાને મદદ કરીએ, અને આ મદદ કરવા માટે અમારી પાસે એક સરળ રીત છે.

કંપનીનો દાવો, કારના કોઈપણ ખૂણામાં કોરોના છુપાઈ નહીં શકે, કાર એક્સપર્ટ્સનો વિરોધી મત

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The UltraHVCam ActiveX Control 'UltraHVCamX.ocx' suffers from a stack buffer overflow vulnerability when parsing large amount of bytes to several functions in UltraHVCamLib, resulting in memory corruption overwriting several registers including the SEH. An attacker can gain access to the system of the affected node and execute arbitrary code. Versions affected include PT Type ICS2330, Cube Type ICS2030, and Dome Type ICS7522.