1 Dominican Peso = 2.657 Icelandic Krona

1 Dominican Peso = 0.0637 Israeli New Sheqel

Thomas Zunie, a junior from Zuni, New Mexico qualified today for the 2012 NAIA Outdoor Track and Field National Championships to be held the last week of May on the campus of Indiana Wesleyan University.   

Haskell Track and Field is finally back …. Approximately four years ago the Haskell Track and Field Program was put on hold.  A couple of years later the distance portion of Track and Field returned.  In 2011-2012, Haskell opened up the Indoor and Outdoor Seasons to include the addition of sprints, mid-distance, and throws.  Yesterday at the Emporia State Twilight Meet the Indians added long jump, triple jump, and a relay team to the track and field mix. 

NCAA Division II, Emporia State University served as the 2^ndmeet of the Outdoor Track and Field season for the Indians.  Highlights from the meet include:

Ian Stand, a sophomore from Bay Point, California returned to the discus ring and completed a toss of 36.52 meters, an improvement from his first meet.  Stand, also earned a seventh place finish in the shot put with a distance of 10.76 meters. 

Two Haskell men finish fourth, while one Indian woman places sixth

Christina Belone, Talisa Budder and Matt Woody compete in the 85^th edition of the annual event

Thomas Zunie, a junior from Zuni, NM takes first in the Men's 5000 meter run in a time of 17:21.41.  Zunie's finish in the 5000 garnered him a First Team All-Conference.  Zunie also earned a third place in the 1500 meter run with a time of 4:33.77.   

Billy Mills (Track & Field) 1953-57
Mills grew up on the Pine Ridge Indian Reservation for the Oglala Lakota Tribe in Pine Ridge, S.D. Growing up Mills participated in boxing and running but did not hone his skills on the track until he came to Lawrence, Kan., and Haskell Institute. Following his time at Haskell, the South Dakota native went onto star at the University of Kansas, where he was a three-time All-American and a Big 8 champion. Aside from his collegiate prowess, Mills did exceptionally well on the international stage, winning Gold in the 10,000 meters during the 1964 Olympics in Tokyo, where he became only the second Native American to capture Gold. The heralded Olympian continued to run after his Tokyo experience, breaking U.S. records in two events (10,000 meters and three mile run), as well as a world record in the six mile. Mills currently lives in Sacramento, Calif., where he is a spokesperson for ‘Running Strong for American Indian Youth' organization. He is also a member of numerous Hall of Fames throughout the nation, including the U.S. Olympic Hall of Fame as well as the National Distance Running Hall of Fame.

Last week the weather disrupted the Indians as they opened the Outdoor Season at Pittsburg State University.  Thunderstorms and lightning prevented numerous races and events from running on schedule.  For many, the meet yesterday was their opportunity to finally compete.

Haskell will play host to the 2014 Midlands Collegiate Athletic Conference Outdoor Track and Field Championships on April 25th and 26th. 

Baldwin City, Kansas - The Haskell Indian Nations University men's track and field teams competed at the Baker Relays on Saturday.

Ottawa, Kansas - The Haskell Indian Nations University Men's track and field teams competed at the Ottawa Braves Invitational on Saturday.

Liberty, MO - The Haskell Indian Nations University Men's track and field teams competed at the Darrel Gourley Open on Saturday.

The Men's Track & Field team finished their season at Baker Invite on April 29th. Here are some of the athlete's best finishes throughout the season. The Seniors behind the Track & Field program are Isaac Johnson and Stephen Esmond (SR). 

1 Papua New Guinean Kina = 2.9115 Venezuelan Bolivar Fuerte

1 Papua New Guinean Kina = 5.0047 Seychellois Rupee

1 Papua New Guinean Kina = 42.6308 Icelandic Krona

1 Papua New Guinean Kina = 1.0222 Israeli New Sheqel

1 Brunei Dollar = 7.067 Venezuelan Bolivar Fuerte

1 Brunei Dollar = 12.1479 Seychellois Rupee

1 Brunei Dollar = 103.4771 Icelandic Krona

1 Brunei Dollar = 2.4813 Israeli New Sheqel

Final Score: 71-53

Design and verification standards are critical if we want to get a new generation of Internet of Things (IoT) devices into the market, according to panelists at an Accellera Systems Initiative breakfast at the Design Automation Conference (DAC 2015) June 9. However, IoT devices for different vertical markets pose very different challenges and requirements, making the standards picture extremely complicated.

The panel was titled “Design and Verification Standards in the Era of IoT.” It was moderated by industry editor John Blyler, CEO of JB Systems Media and Technology. Panelists were as follows, shown left to right in the photo below:

• Lu Dai, director of engineering, Qualcomm
• Wael William Diab, senior director for strategy marketing, industry development and standardization, Huawei
• Chris Rowen, CTO, IP Group, Cadence Design Systems, Inc.

In opening remarks, Blyler recalled a conversation from the recent IEEE International Microwave Symposium in which a panelist pointed to the networking and application layers as the key problem areas for RF and wireless standardization. Similarly, in the IoT space, we need to look “higher up” at the systems level and consider both software and hardware development, Blyler said.

Rowen helped set some context for the discussion by noting three important points about IoT:

• IoT is not a product segment. Vertical product segments such as automotive, medical devices, and home automation all have very different characteristics.
• IoT “devices” are components within a hierarchy of systems that includes sensors, applications, user interface, gateway application (such as cell phone), and finally the cloud, where all data is aggregated.
• A bifurcation is taking place in design. We are going from extreme scale SoCs to “extreme fit” SoCs that are specialized, low energy, and very low cost.

Here are some of the questions and answers that were addressed during the panel discussion.

Q: The claim was recently made that given the level of interaction between sensors and gateways, 50X more verification nodes would have to be checked for IoT. What standards need to be enhanced or changed to accomplish that?

Rowen: That’s a huge number of design dimensions, and the way you attack a problem of that scale is by modularization. You define areas that are protected and encapsulated by standards, and you prove that individual elements will be compliant with that interface. We will see that many interesting problems will be in the software layers.

Q: Why is standardization so important for IoT?

Dai: A company that is trying to make a lot of chips has to deal with a variety of standards. If you have to deal with hundreds of standards, it’s a big bottleneck for bringing your products to market. If you have good standardization within the development process of the IC, that helps time to market.

When I first joined Qualcomm a few years ago, there was no internal verification methodology. When we had a new hire, it took months to ramp up on our internal methodology to become effective. Then came UVM [Universal Verification Methodology], and as UVM became standard, we reduced our ramp-up time tremendously. We’ve seen good engineers ramp up within days.

Diab: When we start to look at standards, we have to do a better job of understanding how they’re all going to play with each other. I don’t think one set of standards can solve the IoT problem. Some standards can grow vertically in markets like industrial, and other standards are getting more horizontal. Security is very important and is probably one thing that goes horizontally.

Requirements for verticals may be different, but processing capability, latency, bandwidth, and messaging capability are common [horizontal] concerns. I think a lot of standards organizations this year will work on horizontal slices [of IoT].

Q: IoT interoperability is important. Any suggestions for getting that done and moving forward?

Rowen: The interoperability problem is that many of these [IoT] devices are wireless. Wireless is interesting because it is really hard – it’s not like a USB plug. Wireless lacks the infrastructure that exists today around wired standards. If we do things in a heavily wireless way, there will be major barriers to overcome.

Dai: There are different standards for 4G LTE technology for different [geographical] markets. We have to make a chip that can work for 20 or 30 wireless technologies, and the cost for that is tremendous. The U.S., Europe, and China all have different tweaks. A good standard that works across the globe would reduce the cost a lot.

Q: If we’re talking about the need to define requirements, a good example to look at is power. Certainly you have UPF [Unified Power Format] for the chip, board, and module.

Rowen: There is certainly a big role for standards about power management. But there is also a domain in which we’re woefully under-equipped, and that is the ability to accurately model the different power usage scenarios at the applications level. Too often power devolves into something that runs over thousands of cycles to confirm that you can switch between power management levels successfully. That’s important, but it tells you very little about how much power your system is going to dissipate.

Dai: There are products that claim to be UPF compliant, but my biggest problem with my most recent chip was still with UPF. These tools are not necessarily 100% UPF compliant.

One other concern I have is that I cannot get one simulator to pass my Verilog code and then go to another that will pass. Even though we have a lot of tools, there is no certification process for a language standard.

Q: When we create a standard, does there need to be a companion compliance test?

Rowen: I think compliance is important. Compliance is being able to prove that you followed what you said you would follow. It also plays into functional safety requirements, where you need to prove you adhered to the flow.

Dai: When we [Qualcomm] sell our 4G chips, we have to go through a lot of certifications. It’s often a differentiating factor.

Q: For IoT you need power management and verification that includes analog. Comments?

Rowen: Small, cheap sensor nodes tend to be very analog-rich, lower scale in terms of digital content, and have lots of software. Part of understanding what’s different about standardization is built on understanding what’s different about the design process, and what does it mean to have a software-rich and analog-rich world.

Dai: Analog is important in this era of IoT. Analog needs to come into the standards community.

Richard Goering

Cadence Blog Posts About DAC 2015

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DAC 2015: Can We Build a Virtual Silicon Valley?

DAC 2015: Cadence Vision-Design Presentation Wins Best Paper Honors

EDA investor and former executive Jim Hogan is optimistic about automotive electronics, but he has some concerns as well. At the recent Design Automation Conference (DAC 2015), he delivered a speech titled “The Looming Quality, Reliability, and Safety Crisis in Automotive Electronics...Why is it and what can we do to avoid it?"

Hogan gave the keynote speech for IP Talks!, a series of over 30 half-hour presentations located at the ChipEstimate.com booth. Presenters included ARM, Cadence, eSilicon, Kilopass, Sidense, SilabTech, Sonics, Synopsys, True Circuits, and TSMC. Held in an informal setting, the talks addressed the challenges faced by SoC design teams and showed how the latest developments in semiconductor IP can contribute to design success.

Jim Hogan delivers keynote speech at DAC 2015 IP Talks!

Hogan talked about several phases of automotive electronics. These include assisted driving to avoid collisions, controlled automation of isolated tasks such as parallel parking, and, finally, fully autonomous vehicles, which Hogan expects to see in 15 to 20 years. The top immediate priorities for automotive electronics designers, he said, will be government regulation, fuel economy, advanced safety, and infotainment.

More Code than a Boeing 777

According to Hogan, today’s automobiles use 50-100 microcontrollers per car, resulting in a worldwide automotive semiconductor market of around $40 billion. The global market for advanced automotive electronics is expected to reach $240 billion by 2020. Software is growing faster in the automotive market than it is in smartphones. Hogan quoted a Ford vice president who observed that there are more lines of code in a Ford Fusion car than a Boeing 777 airplane.

One unique challenge for automotive electronics designers is long-term reliability. This is because a typical U.S. car stays on the road for 15 years, Hogan said. Americans are holding onto new vehicles for a record 71.4 months.

Another challenge is regulatory compliance. Aeronautics is highly regulated from manufacturing to air traffic control, and the same will probably be true of automated cars. Hogan speculated that the Department of Transportation will be the regulatory authority for autonomous cars. Today, automotive electronics providers must comply with the ISO26262 automotive functional safety specification.

So where do we go from here? “We’ve got to change our mindset,” Hogan said. “We’ve got to focus on safety and reliability and demand a different kind of engineering discipline.” You can watch Hogan’s entire presentation by clicking on the video icon below, or clicking here. You can also watch other IP Talks! videos from DAC 2015 here.

https://youtu.be/qL4kAEu-PNw

Richard Goering

Related Blog Posts

DAC 2015: See the Latest in Semiconductor IP at “IP Talks!”

Automotive Functional Safety Drives New Chapter in IC Verification

Hello, my name is Hsukang. I want to use Liberate to create a .lib file for the following circuit. This is a scan FF with two separate outputs.   The question is that no matter how I described its function, the synthesis tool said its a manformed scan FF.  Has anyone ever encountered anything like this？How should I describe the function correctly？I found that almost standard flip-flop cells are with only one output Q or have Qn at the same time. Does Liberate support scan flip-flop cells with two separate outputs ？

Thanks.

Hi,

There was tool available with INCISIV called imc to view the coverage reports.

The question is: How can we view the code coverage reports generated with XCELIUM? I think imc is not available with XCELIUM?

Thanks in advance.

Hi,

I recently encountered a probelm where scrolling with the mouse wheel and [i][o] button does not zoom in or out both in "Allegro orcad capture CIS 17.2.2016 " .

When I scroll the mouse wheel or [i][o] button, nothing is done.

The thing is that it worked fine until yesterday.

Anyone has an idea?

Thanks,

Dung.

For a netlist vs. netlist LEC flow we have to solve the following problem:

- in the RTL code we replicate a large array of N x M all-identical hard-macros, let call them MACRO_A

- MACRO_A is pre-assembled in Innovus and contains digital parts and analog parts (bottom-up hierarchical flow)

- at top-level (full-chip) we instantiate this array of all-identical macros

- in the top-level place-and-route flow we perform ecoChangeCell to remaster the top row of this array with MACRO_B

- MACRO_B is just a copy of the original MACRO_A cell containing same pins position, same internal digital functionality and also same digital layout, only slight differences in one analog block inside the macro

- MACRO_A and MACRO_B have the same .lib file generated with the do_extract_model command at the end of the Innovus flow, they only differ in the name of the macro

- when performing post-synthesis netlist vs post-place-and-route we load .lib files of both macros in Conformal LEC

- the LEC flow fails because Conformal LEC sees only MACRO_A instantiated in the post-synthesis netlist and both MACRO_A and MACRO_B in the post-palce-and-route netlist

Since both digital functionality and STD cells layout are the same between MACRO_A and MACRO_B we don't want to keep track of this difference already at RTL stage, we just want to perform this ECO change in place-and-route and force Conformal to assume equivalence between MACRO_A and MACRO_B .

Basically what I'm searching for is something similar to the add_instance_equivalences Conformal command but that works between Golden and Revised designs on cell primitives/black-boxes .

Is this flow supported ?

Thanks in advance

Luca

Happy New Year! Have you tried the new Transmission Line Library (rfTlineLib) yet? In case you missed it, rfTlineLib was introduced in IC 6.1.6 ISR1 plus MMSIM 12.1.1 -or- MMSIM13.1. You may wonder....Why should I use the new rfTlineLib ? Well...(read more)

Hi Folks, A question that I've often received from designers, "Is there a method to determine the amount of memory required before I submit a job? I use distributed processing and need to provide an estimate before submitting jobs." The answer...(read more)

I have a technology library (given by foundry) with leLsw layer section defined.
I do not want to touch it

I added few layers with an ITDB approach. Now I'm unable to see the added layers, as it is not present in the leLsw layer section of the main techlib.

I want the user of the new techlib to see all the layers by default.(I don't want the users to go to the properties of palette and switch the display option to techfile layers instead of leLsw)

Hello,

I am in a need of a skill program to find all instances of a specific cell (Including Mosaics), throughout the hierarchy. The program should print the instance's name, xy coordinates at the top level, and extract a label name that is dropped on top of it. In case there is no label on top of the found instance, the program should print "No Label Found" in the report text file. This program aims to map PADs cells within top level.

I am using the below Cadence's solution to find instances and it works well. The missing feature is to identify LABELs that are on top of the found instances. 

I tried to use dbGetOverlap() function, within the below code, in few setups but it seems to fail to identify the existence of labels on top of the found instances.

For example: 

overlapLabel=dbGetTrueOverlaps(cv cadr(instBox) list("M1" "text"))

I am interested to add to the Cadence's solution below some code in order to identify labels on top of the found instances.

Any tip would be greatly appreciated.

Thanks,

Danny

--------------------------------------------------------

I can get the bound stdcells using bndGetBoundObjects, but not get what each individual stdcell corresponds in layout.

Is there a way to get the layout bound stdcells of an array schematic symbol if the layout stdcell name do or do not match the symbol naming?

Once the schematic array stdcells are bound to the layout stdcells, how to get the correct terminal term~>name and net~>name?

Example of a schematic symbol and layout stdcell:

Schematic

INV<0:2>    instTerms~>terms~>name = ("vss" "vdd" "A" "Y")

                   instTerms~>net~>name = ("<*3>vss" "<*3>vdd" "in<0:2>" "nand2A,nand3B,nor2B")

Layout ( I know it is bad practice, but it happens )

stdcell1 instTerms~>terms~>name = ("vss" "vdd" "A" "Y")

             instTerms~>net~>name = ("vss" "vdd" "in<0>" "nand2A")

I23        instTerms~>terms~>name = ("vss" "vdd" "A" "Y")

             instTerms~>net~>name = ("vss" "vdd" "in<1>" "nand3B")

INV(2) instTerms~>terms~>name = ("vss" "vdd" "A" "Y")

             instTerms~>net~>name = ("vss" "vdd" "in<2>" "nor2B")

Paul

I want to select a constraint, and then run a SKILL command that returns a list with the members of that constraint. Is this possible?

Thx,

I have a modeless informational dialog box defined at the beginning of a SKILL script, but its contents don't display until the script finishes.

How do you get a modeless dialog box contents to display while a SKILL script is running?

procedure(myproc()

   prog((myvars)

     hiDisplayAppDBox()    ; opens blank dialog box - no dboxText contents show until script completes!

     ....rest of SKILL code in script...launches child processes

   );prog

);proc

When I place a pcell and do not change the W parameter (default is used) the value is not saved in the OA cell property.

When I change the default value of the super master now, the old pcell will get the new default value automatically because there is nothing saved inside the OA cell for this parameter.

Do you have any Idea, that how we can save the default values in the OA cell properties so that this value doesn't get updated if the default values are updated in the new PDKs

I have a top cell & need to revise all the instances' cellview & export top cell as a new GDS file.

So I write a SKILL code to do so and I find out it will be a little bit slow by using the dbSave to save the cellview of each instance.

Code as below:

let( (topCV subCV )
topCV = dbOpenCellViewByType(newLibName topCellName "layout" "maskLayout" "a")
foreach(inst topCV->instances
subCV = dbOpenCellViewByType(newLibName inst->cellName "layout" "maskLayout" "a")
;;;revise code content
;;;...
;;;revise code content
dbSave(subCV)
dbClose(subCV)
)
dbSave(topCV)
dbClose(topCV)
system(strcat( "strmout -library " newLibName " -topCell " topCellName " -view layout -strmFile " resultFolder "/" topCellName ".gds -techLib " srcLibName " -enableColoring -logFile " topCellName "_strmOut.log" ) )
)

Even if the cell content is not revised, the run time of dbSave will be 2 minutes when there are ~ 1000 instances in topcell. The exported GDS file size is ~2MB.

And the dbSave becomes the bottle neck of the code runtime...

Is there any better way to do such a thing? 

Hi,

I am trying add multiple choices to my radio field in cdf parameters. when i see the select the instance and try editing the Instance properties I can not view them in a single window. Instead i get a vertical sliding bar. Is there a way to display them in multiple rows?

-Haareeth

Hello,

After deleting cells using the following loop:

foreach(cellId ddGetObj(libName)~>cells
    ddDeleteObj(cellId)
)

the following warnings are printed in the CIW:

*WARNING* (SCH-2162): "... symbol" has been updated since "... schematic" was last saved. Validate that the schematic is correct and run Check and Save to suppress this warning.
*WARNING* (DB-270337): dbGetInstHeaderMaster: Failed to open cellview '...' from library '...' in read-only mode because the cellview does not exist. This cellview was instantiated in cellview '...' of library '...'. Ensure that the cellview exists in the library.

Is it possible to turn them off?

Thank you

Best regards,

Aldo

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