Certain embodiments of the present disclosure are directed to a baseboard management controller (BMC) that includes a PCI express (PCIe) interface controller configured to provide access to a PCIe channel over a PCIe link, and firmware. The firmware includes a PCIe module being configured to access the PCIe channel through the PCIe interface controller and registered as a PCIe function. A software stack of the BMC communicates, through the PCIe module, with a PCIe device over the PCIe channel.

Various embodiments include apparatuses, stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In some embodiments, the conductive paths may be arranged to connect with circuitry on alternating dice of the stack. In other embodiments, a plurality of dice stacks may be arranged on a single interface die, and some or all of the dice may have interleaving conductive paths.

A system, method and computer-readable media for managing a compute environment are disclosed. The method includes importing identity information from an identity manager into a module performs workload management and scheduling for a compute environment and, unless a conflict exists, modifying the behavior of the workload management and scheduling module to incorporate the imported identity information such that access to and use of the compute environment occurs according to the imported identity information. The compute environment may be a cluster or a grid wherein multiple compute environments communicate with multiple identity managers.

A system and method for detecting, filtering, prioritizing and reporting shared memory hazards are disclosed. The method includes, for a unit of hardware operating on a block of threads, mapping a plurality of shared memory locations assigned to the unit to a tracking table. The tracking table comprises initialization information for each shared memory location. The method also includes, for an instruction of a program within a barrier region, identifying a potential conflict by identifying a second access to a location in shared memory within a block of threads executed by the hardware unit. First information associated with a first access and second information associated with the second access to the location is determined. Filter criteria is applied to the first and second information to determine whether the instruction causes a reportable hazard. The instruction is reported when it causes the reportable hazard.

Methods and systems for statistically eliding fences in a work stealing algorithm are disclosed. A data structure comprising a head pointer, tail pointer, barrier pointer and an advertising flag allows for dynamic load-balancing across processing resources in computer applications.

Some embodiments provide a method for managing a logical switching element that includes several logical ports. The logical switching element receives and sends data packets through the logical ports. The logical switching element is implemented in a set of managed switching elements that forward data packets in a network. The method provides a set of tables for specifying forwarding behaviors of the logical switching element. The method performs a set of database join operations on the tables to specify in the tables that the logical forwarding element drops a data packet received through a first logical port when the data packet is headed to a second logical port different than the first logical port.

The technology of the present application provides a networked computer system with at least one workstation and at least one shared resource such as a database. Access to the database by the workstation is managed by a database management system. An access engine reviews job requests for access to the database and allows job requests access to the resource based protocols stored by the system.

According to an embodiment, based on task border information, and first-type dependency relationship information containing N number of nodes corresponding to data accesses to one set of data, containing edges representing dependency relationship between the nodes, and having at least one node with an access reliability flag indicating reliability/unreliability of corresponding data access; task border edges, of edges extending over task borders, are identified that have an unreliable access node linked to at least one end, and presentation information containing unreliable access nodes is generated. According to dependency existence information input corresponding to the set of data, conversion information indicating absence of data access to the unreliable access nodes is output. According to the conversion information, the first-type dependency relationship information is converted into second-type dependency relationship information containing M number of nodes (0≦M≦N) corresponding to data accesses to the set of data and containing edges representing inter-node dependency relationship.

Disclosed is an information processing device and a task switching method that can reduce the time required for switching of tasks in a plurality of coprocessors. The information processing device (30) includes a processor core (301); coprocessors (311 to 31n) including operation units (321 to 32n) that perform operation in response to a request from the processor core (301) and operation storage units (331 to 22n) that store the contents of operation of the operation units (321 to 32n), save storage units (351 to 35n) that store the saved contents of operation, a task switching control unit (302) that outputs a save/restore request signal when switching a task on which operation is performed by the coprocessors (311 to 31n), and save/restore units (341 to 34n) that perform at least one of saving of the contents of operation in the operation storage units (331 to 33n) to the save storage units (351 to 35n) and restoration of the contents of operation in the save storage units (351 to 35 n) to the operation storage units (331 to 33n) in response to the save/restore request signal.

A process for producing a fluoroalkyl iodide as a telomer Rf(CF2CF2)nI (wherein Rf is a C1-10 fluoroalkyl group, and n is an integer of from 1 to 6) by telomerization from a fluoroalkyl iodide represented by the formula RfI (wherein Rf is as defined above) as a telogen and tetrafluoroethylene (CF2CF2) as a taxogen, which comprises a liquid phase telomerization step of supplying a homogeneous liquid mixture of the telogen and the taxogen from the lower portion of a tubular reactor, moving the mixture from the lower portion towards the upper portion of the reactor in the presence of a radical initiator over a retention time of at least 5 minutes while the reaction system is kept in a liquid phase state under conditions where no gas-liquid separation will take place, so that the taxogen supplied to the reactor is substantially consumed by the reaction in the reactor, and drawing the reaction product from the upper portion of the reactor.

A method of synthesizing an alkyl cyclopentadiene compound is disclosed. The method includes contacting at least one cyclopentadienyl anion source and at least one alkyl group source to form at least one alkyl cyclopentadiene compound. The method further includes extracting the alkyl cyclopentadiene compound with a hydrocarbon solvent. The alkyl cyclopentadiene compound may be converted to a metallocene catalyst compound.

This invention relates to fluoroalkyl and chlorofluoroalkyl benzenes with relatively high boiling points, having zero ozone depletion potential and low global warming potential. This invention also relates to the preparation of such fluoroalkyl and chlorofluoroalkyl benzenes. These materials can be used as reaction and heat transfer media, cleaning agents and as intermediates for biologically active materials.

Disclosed is a process for the synthesis of 1,1,2,3-tetrachloropropene (HCC-1230xa) using 1,1,3-trichloropropene (HCC-1240za) and/or 3,3,3-trichloropropene (HCC-1240zf) and Cl2 gas as the reactants, wherein the process takes place in a single reactor system. Before this invention, HCC-1230xa was made in a two-step process using HCC-1240za/HCC-1240zf and Cl2 gas, and the processing was conducted using two separate reactors.

The invention is to provide a new liquid crystal compound having a high clearing point, a good compatibility with other compounds, a small viscosity, and a high stability to heat, light and so forth; compound (1) is provided: R1CF2nR2 (1) wherein, for example, R1 is alkyl having 4 to 10 carbons or —(CH2)2—CH═CH2, R2 is alkyl having 2 to 10 carbons, n is 8, and R1 and R2 are not allowed to be straight-chain alkyl having an identical number of carbons.

The disclosure describes a process for dehalogenation of chlorofluorocompounds. The process comprises contacting a saturated chlorofluorocompound with hydrogen in the presence of a catalyst at a temperature sufficient to remove chlorine and/or fluorine substituents to produce a fluorine containing terminal olefin.

The invention relates to a process for removing one or more undesired (hydro)halocarbon compounds from a (hydro)fluoroalkene, the process comprising contacting a composition comprising the (hydro)fluoroalkene and one or more undesired (hydro)halocarbon compounds with an aluminum-containing absorbent, activated carbon, or a mixture thereof.

Disclosed is a reactor and agitator useful in a high pressure process for making 1-chloro-3,3,3-trifluoropropene (1233zd) from the reaction of 1,1,1,3,3-pentachloropropane (240fa) and HF, wherein the agitator includes one or more of the following design improvements: (a) double mechanical seals with an inert barrier fluid or a single seal;(b) ceramics on the rotating faces of the seal;(c) ceramics on the static faces of seal;(d) wetted o-rings constructed of spring-energized Teflon and PTFE wedge or dynamic o-ring designs; and(e) wetted metal surfaces of the agitator constructed of a corrosion resistant alloy.

To provide a method for efficiently separating 2,3,3,3-tetrafluoropropene (HFO-1234yf) and chloromethane (R40) from a composition comprising HFO-1234yf and R40. An azeotrope-like composition comprising from 58 to 78 mol % of HFO-1234yf and from 22 to 42 mol % of R40, and a method for producing HFO-1234yf, which comprises steps of distilling an initial mixture containing HFO-1234yf in a content exceeding 63 mol % in the total amount of HFO-1234yf and R40, thereby to separate the initial mixture into a first fraction in which the content of HFO-1234yf in the total amount of HFO-1234yf and R40 is lower than the content of HFO-1234yf in the total amount of HFO-1234yf and R40 in the initial mixture, and a second fraction in which the content of HFO-1234yf in the total amount of HFO-1234yf and R40 is higher than the content of HFO-1234yf in the total amount of HFO-1234yf and R40 in the initial mixture, and then obtaining HFO-1234yf having a reduced R40 concentration, from the second fraction.

The disclosure provides a method for crosslinking a colloid, including: (a) providing a colloid solution; (b) adding a crosslinking agent and solid particles to the colloid solution, wherein the amount of solid particles added is enough to convert the colloid solution into a solid mixture, and wherein a crosslinking reaction proceeds in the solid mixture; and (c) removing the solid particles from the solid mixture.

Particular aspects provide compositions comprising an electrokinetically altered oxygenated aqueous fluid, wherein the oxygen in the fluid is present in an amount of at least 25 ppm. In certain aspects, the electrokinetically altered oxygenated aqueous fluid comprises electrokinetically modified or charged oxygen species present in an amount of at least 0.5 ppm. In certain aspects the electrokinetically altered oxygenated aqueous fluid comprises solvated electrons stabilized by molecular oxygen, and wherein the solvated electrons present in an amount of at least 0.01 ppm. In certain aspects, the fluid facilitates oxidation of pyrogallol to purpurogallin in the presence of horseradish peroxidase enzyme (HRP) in an amount above that afforded by a control pressure pot generated or fine-bubble generated aqueous fluid having an equivalent dissolved oxygen level, and wherein there is no hydrogen peroxide, or less than 0.1 ppm of hydrogen peroxide present in the electrokinetic oxygen-enriched aqueous fluid.

A manufacturing method of a glass substrate for a magnetic disk is provided whereby nano pits and/or nano scratches cannot be easily produced in polishing a principal face of a glass substrate using a slurry containing zirconium oxide as an abrasive. The manufacturing method of a glass substrate for a magnetic disk includes, for instance, a polishing step of polishing a principal face of a glass substrate using a slurry containing, as an abrasive, zirconium oxide abrasive grains having monoclinic crystalline structures (M) and tetragonal crystalline structures (T).

The disclosure relates to methods of making polymer particles, said methods including the steps of: making an aqueous gel reaction mixture; forming an emulsion having dispersed aqueous phase micelles of gel reaction mixture in a continuous phase; adding an initiator oil comprising at least one polymerization initiator to the continuous phase; and performing a polymerization reaction in the micelles. Further, the initiator oil is present in a volume % relative to a volume of the aqueous gel reaction mixture of between about 1 vol % to about 20 vol %. The disclosure also relates to methods of making nucleic acid polymer particles having the same method steps and wherein the aqueous gel reaction mixture includes a nucleic acid fragment, such as a primer.

A method for synthesizing catalyst beads of bulk transmission metal carbides, nitrides and phosphides is provided. The method includes providing an aqueous suspension of transition metal oxide particles in a gel forming base, dropping the suspension into an aqueous solution to form a gel bead matrix, heating the bead to remove the binder, and carburizing, nitriding or phosphiding the bead to form a transition metal carbide, nitride, or phosphide catalyst bead. The method can be tuned for control of porosity, mechanical strength, and dopant content of the beads. The produced catalyst beads are catalytically active, mechanically robust, and suitable for packed-bed reactor applications. The produced catalyst beads are suitable for biomass conversion, petrochemistry, petroleum refining, electrocatalysis, and other applications.

Method for making a liquid foam from graphene. The method includes preparing an aqueous dispersion of graphene oxide and adding a water miscible compound to the aqueous dispersion to produce a mixture including a modified form of graphene oxide. A second immiscible fluid (a gas or a liquid) with or without a surfactant are added to the mixture and agitated to form a fluid/water composite wherein the modified form of graphene oxide aggregates at the interfaces between the fluid and water to form either a closed or open cell foam. The modified form of graphene oxide is the foaming agent.

A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.

The disclosure relates to the implementation of multi-tasking on a digital signal processor. Blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which instead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. Whilst the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.

Embodiments provide methods, apparatus, systems, and computer readable media associated with predicting predicates and branch targets during execution of programs using combined branch target and predicate predictions. The predictions may be made using one or more prediction control flow graphs which represent predicates in instruction blocks and branches between blocks in a program. The prediction control flow graphs may be structured as trees such that each node in the graphs is associated with a predicate instruction, and each leaf associated with a branch target which jumps to another block. During execution of a block, a prediction generator may take a control point history and generate a prediction. Following the path suggested by the prediction through the tree, both predicate values and branch targets may be predicted. Other embodiments may be described and claimed.

An array of a plurality of processing elements (PEs) are in a data packet-switched network interconnecting the PEs and memory to enable any of the PEs to access the memory. The network connects the PEs and their local memories to a common controller. The common controller may include a shared load/store (SLS) unit and an array control unit. A shared read may be addressed to an external device via the common controller. The SLS unit can continue activity as if a normal shared read operation has taken place, except that the transactions that have been sent externally may take more cycles to complete than the local shared reads. Hence, a number of transaction-enabled flags may not have been deactivated even though there is no more bus activity. The SLS unit can use this state to indicate to the array control unit that a thread switch may now take place.

A framework for implementing multitenant architecture is provided. The framework comprises a framework services module which is configured to provide framework services that facilitate abstraction of Software-as-a-Service (SaaS) services and crosscutting services for a Greenfield application and a non SaaS based web application. Further the abstraction results in a SaaS based multitenant web application. The framework further comprises a runtime module configured to automatically integrate and consume the framework services and APIs to facilitate monitoring and controlling of features associated with the SaaS based multitenant web application. The framework further comprises a metadata services module configured to provide a plurality of metadata services to facilitate abstraction of storage structure of metadata associated with the framework and act as APIs for managing the metadata. The framework further comprises a role based administration module that facilitates management of the metadata through a tenant administrator and a product administrator.

An individual alkamide and/or a mixture having two or more different alkamides, is disclosed for changing, masking or reducing the unpleasant flavor impression of an unpleasant-tasting substance or mixture of substances. The alkamide can be trans-pellitorine; cis-pellitorine; 2Z,4Z- or 2Z,4E-decadienoic acid-N-isobutylamide; 2E,4E-decadienoic acid-N-([2S]-2-methylbutyl)amide; 2E,4E-decadienoic acid-N-([2R]-2-methylbutylamide); 2E,4Z-decadienoic acid-N-(2-methylbutyl)amide; achilleamide; sarmentine; 2E- or 3E-decenoic acid-N-isobutylamide; 3E-nonenoic acid-N-isobutylamide; spilanthol; homospilanthol; 2E,6Z,8E-decatrienoic acid-N-([2R]-2-methylbutyl)amide; 2E- or 2Z-decen-4-oic acid-N-isobutylamide; α-sanshool; α-hydroxysanshool; γ-hydroxysanshool; γ-hydroxysanshool; γ-hydroxyisosanshool; γ-dehydrosanshool; γ-sanshool; bungeanool; isobungeanool; dihydrobungeanool; or tetrahydrobungeanool, or combinations thereof.

The present invention primarily concerns certain 4-alkyl pyridines of the following formula (I), wherein R is C8-C12 alkyl, odiferous substance mixtures and aromatic substance mixtures containing these 4-alkyl pyridines, the respective uses thereof as an odiferous or aromatic substance (mixture) and corresponding perfumed products.

The present invention relates to a process for preparing cyclic compounds having at least eight carbon atoms and at least one keto group, to the cyclic compounds obtained by this process and to the use thereof, in particular as fragrance or for providing a fragrance.

A process for selective formation of ethanol from acetic acid by hydrogenating acetic acid in the presence of a catalyst comprises a first metal on an acidic support. The acidic support may comprise an acidic support material or may comprise an support having an acidic support modifier. The catalyst may be used alone to produced ethanol via hydrogenation or in combination with another catalyst. In addition, the crude ethanol product is separated to obtain ethanol.

A process is disclosed for producing ethanol comprising contacting acetic acid and hydrogen in a reactor in the presence of a catalyst comprising a binder and a mixed oxide comprising nickel and tin.

Disclosed are processes relating to the production of polyglycerol ethers of fatty alcohols, in particular, one step process using fatty alcohol and glycerine to synthesize polyglycerides of fatty alcohols will provide a 100% renewable surfactant that is cost effective efficient and CMR free. The synthetic methods mentioned in prior art uses hazardous chemicals as glycidyl ethers, epichlorohydrin that are listed as CMR and known carcinogens and hazardous to handle.

The invention relates to compressed data transmission in wireless data communication. Disclosed are methods and apparatuses for transporting residue of vehicle position data via a wireless network. A disclosed method for transporting residue of vehicle position data via a wireless network, includes the steps of: receiving data for updating residue encoding schema from a monitoring server; constructing a residue encoding schema based on the data, thereby producing a constructed residue encoding schema; and storing the constructed residue encoding schema such that the constructed residue encoding schema will become the current residue encoding schema; where: the constructed residue encoding schema is constructed such that each residue of the constructed residue encoding schema corresponds to a code; and the constructed residue encoding schema is constructed such that a residue having a relatively high probability of occurrence corresponds to a code of relatively short length.

An automated process uses a local positioning system to acquire location (i.e., position and orientation) data for one or more movable target objects. In cases where the target objects have the capability to move under computer control, this automated process can use the measured location data to control the position and orientation of such target objects. The system leverages the measurement and image capture capability of the local positioning system, and integrates controllable marker lights, image processing, and coordinate transformation computation to provide tracking information for vehicle location control. The resulting system enables position and orientation tracking of objects in a reference coordinate system.

Described herein is a descriptive framework to facilitate large scale demand responsive transit. In accordance with one aspect of the framework, one or more trip requests from one or more commuter devices are received. A trip request indicates at least one start location and at least one end location. In addition, vehicle information is received from one or more available vehicles. The vehicle information indicates at least one current location of a vehicle. An adaptive route for the vehicle may be planned based on the one or more trip requests and the vehicle information. Update information of the adaptive route may be communicated to the vehicle and the one or more commuter devices.

A parking assist system includes: an actuator that drives a back door of a vehicle; an opening degree control unit that controls an opening degree of the back door by controlling the actuator; a storage device that stores an allowable opening degree of the back door at a park position of the vehicle in association with the park position; and a position information acquisition unit that acquires position information of the vehicle. When a position of the vehicle corresponds to the park position stored in the storage device, the opening degree control unit limits the opening degree of the back door on the basis of the allowable opening degree of the back door, stored in the storage device in association with the park position.

Vehicle event recorder systems are arranged to be in constant communication with remote servers and administrators via mobile wireless cellular networks. Vehicle event recorders equipped with video cameras capture video and other data records of important events relating to vehicle use. These data are then transmitted over special communications networks having very high coverage space but limited bandwidth. A vehicle may be operated over very large region while maintaining continuous communications connections with a remote fixed server. As such, systems of these inventions may be characterized as including a mobile unit having: a video camera; a microprocessor; memory; an event trigger; and mobile wireless transceivers, and a fixed network portion including: mobile wireless cellular network, a protocol translation gateway, the Internet and an application-specific server.

A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.

One implementation of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing a layout suggestion table when the crosstalk value is larger than the predetermined value.

A method includes providing a design of a semiconductor device such as a stacked CMOS device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based on at least one predetermined criterion. Each respective one of the at least one first type of circuit element is to be assigned to a respective designated one of the plurality of tiers. The method further includes dividing the remainder of the plurality of circuit elements into at least two groups of circuit elements based on circuit density, and assigning the at least one first type of circuit element and the at least two groups of circuit elements to respectively different ones of the plurality of tiers of the semiconductor device.

A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.

An integrated circuit having a programmable clock spreader configured to generate a plurality of controllably skewed clock signals, each applied to a corresponding region within the integrated circuit with circuitry configured to be triggered off the applied clock signal. The programmable clock spreader is designed to enable customization of the current-demand characteristics exhibited by the integrated circuit, e.g., based on the circuit's spectral impedance profile, to cause transient voltage droops in the power-supply network of the integrated circuit to be sufficiently small to ensure proper and reliable operation of the integrated circuit.

An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

Methods for the design of microwave filters comprises comprising preferably the steps of inputting a first set of filter requirements, inputting a selection of circuit element types, inputting a selection of lossless circuit response variables, calculating normalized circuit element values based on the input parameters, and generate a first circuit, insert parasitic effects to the normalized circuit element values of the first circuit, and output at least the first circuit including the post-parasitic effect circuit values. Additional optional steps include: requirements to a normalized design space, performing an equivalent circuit transformation, unmapping the circuit to a real design space, performing a survey, and element removal optimization. Computer implement software, systems, and microwave filters designed in accordance with the method are included.

A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least partly on the generated signal behaviour description, and performing gate-level simulation using the generated gate-level stimuli to generate gate-level activity data for the IC design. In one embodiment, generating the signal behaviour description includes performing Register Transfer Level (RTL) simulation of the IC design, and generating the gate-level netlist includes performing RTL synthesis. The RTL simulation and RTL synthesis are performed on RTL data for the IC design.

The present disclosure relates a method of performing a design rule checking (DRC) procedure on a multi-tiered integrated chip. In some embodiments, the method is performed by defining layer databases for a plurality of tiers within a multi-tiered integrated chip. The layer databases respectively identify design layers within an associated tier. A DRC (design rule checking) deck is then generated, which defines one or more individual design layer definitions as a function of a plurality of layer databases, so that the one or more individual design layer definitions are defined for a plurality of tiers. One or more design rules for the one or more individual design layer definitions are defined within the DRC deck. Since the individual design layer definitions are defined as functions of the plurality of layer databases, the design rules apply to the plurality of tiers.

A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of horizontal interconnects and gap channels. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. The highest crosstalk may comprise far-end crosstalk or near-end crosstalk and may be calculated for a range of frequencies or for a plurality of frequencies. The crosstalk may be calculated by modeling the interconnects as transmission lines.