A conditioning device for a forage harvester is equipped with a first roller, profiled in the axial direction, and a second roller, also profiled in the axial direction. The two rollers are rotated, around their axes, in opposite directions and are aligned parallel to one another. An element, profiled, in the axial direction, in a manner complementary to the profile of the first roller and adjacent to the circumference of the first roller, for the removal of crop residues from the roller, extends in a circular arc over a part of the circumference of the first roller.

A grass cutting machine with two cutting units mounted on opposite sides of the chassis has an inclinometer monitoring the left/right inclination of the chassis. If the inclination value exceeds a defined threshold, the higher of the two cutting units is lifted to improve stability.

An agricultural working machine has a one control/regulating unit designed to adjust and monitor working parameters, quality parameters or both of the agricultural working machine that influence a harvesting process. The adjusting and monitoring are carried out in an automatable manner by the control/regulating unit using stored families of characteristics. The agricultural working machine also has at least one display device for depicting setpoint values and actual values of the working parameters, quality parameters or both. The control/regulating unit actuates defined measurement points in the stored families of characteristics and the specifically actuated measurement points are located in the boundary regions of the family of characteristics or outside the active working region of the particular family of characteristics.

A mower carrying a rotary cutting deck has a height of cut system for adjusting the vertical position of the deck relative to the mower frame for changing or adjusting the height of cut. The height of cut system comprises a pair of parallel cross shafts that carry a plurality of pivotal suspension linkages that connect to the deck, the cross shafts and linkages pivoting jointly with one another and with a pivotal control lever. One of the cross shafts carries a torsion spring to counterbalance the weight of the deck. The control lever is maintained in a plurality of adjusted pivotal positions by a height selection bracket fixed to the frame with the height selection bracket being capable of having its position changed or adjusted relative to the frame by a single adjustment bolt. Each suspension linkage has its effective length adjusted by turning a threaded adjuster carried at the upper end of a connecting rod that is part of each linkage to allow the deck to be leveled relative to a reference plane. The adjustment of the height selection bracket is accomplished without affecting the length adjustments previously made to any of the suspension linkages.

A harvesting machine for threshing crop materials includes a platform supported in front of a chassis, an erecting device having a number pairs of guiding bars attached to the platform and having a channel formed between two bar members of each pair of guiding bars, a guiding element disposed between every two adjacent pairs of guiding bars for guiding a stalk of the crop materials into the channel of the guiding bars, a number of pawls extended into the channel for sending the stalk of the crop materials into the channel, and a cutting device having two or more cutting elements for cutting the stalk into a lower base segment that carries no grain and an upper straw segment that carries grains.

A stalk reducer bar and an assembly that supports, transports, and rotatably drives a stalk reducer bar in typical environments in which an area of vegetation is to be trimmed are provided. The stalk reducer bar reduces the size of cut stalk segments such as grass stalks segments generated during a lawn mowing operation and includes a carrier body. The carrier body includes a further working portion having a plurality of projections and angular movement of the carrier body in the cutting plane operates to bring the first blade section into stalk cutting engagement with stalks extending from the surface supporting organic matter thereon and operates to bring the plurality of projections of the further working portion into shredding engagement with cut stalks.

The present invention provides a method for measuring reflective intensity of display surface, including: obtaining a luminance value of a first display and a luminance value of a second display when displaying, the first display and the second display having the same observed luminance, the peripheral of the surface of the first display being surrounded by light-shielding object, the first display and the second display being placed side by side; and obtaining the reflective intensity of the display surface in the ambient based on the luminance value of the first display and the luminance values of the second display when displaying. As such, the present invention provides convenient and accurate means to measure the reflective intensity of display surface.

A system is provided that automatically stops a tractor as a function of a status of a round baler. This may include a controller such as a baler controller directly or indirectly detecting initial movement of an actuator that moves a wrapper assembly. Based on this detection, conditions for starting a wrap procedure may be determined either by actuator position or by a time period required for moving the wrapper assembly from a home position to a wrap start position. A time period required to bring the tractor to stop may be determined and compared with the time period required for the wrapper assembly to move from the home position to the wrap start position. The baler controller may send a tractor halt command signal for stopping the tractor to coordinate and synchronize bringing the tractor to a complete stop at the same time that the wrapping material is inserted and applied onto the bale at the beginning of a wrapping procedure.

A mower assembly is provided for cutting around a post. A support structure supports the mower assembly in cantilever fashion. The mower assembly includes a plurality of mower units with each mower unit having a rotary blade. Two or more mower units cooperate to engage and cut around a post and, during the process, the entire mower assembly rotates about an axis enabling the mower units to encircle and efficiently cut grass and other vegetation about the post.

A riding lawn mower may include a cutting deck coupled to a cutting blade, an engine, a deck drive coupled to the engine to receive power for operating the cutting blade, a ground drive coupled to the engine to receive power for movement of the riding lawn mower over ground, and a friction drive coupling the deck drive to the engine.

The weed trimmer head is comprised of a sole plate having a diameter; a circumference; a plurality of pivot pins extending upwardly therefrom near the circumference. The sole plate also has a driving shaft extending upwardly therefrom from a center thereof. The driving shaft has a threaded segment thereon. A plurality of cutting blades are pivotally mounted to the plurality of pivot pins. A wingnut plate is also provided. This wingnut plate has a disc-like portion and wing blades extending on an upper side thereof. The wingnut plate has a threaded hole in its disc-like portion. The threaded hole is mounted to the threaded segment of the driving shaft and the wingnut plate is movable along the threaded segment, for selectively contacting or exposing the ends of the pivot pins.

A combine harvester is provided that separates grain material from material other than grain using multiple processing areas, including a harvesting area, a feederhouse area, a threshing area, a cleaning area, and a grain delivery area. In a location at or prior to entering one of the processing areas, the material may be collected and held until a collection threshold is reached. Once it is determined that the collection threshold is reached, the material forming a first group of material may be transported from the location to the processing area or a subsequent processing area. The first group of material is transported from the location to the processing area or the subsequent processing area substantially simultaneously and thus simulates the gathering of a large amount of crop material even when small plots are involved. In this way, reduced cycle times may be achieved, and the efficiency benefits of large-plot harvesting may be extended to small-plot applications.

A vehicle and a method of controlling a dynamometer mode operation of a vehicle that includes requesting the dynamometer mode; monitoring for at least one non-dynamometer vehicle operating condition; if at least one of the non-dynamometer vehicle operating conditions is detected, prohibiting dynamometer mode; and if none of the non-dynamometer vehicle operating conditions is detected, operating the vehicle in dynamometer mode.

A corn harvesting header comprises a knife bar extending along a front lower edge of a cutting header, with triangular knife sections attached along the bar and a plurality of guards with guard fingers extending forward. Pointed divider pans extend forward from the header such that a slot is formed between adjacent pans. A mounting bracket extends down from a rear of each pan and is attached to forward end portions of a pair of adjacent guard fingers, leaving rear portions of these guard fingers exposed. The divider pans are attached to alternating pairs of guard fingers such that a pair of bare guard fingers extends forward under and laterally adjacent to edges of each slot. The bottom surface of each seed pan is above the guard fingers an elevated distance that is greater than a spacing distance between the guard fingers. The header cuts the corn rows at angle.

A reel lawn mower which has a connection structure for connecting a reel cutting unit to a main body. The reel cutting unit has a spiral cutting reel which is rotated by a prime mover to cut grass together with a bedknife. In the connection structure, in order to connect the reel cutting unit to the main body so that the reel cutting unit rolls around a virtual horizontal line perpendicular to the shaft center of the cutting reel in the center of the axial direction of the cutting reel, the reel cutting unit includes a connecting arm with an arc portion shaped so as to follow a virtual arc centered on the virtual horizontal line. The connecting arm is slidably supported so as to prevent the arc portion from coming off the virtual arc.

A corn header has a row unit frame and an auger sweeping ears of corn toward a center of the corn header. A corn row divider assembly has a snout and gatherer hood hingeably coupled to, and aft of, the snout. An aft end of the gatherer hood is located beneath and to the rear of the fore end of the auger in an operational configuration of the divider assembly. The divider assembly further has a four-point hinge assembly coupling the aft end of the gatherer hood to the row unit frame. The four-point hinge assembly is configured to pivot the gatherer hood between the operational configuration and a non-operational configuration in which the gatherer hood is in a raised condition. The four-point hinge assembly moves the aft end of the gatherer hood forward so that the gatherer hood clears the auger when pivoting to the non-operational configuration.

A rotary implement includes a metallic body that is rotatable around an axis. The metallic body includes a tapered leading edge having an interface surface and an opposite, free surface. The metallic body has a first composition. A metallic layer has a first side surface that is attached to the interface surface and a free, second side surface opposite from the first side surface. The metallic layer has a second, different composition from the first composition. A rotary machine can include an actuator and the rotary implement operably coupled to the actuator. A method for making a rotary implement includes providing the metallic body that has the tapered leading edge having the interface surface and the opposite, free surface. The metallic layer is then attached to the interface surface of the metallic body.

A package includes a device die, which includes a metal pillar at a top surface of the device die, and a solder region on a sidewall of the metal pillar. A molding material encircles the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die, with a bottom surface of the dielectric layer contacting a top surface of the device die and a top surface of the molding material. A redistribution line (RDL) extends into the dielectric layer to electrically couple to the metal pillar.

Disclosed herein is a wafer processing method including a processed position measuring step of imaging an area including a beam plasma generated by applying a pulsed laser beam to a wafer, by using an imaging unit during the formation of a laser processed groove on the wafer, and next measuring the positional relation between the position of the beam plasma and a preset processing position. Accordingly, it is possible to check whether or not the laser processed groove is formed at a desired position, in real time during laser processing. If the position of the laser processed groove is deviated, the processed position can be immediately corrected.

A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die. A second prefabricated insulating film is disposed over the first prefabricated insulating film.

An example method includes providing a packaging device includes a substrate having an integrated circuit die mounting region. A plurality of microstructures, each including an outer insulating layer over a conductive material, are disposed proximate a side of the integrated circuit die mounting region. An underfill material is disposed between the substrate and the integrated circuit die, the microstructures preventing spread of the underfill. In another example method, a via can be formed in a substrate and the substrate etched to form a bump or pillar from the via. An insulating material can be formed over the bump or pillar. In another example method, a photoresist deposited over a seed layer and patterned to form openings. A conductive material is plated in the openings, forming a plurality of pillars or bumps. The photoresist and exposed seed layer are removed. The conductive material is oxidized to form an insulating material.

A method of making a semiconductor device can include providing a wafer comprising a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface. A photosensitive layer can be formed over the wafer and on a backside of each of the plurality of semiconductor die within the wafer with a coating machine. An identifying mark can be formed within the photosensitive layer for each of the plurality of semiconductor die with a digital exposure machine and a developer, wherein a thickness of the identifying mark is less than or equal to 50 percent of a thickness of the photosensitive layer. The photosensitive layer can be cured. The wafer can be singulated into a plurality of semiconductor devices.

A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in such a way as to surround the circuit region and a second moisture-resistant ring disposed in the peripheral region in such a way as to surround the first moisture-resistant ring.

A manufacturing method of a package substrate is provided. The method includes forming a first circuit layer on a carrier. A passive component is disposed on the first circuit layer and the carrier. A dielectric layer is formed on the carrier to embed the passive component and the first circuit layer in the dielectric layer. A second circuit layer is formed on the dielectric layer. The carrier is removed from the dielectric layer. A manufacturing method of a chip package is also provided.

A method for wafer-level packaging includes providing a substrate having a conductive metal pad formed on the surface of the substrate; forming a metal core on the top of the conductive metal pad with the metal core protruding from the surface of the substrate; then, forming an under bump metal layer on the top surface and the side surface of the metal core; and finally, forming a bump structure on the top of the under bump metal layer.

A semiconductor mounting apparatus includes a storing unit that stores a liquid or a gas, a contact unit that comes into contact with a semiconductor chip when the storing unit is filled with the liquid or the gas, and a sucking unit that sucks up the semiconductor chip to bring the semiconductor chip into close contact with the contact unit.

A system for determining thickness variation values of a semiconductor substrate comprises a substrate vacuumed to a pedestal that defines a reference plane for measuring the substrate. A measurement probe assembly determines substrate CTV and BTV values, and defines a substrate slope angle. A thermal bonding assembly attaches a die to the substrate at a bonding angle congruent with the substrate slope angle. A plurality of substrates are measured using the same reference plane on the pedestal. Associated methods and processes are disclosed.

A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; (b) ultrasonically forming tack bonds between ones of the first conductive structures and respective ones of the second conductive structures; and (c) forming completed bonds between the first conductive structures and the second conductive structures.

Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.

A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.

A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

Embodiments of the inventive concepts provide a method for manufacturing a semiconductor device. The method includes forming a stack structure including insulating layers and sacrificial layers which are alternately and repeatedly stacked on a substrate. A first photoresist pattern is formed on the stack structure. A first part of the stack structure is etched to form a stepwise structure using the first photoresist pattern as an etch mask. The first photoresist pattern includes a copolymer including a plurality of units represented by at least one of the following chemical formulas 1 to 3, wherein “R1”, “R2”, “R3”, “p”, “q” and “r” are the same as defined in the description.

A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.

A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.

Embodiments of the inventive concept provide a method for manufacturing a semiconductor device. The method includes forming a stack structure by alternately and repeatedly stacking insulating layers and sacrificial layers on a substrate, sequentially forming a first lower layer and a first photoresist pattern on the stack structure, etching the first lower layer using the first photoresist pattern as an etch mask to form a first lower pattern. A first part of the stack structure is etched to form a stepwise structure using the first lower pattern as an etch mask. The first lower layer includes a novolac-based organic polymer, and the first photoresist pattern includes a polymer including silicon.

The present invention provides a method for manufacturing the N-type TFT, which includes subjecting a light shielding layer to a grating like patternization treatment for controlling different zones of a poly-silicon layer to induce difference of crystallization so as to have different zones of the poly-silicon layer forming crystalline grains having different sizes, whereby through just one operation of ion doping, different zones of the poly-silicon layer have differences in electrical resistivity due to difference of grain size generated under the condition of identical doping concentration to provide an effect equivalent to an LDD structure for providing the TFT with a relatively low leakage current and improved reliability. Further, since only one operation of ion injection is involved, the manufacturing time and manufacturing cost can be saved, damages of the poly-silicon layer can be reduced, the activation time can be shortened, thereby facilitating the manufacture of flexible display devices.

A method of manufacturing a thin film transistor is disclosed. The method of manufacturing the thin film transistor includes: manufacturing a substrate; forming an oxide semiconductor layer on the substrate; forming a pattern including an active layer through a patterning process; forming a source and drain metal layer on the active layer; and forming a pattern including a source electrode and a drain electrode through a patterning process, an opening being formed between the source electrode and the drain electrode at a position corresponding to a region of the active layer used as a channel, wherein the step of forming the pattern including the source electrode and the drain electrode through a patterning process includes: removing a portion of the source and drain metal layer corresponding to the position of the opening through dry etching. The method may also be used to manufacturing a thin film transistor.

A method of forming image sensor packages may include performing a molding process. Mold material may be formed either on a transparent substrate in between image sensor dies, or on a removable panel in between transparent substrates attached to image sensor dies. Redistribution layers may be formed before or after the molding process. Mold material may be formed after forming redistribution layers so that the mold material covers the redistribution layers. In these cases, holes may be formed in the mold material to expose solder pads on the redistribution layers. Alternatively, redistribution layers may be formed after the molding process and the redistribution layers may extend over the mold material. Image sensor dies may be attached to a glass or notched glass substrate with dam structures. The methods of forming image sensor packages may result in hermetic image sensor packages that prevent exterior materials from reaching the image sensor.

A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.

A TFT and manufacturing method thereof, an array substrate and manufacturing method thereof, an X-ray detector and a display device are disclosed. The manufacturing method includes: forming a gate-insulating-layer thin film (3'), a semiconductor-layer thin film (4') and a passivation-shielding-layer thin film (5') successively; forming a pattern (5') that includes a passivation shielding layer through one patterning process, so that a portion, sheltered by the passivation shielding layer, of the semiconductor-layer thin film forms a pattern of an active layer (4a'); and performing an ion doping process to a portion, not sheltered by the passivation shielding layer, of the semiconductor-layer thin film to form a pattern comprising a source electrode (4c') and a drain electrode (4b'). The source electrode (4c') and the drain electrode (4b') are disposed on two sides of the active layer (4a') respectively and in a same layer as the active layer (4a'). The manufacturing method can reduce the number of patterning processes and improve the performance of the thin film transistor in the array substrate.

Manufacturing methods of JFET-type compact three-dimensional memory (3D-MC) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A JFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.

A method of forming a semiconductor device is provided such that a trench is formed in a semiconductor body at a first surface of the semiconductor body. Dopants are introduced into a first region at a bottom side of the trench by ion implantation. A filling material is formed in the trench. Dopants are introduced into a second region at a top side of the filling material. Thermal processing of the semiconductor body is carried out and is configured to intermix dopants from the first and the second regions by a diffusion process along a vertical direction perpendicular to the first surface.

A semiconductor device is provided that includes an n-type field effect transistor including a plurality of vertically stacked silicon-containing nanowires located in one region of a semiconductor substrate, and a p-type field effect transistor including a plurality of vertically stacked silicon germanium alloy nanowires located in another region of a semiconductor substrate. Each vertically stacked silicon-containing nanowire of the n-type field effect transistor has a different shape than the shape of each vertically stacked silicon germanium alloy nanowire of the p-type field effect transistor.

To provide a semiconductor device having improved reliability. After formation of an n+ type semiconductor region for source/drain, a first insulating film is formed on a semiconductor substrate so as to cover a gate electrode and a sidewall spacer. After heat treatment, a second insulating film is formed on the first insulating film and a resist pattern is formed on the second insulating film. Then, these insulating films are etched with the resist pattern as an etching mask. The resist pattern is removed, followed by wet washing treatment. A metal silicide layer is then formed by the salicide process.

A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.

A method for manufacturing an LDMOS device includes: providing a semiconductor substrate (200), forming a drift region (201) in the semiconductor substrate (200), forming a gate material layer on the semiconductor substrate (200), and forming a negative photoresist layer (204) on the gate material layer; patterning the negative photoresist layer (204), and etching the gate material layer by using the patterned negative photoresist layer (204) as a mask so as to form a gate (203); forming a photoresist layer having an opening on the semiconductor substrate (200) and the patterned negative photoresist layer (204), the opening corresponding to a predetermined position for forming a body region (206); and injecting the body region (206) by using the gate (203) and the negative photoresist layer (204) located above the gate (203) as a self-alignment layer, so as to form a channel region.

In some embodiments, a field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.

A method for producing an integrated power transistor circuit includes forming at least one transistor cell in a cell array, each transistor cell having a doped region formed in a semiconductor substrate and adjoining a first surface of the semiconductor substrate on a first side of the semiconductor substrate, depositing a contact layer on the first side, structuring the contact layer to form a contact structure from the contact layer, the contact structure having, in a projection of the cell array orthogonal to the first surface, a first section and, outside the cell array, a second section which connects the first section to an interface structure, and forming an electrode structure on and in direct contact with the first section in the orthogonal projection of the cell array, the electrode structure being absent outside the cell array.