A method and apparatus for distributing objects. In one embodiment, the method comprises computing a modulus operand based on a number of objects to be distributed and a number of objects pertaining to a first category; computing a modulus operation based on a number of distributed objects and the modulus operand; and distributing a first object or a second object based on a result of computing the modulus operation.

Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.

Systems and methods are provided for generating at least one high fidelity resource state. A classical code and punctured to provide a first set of generators and a second set of generators. The first set of generators is mapped to a set of stabilizer generators, and the second set of generators is mapped to a set of logical operators. A set of resource states are prepared in physical qubits. A decoding process is performed on the resource states according to a quantum code represented by the set of stabilizer generators and the set of logical operators, and qubits corresponding to the stabilizers are measured.

Apparatus comprising an input connected to receive an input signal, a lookup table comprising a plurality of input entries and first and second output entries for each input entry. The look up table receives the input signal and returns a lower input entry, an upper input entry, the second output entry for the lower input entry, and the first output entry for the upper input entry. A first subtractor subtracts the lower input entry from the input signal to produce a first difference. A second subtractor subtracts the input signal from the upper input entry to produce a second difference. First and second multipliers multiply the first and second differences by the first output entry for the upper input entry and the second output entry for the lower input entry, respectively, to produce first and second products. An adder adds the first and second products to produce an output signal.

A method for computer-implemented unit-conversion method, the method comprising identifying a first numerical value in a first system of units displayed on a computing device, converting the first numerical value in the first system of units into a second numerical value, and displaying the second numerical value and the second system of units on the computing device.

The generation of individual-specific information having a good reliability and uniqueness is made possible with a little circuit scale. For this purpose, in an individual-specific information generation apparatus, a plurality of digital circuits are in the same circuit configuration. Each of the digital circuits outputs a fixed or a random number output value individually without their output with respect to a certain input being determined unambiguously among the digital circuits. In each of the digital circuit, an order is defined in advance. A random number judgment unit judges whether the output value is a random value or fixed, for each of the plurality of digital circuits. An individual-specific information generation unit generates the individual-specific information based on information of the order defined in the digital circuit judged by the random number judgment unit as having a fixed output value among the plurality of digital circuits and the output value.

Disclosed is a processor that is able to efficiently execute DFT operations without having part of a basic operational circuit idle even during non-DFT-operation processing. The processor (1) has an operational means (operation unit) (2) and a control means (control unit) (3). The operation means (2) has a plurality of shift addition-and-subtraction means connected such that CORDIC (COordinate Rotation DIgital Computer) operations can be executed. The shift adding-and-subtracting means also execute shift addition-and-subtraction processing of butterfly operations that process shift addition-and-subtraction for one stage or more. The control means (3) instructs the operation means (2) to execute either CORDIC operations or butterfly operations, based on a plurality of data received from the outside.

A circuit arrangement and method couple a hardware-based pseudorandom number generator (PRNG) to an execution unit in such a manner that pseudorandom numbers generated by the PRNG may be selectively output to the execution unit for use as an operand during the execution of instructions by the execution unit. A PRNG may be coupled to an input of an operand multiplexer that outputs to an operand input of an execution unit so that operands provided by instructions supplied to the execution unit are selectively overridden with pseudorandom numbers generated by the PRNG. Furthermore, overridden operands provided by instructions supplied to the execution unit may be used as seed values for the PRNG.

A data collection unit obtains physiological data from a subject interface on a subject. The subject interface can be connected to the data collection unit. When the subject interface is connected to the data collection unit, subject interface contacts on the subject interface make contact with data collection unit contacts on the data collection unit. Some of the data collection unit contacts are for communicating physiological data from the subject interface to the data collection unit. Some of the contacts are for powering the data collection unit upon the subject interface being connected to the data collection unit and for powering down the data collection unit upon the subject interface being disconnected from the data collection unit.

An independently functioning or centrally controlled wall light switch is configured to operate in normal mode and a Jewish holiday mode wherein the state of the light is fixed, regardless of the user's physical manipulation of the light switch. The control system automatically activates holiday mode by combining a geographically determined Jewish religious clock executed by software and hardware that utilizes the current time, date and geographical location of the apparatus in accordance with the Jewish definition of time and laws for calculating numerous religiously significant shifting daily points in time. The control system further incorporates several energy saving and preference modes by utilizing a particular day's calculated religious points in time in conjunction with holiday behavior patterns common to most Jewish families to provide the user with a greatly simplified means of programming an automatically adjusting on/off light timer and dimming overlay functionality during holiday mode.

Memory system operations are extended for a data processor by DMA, cache, or memory controller to include a DMA descriptor, including a set of operations and parameters for the operations, which provides for data compression and decompression during or in conjunction with processes for moving data between memory elements of the memory system. The set of operations can be configured to use the parameters and perform the operations of the DMA, cache, or memory controller. The DMA, cache, or memory controller can support moves between memory having a first access latency, such as memory integrated on the same chip as a processor core, and memory having a second access latency that is longer than the first access latency, such as memory on a different integrated circuit than the processor core.

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

In accordance with one or more aspects, an initial output string is generated by a random number generator. The initial output string is sent to a random number service, and an indication of failure is received from the random number service if the initial output string is the same as a previous initial output string received by the random number service. Operation of the device is ceased in response to the indication of failure. Additionally, entropy estimates for hash values of an entropy source can be generated by an entropy estimation service based on hash values of various entropy source values received by the entropy estimation service. The hash values can be incorporated into an entropy pool of the device, and the entropy estimate of the pool being updated based on the estimated entropy of the entropy source.

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit. The data detector circuit includes an anti-causal noise predictive filter circuit and a data detection circuit. In some cases, the anti-causal noise predictive filter circuit is operable to apply noise predictive filtering to a detector input to yield a filtered output, and the data detection circuit is operable to apply a data detection algorithm to the filtered output derived from the anti-causal noise predictive filter circuit.

Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

A random number generation method and apparatus using a low-power microprocessor is provided. In the random number generation method, a low-power microprocessor determines whether external power is supplied to a random number generator. The low-power microprocessor updates an internal state of the random number generator based on a first scheme if it is determined that the external power is supplied to the random number generator. The low-power microprocessor updates the internal state of the random number generator based on a second scheme different from the first scheme if it is determined that the external power is not supplied to the random number generator.

Apparatus and method for processing linear systems of equations and finding a n×1 vector x satisfying Ax=b where A is a symmetric, positive-definite n×n matrix corresponding to n×n predefined high-precision elements and b is an n1 vector corresponding to n predefined high-precision elements. A first iterative process generates n low-precision elements corresponding to an n×1 vector xl satisfying Alxl=bl where Al, bl are elements in low precision. The elements are converted to high-precision data elements to obtain a current solution vector x. A second iterative process generates n low-precision data elements corresponding to an n×1 correction vector dependent on the difference between the vector b and the vector product Ax. Then there is produced from the n low-precision data elements of the correction vector respective high-precision data elements of an n×1 update vector u. The data elements of the current solution vector x are updated such that x=x+u.

Distributed processing system and method for discrete logarithm calculation. The speed and resource efficiency of discrete logarithm calculation may be improved by allowing a plurality of operation agents to distributively process an operation of generating a modulo multiplication auxiliary table, an operation of generating a pre-calculation table, and an operation of searching for an answer by applying an iterated function for discrete logarithm calculation in a discrete logarithm calculation operation using the pre-calculation table.

A communication device includes a storage unit to store quotients and remainders associated with multiplication values obtained by multiplying a specified integer number, which is expressed in a form of (2β+α) where β is a positive integer number and α is a positive integer number other than integral multiples of 2, respectively, the quotients and the remainders being obtained by dividing the multiplication values by 2β, respectively, a first unit to divide a dividend by 2βand calculate a quotient and a remainder, a second unit to obtain a quotient, which corresponds to the remainder from the storage unit, and a third unit to determine that the data length of the packet data is normal, when a combination of the quotient and the remainder calculated by the first unit is in the storage unit.

Systems, devices, processors, and methods are described which may be used for the reception of a wireless broadband signal at a user terminal from a gateway via a satellite. A wireless signal may include a series of physical layer frames, each frame including a physical layer header and payload. The received signal is digitized and processed using various novel physical layer headers and related techniques to synchronize the physical layer frames and recover data from physical layer headers for purposes of demodulation and decoding.

A function f(x) is calculated with a calculating apparatus that makes a correct calculation with a low probability. Provided that G and H are cyclic groups, f is a function that maps an element x of the group H into the group G, X1 and X2 are random variables whose values are elements of the group G, x1 is a realized value of the random variable X1, and x2 is a realized value of the random variable X2, an integer calculation part calculates integers a' and b' that satisfy a relation a'a+b'b=1 using two natural numbers a and b that are relatively prime. A first randomizable sampler is capable of calculating f(x)bx1 and designates the calculation result as u. A first exponentiation part calculates u'=ua. A second randomizable sampler is capable of calculating f(x)ax2 and designates the calculation result as v. A second exponentiation part calculates v'=vb. A determining part determines whether u'=v' or not. A final calculation part calculates ub'va' in a case where it is determined that u'=v'.

The disclosure is related systems and methods for using operation durations of a data storage medium to generate random numbers. In one embodiment, a device may comprise a random number generator circuit configured to store a value representing a duration of an operation on the data storage medium, and generate a random number based on the value. Another embodiment may be a method comprising recording durations of access operations to a data storage medium, and generating a random number based on the durations.

A method is provided for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth. The method applies the digital signal input samples to a (M−1) stage tapped delay line, downsamples the input samples and the output samples of each tapped delay line stage by a factor of M, and applies each of the M downsampled sample value streams to M allpass IIR filters, respectively. The M allpass IIR filtered sample streams are then summed and scaled by a factor of 1/M. The result can then be filtered by a digital channel filter.

A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

A system (200) and a method (100) of operating a computing device to perform memoization are disclosed. The method includes determining whether a result of a function is stored in a cache and, if so, retrieving the result from the cache and, if not, calculating the result and storing it in the cache. The method (100) includes transforming (104) by the computing device at least one selected from the input parameters and the output parameters of the function, the transforming being based on an analysis of the function and its input arguments to establish whether or not there is a possible relationship reflecting redundancy among the input parameters and output parameters of the function. The transforming may include at least one of: use of symmetry, scaling, linear shift, interchanging of variables, inversion, polynomial and/or trigonometric transformations, spectral or logical transformations, fuzzy transformations, and systematic arrangement of parameters.

Devices, systems, methods, and other embodiments associated with generating a moving average are described. In one embodiment, a method includes inputting a new data value, wherein the new data value is a most recent data value in a series of M prior sequential data values that are input to an accumulator for the purpose of calculating a moving average having a window size of M. The method also includes detecting an error in the new data value and correcting the moving average, based at least in part, on the error.

A method of generating a code sequence in a wireless communication system is disclosed. More specifically, the method includes recognizing a desired length of the code sequence, generating a code sequence having a length different from the desired length, and modifying the length of the generated code sequence to equal the desired length. Here, the step of modifying includes discarding at least one element of the generated code sequence or inserting at least one null element to the generated code sequence.

A method for generating multi-level (or multi-bit) pseudo-random sequences is disclosed. This embodiment relates to communication systems, and more particularly to generating multi-level pseudo random symbol sequence. Present day systems do not employ effective mechanisms for generation of multi level PRBS in order to increase the data communication rates. Further, these systems do not cover all the possible transitions for the outputs of the system. The proposed system employs mechanisms in order to generate PRBS signals for producing multi levels signals to the electronic components. The mechanism employs alternate bit tapping techniques. In the alternate bit tapping technique, bits are tapped alternatively to determine the current state and the next state of the system. In addition, the mechanism also covers all the possible states of the output vector with transitions between the output states. This ensures that high data rates are obtained for a given bandwidth of operation.

Examples disclose a computing system comprising a computing device with a display surface to detect a selection of functionality from a list of functionalities to be disabled on a calculator. Further, the computing device creates a custom configuration based on the selected functionality. Additionally, the examples also disclose a calculator with a processor to integrate the custom configuration, the custom configuration restricts the selected functionality on the calculator.

A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal.

A method and apparatus may be used to evaluate a polynomial by initializing a multiply and accumulate feedback apparatus (260) comprising a multiplier stage (264) having an output coupled to an input of an accumulator stage (267) having an accumulator feedback output (269) selectively coupled to an input of the multiplier stage over a plurality of clock cycles; iteratively calculating a final working loop variable z over an additional plurality of clock cycles; multiplying the final working loop variable z and a complex input vector x to compute a final multiplier value; and adding a least significant complex polynomial coefficient to the final multiplier value using the multiplier stage of the multiply and accumulate feedback apparatus to yield a result of the polynomial evaluation.

A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

A data processing apparatus is provided for producing a randomized value. A cell in the data processing apparatus comprises a dielectric oxide layer and stress voltage circuitry is configured to apply a stress voltage across the dielectric oxide layer of the cell to cause an oxide breakdown process to occur. Oxide breakdown detection circuitry is configured to determine a current extent of the oxide breakdown process by measuring a response of the dielectric oxide layer to the stress voltage and randomized value determination circuitry is configured to determine a randomized value in dependence on the current extent of the oxide breakdown process.

The present invention provides a polymerization reactor for producing a super absorbent polymer comprising: a reaction unit; a monomer composition supply unit being connected to the reaction unit and supplying a monomer composition solution containing a monomer, a photoinitiator, and a solvent; an agitating shaft extended in the reaction unit from one end of the reaction unit connected to the monomer composition supply unit to the other end of the reaction unit; a plurality of agitating blades installed around the agitating shaft; and a light irradiation unit providing light to the monomer composition solution furnished from the monomer composition supply unit, and a method of producing super absorbent polymers by using the same.

The invention provides a method for the manufacture of a catheter comprising a hydrophilic gel. The method comprising the steps of combining a polymeric photoinitiator of the general formula (I): R1(A1)r-(R2(A2)m-O)o—(R3(A3)n-O)p—R4(A4)s (I) with one or more gel-forming polymers and/or gel-forming monomers to form a matrix composition, curing the matrix composition by exposing it to UV radiation, exposing the matrix composition to a swelling medium and incorporating the hydrophilic gel into a catheter. The invention also provides autocuring of the polymeric photoinitiator (I) to provide a gel precursor, a hydrophilic gel and a catheter comprising or coated with the hydrophilic gel of the invention.

Described is a radiation-crosslinkable hotmelt adhesive comprising at least one radiation-crosslinkable poly(meth)acrylate formed to an extent of at least 60% by weight of C1 to C10 alkyl(meth)acrylates and at least one oligo(meth)acrylate which comprises nonacrylic C C double bonds and has a K value of less than or equal to 20. The hotmelt adhesive comprises a photoinitiator which may be present in the form of an additive not attached to the poly(meth)acrylate and/or not attached to the oligo(meth)acrylate, may be incorporated by copolymerization into the poly(meth)acrylate, and/or may be attached to the oligo(meth)acrylate. The hotmelt adhesive can be used for producing adhesive tapes.

The active ray-curable inkjet ink comprises a gelling agent, photopolymerizable compounds and a photoinitiator, and reversibly transitions into a sol-gel phase according to the temperature. Therein: (1) a (meth)acrylate compound having a molecular weight of 300-1,500 and having 3-14 (—CH2—CH2—O—) structural units within a molecule is included as the first photopolymerizable compound at a proportion of 30-70 mass % relative to the total mass of the ink; (2) a (meth)acrylate compound having a molecular weight of 300-1,500 and a C log P value of 4.0-7.0 is included as the second photopolymerizable compound at a proportion of 10-40 mass % relative to the total mass of the ink; and (3) the gelling agent has a total of at least 12 carbon atoms, and has a straight or branched alkyl chain including at least three carbon atoms.

The present invention relates to methods for making oxidation resistant homogenized polymeric materials and medical implants that comprise polymeric materials, for example, ultra-high molecular weight polyethylene (UHMWPE). The invention also provides methods of making antioxidant-doped medical implants, for example, doping of medical devices containing cross-linked UHMWPE with vitamin E by diffusion and annealing the anti-oxidant doped UHMWPE in a super critical fluid, and materials used therein.

A durable ambient light curable waterproof liquid rubber coating with volatile organic compound (VOC) content of less than 450 grams per liter made from ethylene propylene diene terpolymer (EPDM) in a solvent, a photoinitiator, an additive, pigments, and fillers, and a co-agent and a method for making the formulation, wherein the formulation is devoid of thermally activated accelerators.

A durable ambient light curable waterproof liquid rubber coating with volatile organic compound (VOC) content of less than 450 grams per liter made from ethylene propylene diene terpolymer (EPDM) in a solvent, a photoinitiator, an additive, pigments, and fillers, and a co-agent and a method for making the formulation, wherein the formulation is devoid of thermally activated accelerators.

A crosslinkable curing super-branched polyester and the cured product and the preparation method thereof are disclosed. The super-branched polyester has high refractive index and comprises a compound represented by the following structural formula (I). In the formula (I), HBP is the backbone of the super-branched polyester; both a and b are positive integers; the sum of a and b is less than or equal to n; n is more than or equal to 10 and less than 80. In the super-branched polyester, A is represented by formula (II) and N is represented by formula (III), wherein R is methyl or hydrogen atom; the mole ratio of N relative to the total mole of A and N is more than 30 mol %, and the ratio of the total mole of A and N relative to the product of the total mole of HBP backbone and n is more than 0.5 and less than or equal to 1.

The invention relates to a radiation curable composition for taking a dental impression comprising (A) a cationically hardenable compound comprising at least one aziridine moiety, and (B) a radiation sensitive starter, the radiation sensitive starter comprising an onium salt, a ferrocenium salt, a combination or mixture thereof.

A process for the preparation of polymer lattices comprising polymer nanoparticles by a photo-initiated heterophase polymerization includes preparing a heterophase medium comprising a dispersed phase and a continuous phase and at least one of at least one surfactant, at least one photoinitiator, and at least one polymerizable monomer. The at least one polymerizable monomer is polymerized by irradiating the heterophase medium with electromagnetic radiation so as to induce a generation of radicals. The at least one photoinitiator is selected from compounds comprising at least one phosphorous oxide group (P═O) or at least one phosphorous sulfide (P═S) group. The irradiating of the heterophase medium is effected so that a ratio of an irradiated surface of the heterophase medium to a volume of the heterophase medium is at least 200 m−1.

A radiation curable temporary laminating adhesive composition for use in temperature applications at 150° C. or greater, and typically at 200° C. or greater, comprises (A) a hydrogenated polybutadiene diacrylate; (B) a radical photoinitiator; and (C) a diluent.

A process for the preparation of modified polymers by a photo-initiated polymerization includes preparing a polymerization medium comprising at least one photoinitiator comprising at least one phosphorous oxide (P═O) group or at least one phosphorous sulfide (P═S) group, and at least one polymerizable monomer. The at least one polymerizable monomer is polymerized by irradiating the polymerization medium with electromagnetic radiation so as to induce a generation of radicals so as to obtain a polymer. The polymer is modified by irradiating the polymer with electromagnetic radiation so as to induce a generation of radicals from the polymer in a presence of at least one modifying agent.

A photocurable material for sealing including (A) an oligomer having a weight average molecular weight of 10,000 to 30,000 and having (meth)acryloyl group(s), (B) a (meth)acrylate monomer, (C) a polythiol compound, and optionally (D) a carbodiimide compound enables the provision of a sealing material that has high compression recovery performance, high tensile strength and excellent flexibility, can have low hardness if required, and therefore has excellent sealing properties including air-tightness performance and water-proof performance and undergoes the formation of little surface tacks and the like.