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Cerium containing nanoparticles prepared in non-polar solvent

A method of making cerium-containing metal oxide nanoparticles in non-polar solvent eliminates the need for solvent shifting steps. The direct synthesis method involves: (a) forming a reaction mixture of a source of cerous ion and a carboxylic acid, and optionally, a hydrocarbon solvent; and optionally further comprises a non-cerous metal ion; (b) heating the reaction mixture to oxidize cerous ion to ceric ion; and (c) recovering a nanoparticle of either cerium oxide or a mixed metal oxide comprising cerium. The cerium-containing oxide nanoparticles thus obtained have cubic fluorite crystal structure and a geometric diameter in the range of about 1 nanometer to about 20 nanometers. Dispersions of cerium-containing oxide nanoparticles prepared by this method can be used as a component of a fuel or lubricant additive.




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Methods for producing a dispersion containing silicon dioxide particles and cationization agent

Process for preparing a dispersion comprising silicon dioxide particles and cationizing agents, by dispersing 50 to 75 parts by weight of water, 25 to 50 parts by weight of silicon dioxide particles having a BET surface area of 30 to 500 m2/g and 100 to 300 μg of cationizing agent per square meter of the BET surface area of the silicon dioxide particles, wherein the cationizing agent is obtainable by reacting at least one haloalkyl-functional alkoxysilane, hydrolysis products, condensation products and/or mixtures thereof with at least one aminoalcohol and water; and optionally removing the resulting hydrolysis alcohol from the reaction mixture. Also the process for preparing the dispersion, wherein the cationizing agent comprises one or more quaternary, aminoalcohol-functional, organosilicon compounds of formula III and/or condensation products thereof, wherein Ru and Rv are independently C2-4 alkyl group, m is 2-5 and n is 2-5.




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Foams of graphene, method of making and materials made thereof

Method for making a liquid foam from graphene. The method includes preparing an aqueous dispersion of graphene oxide and adding a water miscible compound to the aqueous dispersion to produce a mixture including a modified form of graphene oxide. A second immiscible fluid (a gas or a liquid) with or without a surfactant are added to the mixture and agitated to form a fluid/water composite wherein the modified form of graphene oxide aggregates at the interfaces between the fluid and water to form either a closed or open cell foam. The modified form of graphene oxide is the foaming agent.




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Aqueous delivery system for low surface energy structures

An aqueous delivery system is described including at least one surfactant and at least one water insoluble wetting agent. Further described are low surface energy substrates, such as microporous polytetrafluoroethylene, coated with such an aqueous solution so as to impart a change in at least one surface characteristic compared to the surface characteristics of the uncoated low surface energy substrate.




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Defoaming agent

The present invention is a defoaming agent comprising a fatty acid amide (A), a base oil (B) that is liquid at 25° C., an oil thickening agent (C), and a surfactant (D), wherein the content of the fatty acid amide (A) is 1 to 10% by weight, the content of the base oil (B) that is liquid at 25° C. is 71 to 97.9% by weight, the content of the oil thickening agent (C) is 0.1 to 10% by weight, and the content of the surfactant (D) is 1 to 9% by weight based on the weight of the fatty acid amide (A), the base oil (B) that is liquid at 25° C., the oil thickening agent (C), and the surfactant (D), and the viscosity (25° C.) at a shear rate of 1000 s−1 is 0.1 to 1.0 Pa·s.




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Defoamer for fermentation

Provided is a defoamer for fermentation which has excellent dispersibility in water and forms neither a precipitate nor oil droplets when the dispersion is heated, and which is highly effective in defoaming fermentation media. This defoamer contains a reaction product obtained by mixing a fat or oil having an iodine value of 40 to 130 with glycerin or like in a molar ratio of from 3/2 to 1/2 to obtain a mixture, causing 4 to 17 mol of propylene oxide to add to 1 mol of the mixture, and then causing 20 to 40 mol of ethylene oxide and 70 to 110 mol of propylene oxide to block-wise add thereto in this order, the reaction product having an ethylene oxide/propylene oxide molar ratio of from 1/4 to 2/5.




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Low latency variable transfer network communicating variable written to source processing core variable register allocated to destination thread to destination processing core variable register allocated to source thread

A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.




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Implementation of multi-tasking on a digital signal processor with a hardware stack

The disclosure relates to the implementation of multi-tasking on a digital signal processor. Blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which instead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. Whilst the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.




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APC model extension using existing APC models

A method of extending advanced process control (APC) models includes constructing an APC model table including APC model parameters of a plurality of products and a plurality of work stations. The APC model table includes empty cells and cells filled with existing APC model parameters. Average APC model parameters of the existing APC model parameters are calculated, and filled into the empty cells as initial values. An iterative calculation is performed to update the empty cells with updated values.




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Client-allocatable bandwidth pools

Methods and apparatus for client-allocatable bandwidth pools are disclosed. A system includes a plurality of resources of a provider network and a resource manager. In response to a determination to accept a bandwidth pool creation request from a client for a resource group, where the resource group comprises a plurality of resources allocated to the client, the resource manager stores an indication of a total network traffic rate limit of the resource group. In response to a bandwidth allocation request from the client to allocate a specified portion of the total network traffic rate limit to a particular resource of the resource group, the resource manager initiates one or more configuration changes to allow network transmissions within one or more network links of the provider network accessible from the particular resource at a rate up to the specified portion.




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Method and device for passing parameters between processors

The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced. The disclosure reduces the cycle delay of the slave processor in accessing the dual-port RAM and the register, thereby effectively reducing the dynamic power consumption of the chip, improving the processing capability of the slave processor and enhancing the effective performance of the slave processor.




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Active memory command engine and method

A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored.




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Efficient conditional ALU instruction in read-port limited register file microprocessor

A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result. To execute the second microinstruction, it writes the destination register with the result generated by the first microinstruction if the architectural condition flags satisfy the condition, and writes the destination register with the current value of the destination register if the architectural condition flags do not satisfy the condition.




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Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels

A hypervisor and one or more guest operating systems resident in a data processing system and hosted by the hypervisor are configured to selectively enable or disable branch prediction logic through separate hypervisor-mode and guest-mode instructions. By doing so, different branch prediction strategies may be employed for different operating systems and user applications hosted thereby to provide finer grained optimization of the branch prediction logic for different operating scenarios.




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Efficient parallel computation of dependency problems

A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.




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Method and system for managing hardware resources to implement system functions using an adaptive computing architecture

An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.




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System and method for communicating with sensors/loggers in integrated radio frequency identification (RFID) tags

A system and method is disclosed for communicating with sensors/loggers in integrated radio frequency identification (RFID) tags. An RFID reader uses a Communicate With Data Logger Command to communicate with a data logger in an RFID tag. The RFID reader performs data access processes using an Index Register and a Data Register of the RFID tag. The RFID reader selects one of (1) Index Read access (2) Index Write access (3) Data Write access (4) Data Read access with parity and (5) Data Read access with cyclic redundancy check (CRC). The RFID tag performs the requested data access and then performs an error detection process.




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Reception according to a data transfer protocol of data directed to any of a plurality of destination entities

A data processing system arranged for receiving over a network, according to a data transfer protocol, data directed to any of a plurality of destination identities, the data processing system comprising: data storage for storing data received over the network; and a first processing arrangement for performing processing in accordance with the data transfer protocol on received data in the data storage, for making the received data available to respective destination identities; and a response former arranged for: receiving a message requesting a response indicating the availability of received data to each of a group of destination identities; and forming such a response; wherein the system is arranged to, in dependence on receiving the said message.




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Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)

A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.




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Storing in other queue when reservation station instruction queue reserved for immediate source operand instruction execution unit is full

A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing apparatus also includes another execution unit which performs computation on two operand inputs, one of which is selectable between read data from a register and an immediate value, and the other of which is an immediate value. A control unit determines, based on a received instruction specifying a computation on two operands, whether each of the two operands specifies read data from a register or an immediate value. Depending on the determination result, the control unit causes one of the execution units to execute the computation specified by the received instruction.




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Generating hardware events via the instruction stream for microprocessor verification

A processor receives an instruction operation (OP) code from a verification system. The instruction OP code includes instruction bits and forced event bits. The processor identifies a forced event based upon the forced event bits, which is unrelated to an instruction that corresponds to the instruction bits. In turn, the processor executes the forced event.




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Dynamic energy savings for digital signal processor modules using plural energy savings states

In an example embodiment, there is described herein an apparatus comprising an interface for communicating with a plurality of digital signal processors and logic operable to send and receive data via the interface. The logic is configured to determine a first set of digital signal processors to be maintained in a ready state, a second set of digital signal processors to be maintained in a first energy saving state, and a third set of digital signal processors to be maintained in a second energy saving state.




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Automatic WSDL download of client emulation for a testing tool

A method is disclosed which may include analyzing communication requests in a business process between a client and a server offering a service application to be tested. The method may further include identifying a call to a web service in the analyzed communication. The method may also include determining a location of a Web Service Description Language (WSDL) file relating to the web service on a remote server and downloading the WSDL file from the determined location. A computer readable medium having stored thereon instructions for performing the method and a computer system are also disclosed.




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Framework for facilitating implementation of multi-tenant SaaS architecture

A framework for implementing multitenant architecture is provided. The framework comprises a framework services module which is configured to provide framework services that facilitate abstraction of Software-as-a-Service (SaaS) services and crosscutting services for a Greenfield application and a non SaaS based web application. Further the abstraction results in a SaaS based multitenant web application. The framework further comprises a runtime module configured to automatically integrate and consume the framework services and APIs to facilitate monitoring and controlling of features associated with the SaaS based multitenant web application. The framework further comprises a metadata services module configured to provide a plurality of metadata services to facilitate abstraction of storage structure of metadata associated with the framework and act as APIs for managing the metadata. The framework further comprises a role based administration module that facilitates management of the metadata through a tenant administrator and a product administrator.




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Enhanced instruction scheduling during compilation of high level source code for improved executable code

Systems and methods for static code scheduling are disclosed. A method can include receiving an intermediate representation of source code, building a directed acyclic graph (DAG) for the intermediate representation, and creating chains of dependent instructions from the DAG for cluster formation. The chains are merged into clusters and each node in the DAG is marked with an identifier of a cluster it is part of to generate a marked instruction DAG. Instruction DAG scheduling is then performed using information about the clusters to generate an ordered intermediate representation of the source code.




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Systems and methods for monitoring product development

A computer-implemented method is provided for evaluating team performance in a product development environment. The method includes receiving a plurality of points of effort made by a team over a plurality of days in a time period, computing a slope associated with a line of best fit through the plurality of points of effort over the plurality of days, computing a deviation of the slope from an ideal slope corresponding to a desired performance rate for the team, and generating a display illustrating at least one of the slope, the ideal slope or the deviation.




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Conducting verification in event processing applications using formal methods

A method of applying formal verification methodologies to event processing applications is provided herein. The method includes the following stages: representing an event processing application as an event processing network, being a graph with event processing agents as nodes; generating a finite state machine based on the event processing network, wherein the finite state machine is an over-approximation of the event processing application; expressing stateful rules and policies that are associated with the event processing application using temporal logic, to yield a temporal representation of the event processing application; combining the temporal representation and the finite state machine into a model; generating a statement associated with a user-selected verification-related property of the event processing application, wherein the statement is generated using the temporal representation; and applying the statement to the model, to yield an indication for: (i) a correctness of the statement or (ii) a counter example, respectively.




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Applying coding standards in graphical programming environments

Graphical programming or modeling environments in which a coding standard can be applied to graphical programs or models are disclosed. The present invention provides mechanisms for applying the coding standard to graphical programs/models in the graphical programming/modeling environments. The mechanisms may detect violations of the coding standard in the graphical model and report such violations to the users. The mechanisms may automatically correct the graphical model to remove the violations from the graphical model. The mechanisms may also automatically avoid the violations in the simulation and/or code generation of the graphical model.




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Unified and extensible asynchronous and synchronous cancelation

A cancelation registry provides a cancelation interface whose implementation registers cancelable items such as synchronous operations, asynchronous operations, type instances, and transactions. Items may be implicitly or explicitly registered with the cancelation registry. A consistent cancelation interface unifies cancelation management for heterogeneous items, and allows cancelation of a group of items with a single invocation of a cancel-registered-items procedure.




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Automated generation of two-tier mobile applications

The disclosure generally describes computer-implemented methods, software, and systems for creating and using two-tier mobile applications. A computer-implemented method includes identifying at least a portion of a database to be associated with a mobile application, retrieving a set of metadata associated with the at least a portion of the identified database, automatically generating a set of mobile application source code for directly accessing the at least a portion of the database based on the set of retrieved metadata, and compiling the set of mobile application source code into a distributable mobile application, the distributable mobile application configured to directly access the identified database associated with the mobile application. In some instances, the identifying, retrieving, generating, and compiling operations are performed at design time, while at runtime, the mobile application is executable by a mobile device and, during runtime execution, can request database-related information directly from the identified database.




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Methods and devices for managing a cloud computing environment

Methods, devices, and systems for management of a cloud computing environment for use by a software application. The cloud computing environment may be an N-tier environment. Multiple cloud providers may be used to provide the cloud computing environment.




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System for selecting software components based on a degree of coherence

Disclosed is a novel system and method to select software components. A set of available software components are accessed. Next, one or more dimensions are defined. Each dimension is an attribute to the set of available software components. A set of coherence distances between each pair of the available software components in the set of available software components is calculated for each of the dimensions that have been defined. Each of the coherence distances are combined between each pair of the available software components that has been calculated in the set of the coherence distances into an overall coherence degree for each of the available software components. Using the overall coherence degree, one or more software components are selected to be included in a software bundle.




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System and method for recommending software artifacts

A method for recommending at least one artifact to an artifact user is described. The method includes obtaining user characteristic information reflecting preferences, particular to the artifact user, as to a desired artifact. The method also includes obtaining first metadata about each of one or more candidate artifacts, and scoring, as one or more scored artifacts, each of the one or more candidate artifacts by evaluating one or more criteria, not particular to the artifact user, applied to the first metadata. The method further includes scaling, as one or more scaled artifacts, a score of each of the one or more scored artifacts, by evaluating the suitability of each of the one or more scored artifacts in view of the user characteristic information. The method lastly includes recommending to the artifact user at least one artifact from among the one or more scaled artifacts based on its scaled score.




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Custom code lifecycle management

A method is provided to manage program code that runs in a computer system comprising: producing a management information structure that identifies a managed system within the computer system; producing a master object definition information structure that provides a mapping between master objects and corresponding managed code objects that run in the computer system; and requesting extraction of information from the managed system identified by the master information structure that relates to managed code objects that the object definition information structure maps to master objects.




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Compound versioning and identification scheme for composite application development

The present invention provides a method, a system and a computer program product for defining a version identifier of a service component. The method includes determining various specification levels corresponding to the service component. Thereafter, the determined specification levels are integrated according to a predefined hierarchy to obtain the version identifier of the service component. The present invention also enables the identification of the service components. The service components are identified from one or more service components on the basis of one or more user requirements.




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Identifying differences between source codes of different versions of a software when each source code is organized using incorporated files

An aspect of the present invention identifies differences between source codes (e.g. of different versions of a software), when each source code is organized using incorporated files. In one embodiment, in response to receiving identifiers of a first and second source codes (each source code being organized as a corresponding set of code files), listings of the instructions in the first and second source codes are constructed. Each listing is constructed, for example, by replacing each incorporate statement in the source code with instructions stored in a corresponding one of code files. The differences between the first and second source codes are then found by comparing the constructed listings of instructions.




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System for generating readable and meaningful descriptions of stream processing source code

An information processing system, computer readable storage medium, and method for automatically generating human readable and meaningful documentation for one or more source code files. A processor of the information processing system receives one or more source code files containing source code artifacts (SCA) and infers semantics therefrom based on predefined rules. The processor, based on the inferred semantics, extracts documentation from another source code file. The extracted documentation and the inferred semantics are used to generate new human readable and meaningful documentation for the SCA, such new documentation being previously missing from the SCA. The generated new documentation is included with the SCA in one or more source code files.




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System and method for generating software unit tests simultaneously with API documentation

A system and method may generate unit tests for source code concurrently with API documentation. The system may receive a source code file including several comments sections. Each comments section may include a description of a source code unit such as a class, method, member variable, etc. The description may also correspond to input and output parameters the source code unit. The system and method may parsing the source code file to determine a source code function type corresponding to the unit description and copy the unit description to a unit test stub corresponding to the function type. A developer or another module may then complete the unit test stub to transform each stub into a complete unit test corresponding to the source code unit. Additionally, the system and method may execute the unit test and generate a test result indication for each unit test.




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Simultaneously targeting multiple homogeneous and heterogeneous runtime environments

A single software project in an integrated development environment (IDE) may be built for multiple target environments in a single build episode. Multiple different output artifacts may be generated by the build process for each of the target environments. The output artifacts are then deployed to the target environments, which may be homogeneous or heterogeneous environments. The same source project may be used to generate multiple output artifacts for the same target environment.




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Release management system for a multi-node application

A deployment system provides the ability to deploy a multi-node distributed application, such as a cloud computing platform application that has a plurality of interconnected nodes performing specialized jobs. The deployment system includes a release management system that builds and manages versioned releases of application services and/or software modules that are executed by the plurality of nodes of the cloud computing platform application. The release management system utilizes specification files to define a jobs and application packages and configurations needed to perform the jobs. The jobs and application packages are assembled into a self-contained release bundle that may be provided to the deployment system. The deployment system unwraps the release bundle and provides each job to deployment agents executing on VMs. The deployment agents apply the jobs to their respective VM (e.g., launching applications), thereby deploying the cloud computing platform application.




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System and method for efficient compilation and invocation of function type calls

A system and method for efficient compilation and invocation of function type calls in a virtual machine (VM), or other runtime environment, and particularly for use in a system that includes a Java Virtual Machine (JVM). In accordance with an embodiment, the system comprises a virtual machine for executing a software application; a memory space for the application byte code comprising callsites generated using a function type carrier; a bytecode to machine code compiler which performs MethodHandle invocation optimizations; a memory space for the compiled machine code; and a memory space for storing software objects as part of the software application. The system enables carrying the function type from the original MethodHandle to a callsite in the generated bytecode, including maintaining generics information for a function type acquired from a target function, and generating a callsite based on the generics information for the function object invocation.




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Optimization of loops and data flow sections in multi-core processor environment

The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.




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Program module applicability analyzer for software development and testing for multi-processor environments

In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.




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Method for identifying problematic loops in an application and devices thereof

This invention relates to a method, computer readable medium, and apparatus for identifying one or more problematic loops in an application. This invention provides a Directed Acyclic Graph or DAG representation of structure of one or more loops in the application by performing a static and a dynamic analysis of the application source code and depicts the loop information as LoopID, loop weight, total loop iteration, average loop iteration, total loop iteration time, average loop iteration time and embedded vector size. This aids a programmer to concentrate on problematic loops in the application and analyze them further for potential parallelism.




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Transferring files to a baseboard management controller (‘BMC’) in a computing system

Transferring files to a baseboard management controller (‘BMC’) in a computing system, including: receiving, by the BMC, a request to initiate an update of the computing system; identifying, by the BMC, an area in memory within the computing system for storing an update file; and transmitting, by the BMC, a request to register the BMC as a virtual memory device.




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Transferring files to a baseboard management controller (‘bmc’) in a computing system

Transferring files to a baseboard management controller (‘BMC’) in a computing system, including: receiving, by the BMC, a request to initiate an update of the computing system; identifying, by the BMC, an area in memory within the computing system for storing an update file; and transmitting, by the BMC, a request to register the BMC as a virtual memory device.




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Algorithm for automated enterprise deployments

A method of automating the deployment of a number of enterprise applications on one or more computer data processing systems. Each enterprise application or update is stored in a dynamic distribution directory and is provided with identifying indicia, such as stage information, target information, and settings information. When automated enterprise deployment is invoked, computer instructions in a computer readable medium provide for initializing deployment, performing deployment, and finalizing deployment of the enterprise applications or updates.




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Generic download and upload functionality in a client/server web application architecture

The present invention relates generally to client-server architectures for allowing generic upload and download functionality between a web application at a server and a client. One exemplary method includes sending a download/upload request to a web application at the server, where the download/upload request specifies at least one file to download/upload; receiving a transmission from the server; parsing the transmission to identify a download/upload command and an associated download/upload manifest, where the download/upload manifest includes executable code that, when executed on the client, will perform the download/upload of the at least one file.




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Blueprint-driven environment template creation in a virtual infrastructure

A system for blueprint-driven environment template creation in a virtual infrastructure comprises a processor and a memory. The processor is configured to receive a blueprint, receive an environment template configuration, and build an environment template using the blueprint and the environment template configuration. The environment template is for provisioning an environment. The environment is for deploying an application. The memory is coupled to the processor and is configured to provide the processor with instructions.




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Adjustment of threads for execution based on over-utilization of a domain in a multi-processor system by destroying parallizable group of threads in sub-domains

Embodiments provide various techniques for dynamic adjustment of a number of threads for execution in any domain based on domain utilizations. In a multiprocessor system, the utilization for each domain is monitored. If a utilization of any of these domains changes, then the number of threads for each of the domains determined for execution may also be adjusted to adapt to the change.