Methods and apparatus are provided for evaluating potential resource capacity in a system where there is elasticity and competition between a plurality of containers. A dynamic potential capacity is determined for at least one container in a plurality of containers competing for a total capacity of a larger container. A current utilization by each of the plurality of competing containers is obtained, and an equilibrium capacity is determined for each of the competing containers. The equilibrium capacity indicates a capacity that the corresponding container is entitled to. The dynamic potential capacity is determined based on the total capacity, a comparison of one or more of the current utilizations to one or more of the corresponding equilibrium capacities and a relative resource weight of each of the plurality of competing containers. The dynamic potential capacity is optionally recalculated when the set of plurality of containers is changed or after the assignment of each work element.

A method and apparatus for method of continuously producing 1,1,1,2,3-pentafluoropropane with high yield is provided. The method includes (a) bringing a CoF3-containing cobalt fluoride in a reactor into contact with 3,3,3-trifluoropropene to produce a CoF2-containing cobalt fluoride and 1,1,1,2,3-pentafluoropropane, (b) transferring the CoF2-containing cobalt fluoride in the reactor to a regenerator and bringing the transferred CoF2-containing cobalt fluoride into contact with fluorine gas to regenerate a CoF3-containing cobalt fluoride, and (c) transferring the CoF3-containing cobalt fluoride in the regenerator to the reactor and employing the transferred CoF3-containing cobalt fluoride in Operation (a). Accordingly, the 1,1,1,2,3-pentafluoropropane can be continuously produced with high yield from the 3,3,3-trifluoropropene using a cobalt fluoride (CoF2/CoF3) as a fluid catalyst, thereby improving the reaction stability and readily adjusting the optimum conversion rate and selectivity.

Methods or preparing para-xylene from biomass by carrying out a Diels-Alder cycloaddition at controlled temperatures and activity ratios. Methods of preparing bio-terephthalic acid and bio-poly(ethylene terephthalate (bio-PET) are also disclosed, as well as products formed from bio-PET.

Disclosed are: a diaryliodonium salt mixture which is a precursor of a BF4 salt or the like of a diaryliodonium compound, can be produced in the form of crystals at ambient temperature, can be purified in a simple manner, can be produced with high efficiency, and can be induced into a BF4 salt or the like salt that has excellent solubility in a monomer or the like; and a process for producing the diaryliodonium salt mixture. Also disclosed is a production process which can achieve good yield and can produce reduced amounts of byproducts, and is therefore applicable to the industrial mass production of a diaryliodonium compound. The diaryliodonium salt mixture is characterized by containing at least two specific diaryliodonium salts.

A fluorographene and preparation method thereof are provided. For the said fluorographene, the fraction of F is 0.5

The present disclosure relates to a process for separating a fluoroolefin from a mixture comprising hydrogen fluoride and fluoroolefin, comprising azeotropic distillation both with and without an entrainer. In particular are disclosed processes for separating any of HFC-1225ye, HFC-1234ze, HFC-1234yf or HFC-1243zf from HF.

The present invention relates to a process for separating chlorinated methanes utilizing a dividing wall column. Processes and manufacturing assemblies for generating chlorinated methanes are also provided, as are processes for producing products utilizing the chlorinated methanes produced and/or separated utilizing the present process(es) and/or assemblies.

A dehydrochlorination process is disclosed. The process involves contacting RfCFClCH2X with a catalyst in a reaction zone to produce a product mixture comprising RfCF═CHX, wherein said catalyst comprises MY supported on carbon, and wherein Rf is a perfluorinated alkyl group, X ═H, F, Cl, Br or I, M=K, Na or Cs, and Y═F, Cl or Br.

A method for preparing 13C labeled iodotridecane represented by Formula A: The method comprises the conversion of 13C labeled propargyl alcohol to 13C labeled iodotridecane via alkylation of propargyl alcohol with iododecane.

The invention relates to a process for the preparation of formula (I) which process comprises pyrolyzing a compound of formula (II) wherein X is chloro or bromo, and to compounds which may be used as intermediates for the manufacture of the compound of formula I and to the preparation of said intermediates.

The subject of the invention is a process for the preparation of fluoroolefin compounds. It relates more particularly to a process for manufacturing a (hydro)fluoroolefin compound comprising (i) bringing at least one compound comprising from three to six carbon atoms, at least two fluorine atoms and at least one hydrogen atom, provided that at least one hydrogen atom and one fluorine atom are located on adjacent carbon atoms, into contact with potassium hydroxide in a stirred reactor, containing an aqueous reaction medium, equipped with at least one inlet for the reactants and with at least one outlet, in order to give the (hydro)fluoroolefin compound, which is separated from the reaction medium in gaseous form, and potassium fluoride, (ii) bringing the potassium fluoride formed in (i) into contact, in an aqueous medium, with calcium hydroxide in order to give potassium hydroxide and to precipitate calcium fluoride, (iii) separation of the calcium fluoride precipitated in step (ii) from the reaction medium and (iv) optionally, the reaction medium is recycled after optional adjustment of the potassium hydroxide concentration to step (i).

The present invention provides a method for separating halocarbons. In particular, the invention provides a method for separating halogenated olefin impurities from 2-chloro-1,1,1,2-tetrafluoropropane (HCFC-244bb) using a solid adsorbent, particularly activated carbon. More particularly the invention pertains to a method for separating 2-chloro-3,3,3-trifluoro-propene (HCFO-1233xf) from HCFC-244bb, which are useful as intermediates in the production of 2,3,3,3-tetrafluoropropene (HFO-1234yf).

Fluorinated aromatic materials, their synthesis and their use in optoelectronics. In some cases, the fluorinated aromatic materials are perfluoroalkylated aromatic materials that may include perfluoropolyether substituents.

A process for making a fluorinated olefin having the step of dehydrochlorinating a hydrochlorofluorocarbon having at least one hydrogen atom and at least one chlorine atom on adjacent carbon atoms, preferably carried out in the presence of a catalyst selected from the group consisting of (i) one or more metal halides, (ii) one or more halogenated metal oxides, (iii) one or more zero-valent metals/metal alloys, (iv) a combination of two or more of the foregoing.

A composition and method demulsify a produced emulsion from anionic surfactants and polymer (SP) and alkali, surfactants, and polymer (ASP). The produced emulsion is demulsified into oil and water. In one embodiment, the composition includes a surfactant. The surfactant comprises a cationic surfactant, an amphoteric surfactant, or any combinations thereof.

Methods of increasing the solubility of a base in supercritical carbon dioxide include forming a complex of a Lewis acid and the base, and dissolving the complex in supercritical carbon dioxide. The Lewis acid is soluble in supercritical carbon dioxide, and the base is substantially insoluble in supercritical carbon dioxide. Methods for increasing the solubility of water in supercritical carbon dioxide include dissolving an acid or a base in supercritical carbon dioxide to form a solution and dissolving water in the solution. The acid or the base is formulated to interact with water to solubilize the water in the supercritical carbon dioxide. Some compositions include supercritical carbon dioxide, a hydrolysable metallic compound, and at least one of an acid and a base. Some compositions include an alkoxide and at least one of an acid and a base.

The invention is drawn to fluid concentrate formulations of fatty acid monoethanolamides comprising (a) about 71-76% by weight of one or more C8-C22 fatty acid monoethanolamides, (b) about 15-17% by weight of water, and (c) about 10-12% by weight of one or more hydrotropes, based on the fluid formulation, wherein the fluid formulation is homogeneous, pumpable and color stable at a temperature of less than 55° C. A preferred embodiment is drawn to fluid concentrate formulations of cocamide monoethanolamide (CMEA) consisting of (a) about 71-76% by weight of CMEA, (b) about 15-17% by weight of water, and (c) about 10-12% by weight of glycerol, based on the fluid formulation. Methods of preparing the fluid concentrate formulations mulations are also disclosed. The fluid concentrate formulations of fatty acid monoethanolamides are useful in the preparation of cosmetic and pharmaceutical compositions.

This invention provides a method related to the preparation of derivatives of poly(ethylene glycol), wherein the method comprises increasing the pH of an aqueous composition comprising a poly(ethylene glycol) bearing a —O—(CH2)n—CO2R3 functional group to result in an aqueous composition comprising a poly(ethylene glycol) bearing a —O—(CH2)n—CO2H functional group, wherein R3 is alkyl and (n) in each instance is 1-6.

A method for producing polymer particles includes a preparation step for preparing a first oily liquid containing an oily olefin monomer, a radical polymerization initiator, and an iodine molecule, a synthesis step for obtaining a second oily liquid containing at least an iodine compound produced by a reaction between a radical generated by cleavage of the radical polymerization initiator and the iodine molecule in the first oily liquid, a suspension step for obtaining an oil droplet of the second oily liquid by suspending the second oily liquid in water, and a polymerization step for polymerizing the oily olefin monomer in the oil droplet.

Oil-water dispersions and emulsions derived from petroleum industry operations are demulsified and clarified using anionic polymers. Formation of such oil-water dispersion and emulsions is inhibited and mitigated using the anionic polymers. The anionic polymers comprise: A) 2-80% by weight of at least one C3-C8 α,β-ethylenically unsaturated carboxylic acid monomer; B) 15-80% by weight of at least one nonionic, copolymerizable α,β-ethylenically unsaturated monomer; C) 1-50% by weight of one or more of the following monomers: C1) at least one nonionic vinyl surfactant ester; or C2) at least one nonionic, copolymerizable α,β-ethylenically unsaturated monomer having longer polymer chains than monomer B), or C3) at least one nonionic urethane monomer; and, optionally, D) 0-5% by weight of at least one crosslinker.

The present invention relates to a method for producing particles of a compound of interest. In a method according to the invention a solution is provided of the compound of interest in a solvent. This solution is thickened or gelled and particles are formed. The invention further relates to a particle that is obtainable by the invention.

Particular aspects provide compositions comprising an electrokinetically altered oxygenated aqueous fluid, wherein the oxygen in the fluid is present in an amount of at least 25 ppm. In certain aspects, the electrokinetically altered oxygenated aqueous fluid comprises electrokinetically modified or charged oxygen species present in an amount of at least 0.5 ppm. In certain aspects the electrokinetically altered oxygenated aqueous fluid comprises solvated electrons stabilized by molecular oxygen, and wherein the solvated electrons present in an amount of at least 0.01 ppm. In certain aspects, the fluid facilitates oxidation of pyrogallol to purpurogallin in the presence of horseradish peroxidase enzyme (HRP) in an amount above that afforded by a control pressure pot generated or fine-bubble generated aqueous fluid having an equivalent dissolved oxygen level, and wherein there is no hydrogen peroxide, or less than 0.1 ppm of hydrogen peroxide present in the electrokinetic oxygen-enriched aqueous fluid.

Described is a method to prepare wet foams exhibiting long-term stability wherein colloidal particles are used to stabilize the gas-liquid interface, said particles being initially inherently partially lyophobic particles or partially lyophobized particles having mean particle sizes from 1 nm to 20 μm. In one aspect, the partially lyophobized particles are prepared in-situ by treating initially hydrophilic particles with amphiphilic molecules of specific solubility in the liquid phase of the suspension.

The disclosure relates to methods of making polymer particles, said methods including the steps of: making an aqueous gel reaction mixture; forming an emulsion having dispersed aqueous phase micelles of gel reaction mixture in a continuous phase; adding an initiator oil comprising at least one polymerization initiator to the continuous phase; and performing a polymerization reaction in the micelles. Further, the initiator oil is present in a volume % relative to a volume of the aqueous gel reaction mixture of between about 1 vol % to about 20 vol %. The disclosure also relates to methods of making nucleic acid polymer particles having the same method steps and wherein the aqueous gel reaction mixture includes a nucleic acid fragment, such as a primer.

A method of reducing the downward flow of air currents on the leeward side of an emissions emitting structure including the step of using a system that includes components chosen from the group consisting of one or more mechanical air moving devices; physical structures; and combinations thereof to create an increase in the air pressure within a volume of air on the leeward side of an emissions emitting structure having emissions that become airborne. The increased air pressure prevents or lessens downward flow of emissions that would occur without the use of the system and increases the safety by which one can travel a road or other transportation route that might otherwise be visually obscured by the emissions and the safety of the property and those within the area where emissions occur.

A method of making cerium-containing metal oxide nanoparticles in non-polar solvent eliminates the need for solvent shifting steps. The direct synthesis method involves: (a) forming a reaction mixture of a source of cerous ion and a carboxylic acid, and optionally, a hydrocarbon solvent; and optionally further comprises a non-cerous metal ion; (b) heating the reaction mixture to oxidize cerous ion to ceric ion; and (c) recovering a nanoparticle of either cerium oxide or a mixed metal oxide comprising cerium. The cerium-containing oxide nanoparticles thus obtained have cubic fluorite crystal structure and a geometric diameter in the range of about 1 nanometer to about 20 nanometers. Dispersions of cerium-containing oxide nanoparticles prepared by this method can be used as a component of a fuel or lubricant additive.

Process for preparing a dispersion comprising silicon dioxide particles and cationizing agents, by dispersing 50 to 75 parts by weight of water, 25 to 50 parts by weight of silicon dioxide particles having a BET surface area of 30 to 500 m2/g and 100 to 300 μg of cationizing agent per square meter of the BET surface area of the silicon dioxide particles, wherein the cationizing agent is obtainable by reacting at least one haloalkyl-functional alkoxysilane, hydrolysis products, condensation products and/or mixtures thereof with at least one aminoalcohol and water; and optionally removing the resulting hydrolysis alcohol from the reaction mixture. Also the process for preparing the dispersion, wherein the cationizing agent comprises one or more quaternary, aminoalcohol-functional, organosilicon compounds of formula III and/or condensation products thereof, wherein Ru and Rv are independently C2-4 alkyl group, m is 2-5 and n is 2-5.

A microfluidic method and device for focusing and/or forming discontinuous sections of similar or dissimilar size in a fluid is provided. The device can be fabricated simply from readily-available, inexpensive material using simple techniques.

According to the present invention, a metal nanoparticle dispersion suitable to multiple layered coating by jetting in the form of fine droplets is prepared by dispersing metal nanoparticles having an average particle size of 1 to 100 nm in a dispersion solvent having a boiling point of 80° C. or higher in such a manner that the volume percentage of the dispersion solvent is selected in the range of 55 to 80% by volume and the fluid viscosity (20° C.) of the dispersion is chosen in the range of 2 mPa·s to 30 mPa·s, and then when the dispersion is discharged in the form of fine droplets by inkjet method or the like, the dispersion is concentrated by evaporation of the dispersion solvent in the droplets in the course of flight, coming to be a viscous dispersion which can be applicable to multi-layered coating.

A method for synthesizing catalyst beads of bulk transmission metal carbides, nitrides and phosphides is provided. The method includes providing an aqueous suspension of transition metal oxide particles in a gel forming base, dropping the suspension into an aqueous solution to form a gel bead matrix, heating the bead to remove the binder, and carburizing, nitriding or phosphiding the bead to form a transition metal carbide, nitride, or phosphide catalyst bead. The method can be tuned for control of porosity, mechanical strength, and dopant content of the beads. The produced catalyst beads are catalytically active, mechanically robust, and suitable for packed-bed reactor applications. The produced catalyst beads are suitable for biomass conversion, petrochemistry, petroleum refining, electrocatalysis, and other applications.

A data processing apparatus includes multiple processing means that are connected in a ring shape via corresponding communication means respectively. Each communication means includes a reception means for receiving data from a previous communication means, and a transmission means for transmitting data to a next communication means. Connection information is assigned to each of the reception means and the transmission means. The communication means, when receiving a packet that has same connection information as one assigned to its reception means, causes the corresponding processing means to perform data processing on the packet, sets the connection information assigned to its transmission means to the packet, and transmits the packet to the next communication means, and when receiving a packet that has connection information that is not same as one assigned to its reception means, transmits the packet to the next communication means without changing the connection information of the packet.

A computing section is provided with a plurality of computing units and correlatively stores entries of configuration information that describes configurations of the plurality of computing units with physical configuration numbers that represent the entries of configuration information and executes a computation in a configuration corresponding to a designated physical configuration number. A status management section designates a physical configuration number corresponding to a status to which the computing section needs to advance the next time for the computing section and outputs the status to which the computing section needs to advance the next time as a logical status number that uniquely identifies the status to which the computing section needs to advance the next time in an object code. A determination section determines whether or not the computing section has stored an entry of configuration information corresponding to the status to which the computing section needs to advance the next time based on the logical status number that is output from the status management section. A rewriting section correlatively stores the entry of the configuration information and a physical configuration number corresponding to the entry of the configuration information in the computing section when the determination section determines that the computing section has not stored the entry of configuration information corresponding to the status to which the computing section needs to advance the next time.

Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.

A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.

The disclosure relates to the implementation of multi-tasking on a digital signal processor. Blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which instead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. Whilst the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.

A system and method for controlling restarting of instruction fetching using speculative address computations in a processor are provided. The system includes a predicted target queue to hold branch prediction logic (BPL) generated target address values. The system also includes target selection logic including a recycle queue. The target selection logic selects a saved branch target value between a previously speculatively calculated branch target value from the recycle queue and an address value from the predicted target queue. The system further includes a compare block to identify a wrong target in response to a mismatch between the saved branch target value and a current calculated branch target, where instruction fetching is restarted in response to the wrong target.

Embodiments provide methods, apparatus, systems, and computer readable media associated with predicting predicates and branch targets during execution of programs using combined branch target and predicate predictions. The predictions may be made using one or more prediction control flow graphs which represent predicates in instruction blocks and branches between blocks in a program. The prediction control flow graphs may be structured as trees such that each node in the graphs is associated with a predicate instruction, and each leaf associated with a branch target which jumps to another block. During execution of a block, a prediction generator may take a control point history and generate a prediction. Following the path suggested by the prediction through the tree, both predicate values and branch targets may be predicted. Other embodiments may be described and claimed.

Methods and systems for optimizing generation of natively executable code from non-native binary code are disclosed. One method includes receiving a source file including binary code configured for execution according to a non-native instruction set architecture. The method also includes translating one or more code blocks included in the executable binary code to source code, and applying an optimizing algorithm to instructions in the one or more code blocks. The optimizing algorithm is selected to reduce a number of memory address translations performed when translating the source code to native executable binary code, thereby resulting in one or more optimized code blocks. The method further includes compiling the source code to generate an output file comprising natively executable binary code including the one or more optimized code blocks.

The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced. The disclosure reduces the cycle delay of the slave processor in accessing the dual-port RAM and the register, thereby effectively reducing the dynamic power consumption of the chip, improving the processing capability of the slave processor and enhancing the effective performance of the slave processor.

A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.

A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behavior of the processor 2.

A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.

An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.

A data processing device includes processing circuitry 20 for executing a first memory access instruction to a first address of a memory device 40 and a second memory access instruction to a second address of the memory device 40, the first address being different from the second address. The data processing device also includes prefetching circuitry 30 for prefetching data from the memory device 40 based on a stride length 70 and instruction analysis circuitry 50 for determining a difference between the first address and the second address. Stride refining circuitry 60 is also provided to refine the stride length based on factors of the stride length and factors of the difference calculated by the instruction analysis circuitry 50.

An array of a plurality of processing elements (PEs) are in a data packet-switched network interconnecting the PEs and memory to enable any of the PEs to access the memory. The network connects the PEs and their local memories to a common controller. The common controller may include a shared load/store (SLS) unit and an array control unit. A shared read may be addressed to an external device via the common controller. The SLS unit can continue activity as if a normal shared read operation has taken place, except that the transactions that have been sent externally may take more cycles to complete than the local shared reads. Hence, a number of transaction-enabled flags may not have been deactivated even though there is no more bus activity. The SLS unit can use this state to indicate to the array control unit that a thread switch may now take place.

Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.

Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.

A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.

A processor receives an instruction operation (OP) code from a verification system. The instruction OP code includes instruction bits and forced event bits. The processor identifies a forced event based upon the forced event bits, which is unrelated to an instruction that corresponds to the instruction bits. In turn, the processor executes the forced event.