I am scripting gds streamin using 'strmin', which works fine so far.

But, as it apparently doesn't have an option to specify where the cds.lib file is, I have to run it from the directory where the cds.lib file is, or I guess I could create a dummy one to source that one.

Is there a way to tell strmin where the cds.lib file is?

We are looking for suitable tools that could be used for RTL design, IP-XACT based  integration (third party IP) and RTL design verification ( SV / UVM based methodology).

Request to share details on the different Cadence tools that is most suitable for these activities.

Hi Cadence & forumers, 

I am running a conformal LEC with a flattened netlist against RTL. 

The run hang for 5 days at the "analyze abort" step which is automatically launched by the compare. 

The netlist is flattened at some levels so hierarchical flow which I tried didn't help much. The flattened/highly optimized netlist is from customer and the ultimate goal. How shall I proceed now? 

On the a side note, a test run with a hierarchical netlist from a simple DC "compile -map_effort medium" command finished after 1 day or so. 

Thank you! 

// Command: vpx compare -verbose -ABORT_Print -NONEQ_Print -TIMEstamp
// Starting multithreaded comparison ...
Comparing 241112 points in parallel.

// Multithreading Overhead: 38% Gates: 8501606/6168138
// Multithreaded processing completed.
================================================================================
Compared points PO DFF DLAT BBOX CUT Total
--------------------------------------------------------------------------------
Equivalent 1025 241638 30 75 21 242789
--------------------------------------------------------------------------------
Abort 0 124 0 0 0 124
================================================================================
Compare results of instance/output/pin equivalences and/or sequential merge
================================================================================
Compared points DFF Total
--------------------------------------------------------------------------------
Equivalent 204 204
================================================================================
// Warning: 512 DFFs/DLATs have 1 disabled clock port: skipped data cone comparison
// Resolving aborts by analyze abort...

I'm currently trying to explore the verilog simulation option in cadence.

One thing that comes to my mind that if there exists a way in cadence workflow to dump selected register/wire's waveform during the simulation. 

Are there any additional tools needed apart from xcelium, is there a tutorial or specific training course for this aspect. I glance through Xcelium Simulator Course Version 22.09, but it seems not having related context. 

I know in Synopsys's workflow, it can be realized using verdi & fsdb in the command line as follows:

if (inst.CTRL_STATE==STATE_START_TO_DUMP)

$fsdbDumpvars(0, inst_1.reg_0);

end

Thanks in advance!

I am not able to open 64bit version of simvision using the following :

simvision -64 -wav "path to wav"

This throws the error "  /lib64/libc.so.6: version `GLIBC_2.14' not found"

I am only able to open it without the -64 option.

As a result I am not able to use the source browser feature since the simulation was run in 64 bit mode.

Need suggestion on how to resolve this. Thanks.

Hi everyone, 

Is there any method to generate "Sheet" column for a pin report like table below? The column "Name.Pin" & "Signal" can be generated easily, but I have no idea to generate the column of "Sheet Name".

The software using here are Allegro Design Entry HDL, OrCAD Capture and Allegro PCB Editor. Can these 3 software generate "Sheet Name" data?

Thank you. 

Good morning,
I dug up an old project from 2005 and I should open the schematic to check some things.
This is the schematic of a XILINX XC95108-pq160 CPLD which the XILINX ISE 6.1 software then translated and compiled, to generate a JEDEC file to burn CPLD.

My problem is that I can't open schematics with the versions of Orcad Schematic Entry that I have.
Can anyone help me understand which version of Orcad Schematic Entry I need to install to see these files?

I shared the files on:
drive.google.com/.../view

Thank you very much

Hi, have two designs and would like to copy paste one area of circuit from the old design to the new design, best way/approach and guidance please..

Hi,

I find there is a similar question 10 years ago and the answer is out of date, so I come to ask again.

I have compiled 2 different blocks in 2 different paths, using basic xrun -f xxxx.f, generated 2 xcelium.d folder.

Then I have to compile another block based on these 2, how can I link these 2 generated libraries while compiling the 3rd one?

Thanks

Hello,

I am trying to load some of the signals of the design saved in the signals.svwf to the waveform windown via the tcl file, I am using the following commands but nothing works, Can you please help 

 -submit waveform loadsignals -using "Waveform 2" FB1.svwf but it gives me the below error

-submit waveform new -reuse -name Waveforms

Below is showing my Master.v

********************************************************************************************************************************************************************************************************************

///////ALU
module ALU (
    input [31:0] A,B,
    input[3:0] alu_control,
    output reg [31:0] alu_result,
    output reg zero_flag
);
    always @(*)
    begin
        // Operating based on control input
        case(alu_control)

        4'b0001: alu_result = A+B;
        4'b0010: alu_result = A-B;
        4'b0011: alu_result = A*B;
        4'b0100: alu_result = A|B;
        4'b0101: alu_result = A&B;
        4'b0110: alu_result = A^B;
        4'b0111: alu_result = ~B;
        4'b1000: alu_result = A<<B;
        4'b1001: alu_result = A>>B;
        4'b1010: begin
            if(A<B)
            alu_result = 1;
            else
            alu_result = 0;
        end
        default: alu_result = A+B;

        endcase

        // Setting Zero_flag if ALU_result is zero
        if (alu_result)
            zero_flag = 1'b1;
        else
            zero_flag = 1'b0;   
    end
endmodule


/////CONTROL UNIT
/*
Control unit controls takes opcode, funct7, funct3 of the instruction code to determine
and control regwrite in IFU, alu control in ALU to execute proper instruction
*/
/*
Control unit controls takes opcode, funct7, funct3 of the instruction code to determine
and control regwrite in IFU, alu control in ALU to execute proper instruction
*/
module CONTROL(
    input [4:0] opcode,
    output reg [3:0] alu_control,
    output reg regwrite_control,memread_control,memwrite_control
);
    always @(opcode)
    begin
       case(opcode)
        5'b00001: begin alu_control=4'b0001;  //add
        regwrite_control=1; memread_control=0; memwrite_control=0;
        end
        5'b00010: begin alu_control=4'b0010;  ///sub
        regwrite_control=1; memread_control=0; memwrite_control=0;
        end
        5'b00011: begin alu_control=4'b0011;  //mul
        regwrite_control=0; memread_control=0; memwrite_control=1;
        end
        5'b00100: begin alu_control=4'b0100;  ///OR
        regwrite_control=0; memread_control=0; memwrite_control=1;
        end
        5'b00101: begin alu_control=4'b0101;  ///AND
        regwrite_control=1; memread_control=0; memwrite_control=0;
        end
        5'b00110: begin alu_control=4'b0110;  ///XOR
        regwrite_control=0; memread_control=0; memwrite_control=1;
        end
        5'b00111: begin alu_control=4'b0111;  ///NOT
        regwrite_control=0; memread_control=0; memwrite_control=1;
        end
        5'b01000: begin alu_control=4'b1000;  //SL
        regwrite_control=1; memread_control=1; memwrite_control=0;
        end
        5'b11001: begin alu_control=4'b1001;  //SR
        regwrite_control=1; memread_control=1; memwrite_control=0;
        end
        5'b01010: begin alu_control=4'b1010;  //COMPARE
        regwrite_control=1; memread_control=1; memwrite_control=0;
        end
        //5'b11010: begin ALU_control=4'b0000;  //SW
        //regwrite_control=1; memread_control=0; memwrite_control=0;
        //end
        //5'b01010: begin ALU_control=4'bxxxx;  //LW
        //regwrite_control=0; memread_control=0; memwrite_control=1;
        //end
        default : begin alu_control = 4'b0001;
        regwrite_control=1; memread_control=0; memwrite_control=0;
        end
        endcase  
    end
endmodule



//////DATA MEMORY
module Data_Mem(
input clock, rd_mem_enable, wr_mem_enable,
input [11:0] address,
input [31:0] datawrite_to_mem,
output reg [31:0] dataread_from_mem );

reg [31:0] Data_Memory[8:0];

initial begin
    Data_Memory[0] = 32'hFFFFFFFF;
    Data_Memory[1] = 32'h00000001;
    Data_Memory[2] = 32'h00000005;
    Data_Memory[3] = 32'h00000003;
    Data_Memory[4] = 32'h00000004;
    Data_Memory[5] = 32'h00000000;
    Data_Memory[6] = 32'hFFFFFFFF;
    Data_Memory[7] = 32'h00000000;
    //Data_Memory[8] = 32'h00000008;
    //Data_Memory[9] = 32'h00000009;
    //Data_Memory[10] = 32'h0000000A;
    //Data_Memory[11] = 32'h0000000B;
    //Data_Memory[12] = 32'h0000000C;
    //Data_Memory[13] = 32'h0000000D;
    //Data_Memory[14] = 32'h0000000E;
    //Data_Memory[15] = 32'h0000000F;
    //Data_Memory[16] = 32'h00000010;
    //Data_Memory[17] = 32'h00000011;
    //Data_Memory[18] = 32'h00000012;
    //Data_Memory[19] = 32'h00000013;
    //Data_Memory[20] = 32'h00000014;
    //Data_Memory[21] = 32'h00000015;
    //Data_Memory[22] = 32'h00000016;
    //Data_Memory[23] = 32'h00000017;
    //Data_Memory[24] = 32'h00000018;
    //Data_Memory[25] = 32'h00000019;
    //Data_Memory[26] = 32'h0000001A;
    //Data_Memory[27] = 32'h0000001B;
    //Data_Memory[28] = 32'h0000001C;
    //Data_Memory[29] = 32'h0000001D;
    //Data_Memory[30] = 32'h0000001E;
    Data_Memory[31] = 32'h0000001F;
       
    end
    always@(posedge clock) begin
       if(wr_mem_enable) begin
            Data_Memory[address] <= datawrite_to_mem;
       end
       else if(rd_mem_enable) begin
               dataread_from_mem <= Data_Memory[address];
       end
       else begin
               dataread_from_mem <= 32'h00000000;
       end
    end
endmodule   



/////INST MEM
/*

*/
module INST_MEM(
    input [31:0] PC,
    input reset,
    output [31:0] Instruction_Code
);
    reg [7:0] Memory [43:0]; // Byte addressable memory with 32 locations

    
    assign Instruction_Code = {Memory[PC+3],Memory[PC+2],Memory[PC+1],Memory[PC]};

    
    
    initial begin
            // Setting 32-bit instruction: add t1, s0,s1 => 0x00940333
            Memory[3] = 8'b0000_0000;
            Memory[2] = 8'b0000_0001;
            Memory[1] = 8'b0111_1100;
            Memory[0] = 8'b0000_0001;
            // Setting 32-bit instruction: sub t2, s2, s3 => 0x413903b3
            Memory[7] = 8'b0000_0000;
            Memory[6] = 8'b0000_0110;
            Memory[5] = 8'b1000_1111;
            Memory[4] = 8'b1110_0010;
            // Setting 32-bit instruction: mul t0, s4, s5 => 0x035a02b3
            Memory[11] = 8'b0000_0000;
            Memory[10] = 8'b0000_0101;
            Memory[9] = 8'b0111_1100;
            Memory[8] = 8'b0000_0011;
            // Setting 32-bit instruction: or t3, s6, s7 => 0x017b4e33
            Memory[15] = 8'b1111_1111;
            Memory[14] = 8'b1111_0100;
            Memory[13] = 8'b1010_0000;
            Memory[12] = 8'b1010_0100;
            // Setting 32-bit instruction: and
            Memory[19] = 8'b0000_0000;
            Memory[18] = 8'b0010_1001;
            Memory[17] = 8'b0001_1101;
            Memory[16] = 8'b0010_0101;
            // Setting 32-bit instruction: xor
            Memory[23] = 8'b0000_0000;
            Memory[22] = 8'b0001_1000;
            Memory[21] = 8'b0000_1101;
            Memory[20] = 8'b0110_0110;
            // Setting 32-bit instruction: not
            Memory[27] = 8'b0000_0000;
            Memory[26] = 8'b0010_1001;
            Memory[25] = 8'b0011_1101;
            Memory[24] = 8'b1100_0111;
            // Setting 32-bit instruction: shift left
            Memory[31] = 8'b0000_0000;
            Memory[30] = 8'b0101_0111;
            Memory[29] = 8'b1100_0110;
            Memory[28] = 8'b0000_1000;
            // Setting 32-bit instruction: shift right
            Memory[35] = 8'b0000_0000;
            Memory[34] = 8'b0110_1010;
            Memory[33] = 8'b1101_0010;
            Memory[32] = 8'b0111_1001;
            /// Setting 32-bit instruction: Campare
            Memory[39] = 8'b0000_0000;
            Memory[38] = 8'b0111_1010;
            Memory[37] = 8'b1101_0010;
            Memory[36] = 8'b0110_1010;
            /// Setting 32-bit instruction:
            Memory[43] = 8'b0000_0000;
            Memory[42] = 8'b0111_0111;
            Memory[41] = 8'b1101_0010;
            Memory[40] = 8'b0111_0010;
        end
   

endmodule

//IFU
/*
The instruction fetch unit has clock and reset pins as input and 32-bit instruction code as output.
Internally the block has Instruction Memory, Program Counter(P.C) and an adder to increment counter by 4,
on every positive clock edge.
*/
module IFU(
    input clock,reset,
    output [31:0] Instruction_Code
);
reg [31:0] PC = 32'b0;  // 32-bit program counter is initialized to zero

    
    always @(posedge clock, posedge reset)
    begin
        if(reset == 1)  //If reset is one, clear the program counter
        PC <= 0;
        else
        PC <= PC+4;   // Increment program counter on positive clock edge
    end
    // Initializing the instruction memory block
    INST_MEM instr_mem(.PC(PC),.reset(reset),.Instruction_Code(Instruction_Code));

endmodule


///MUX

module Mux_2X1 (
    input mem_rd_select, // rd_mem_enable
    input wire [31:0] dataread_from_mem, regdata2,

    output reg [31:0] mux_out
);

always @(mem_rd_select or dataread_from_mem or regdata2) begin
    if (mem_rd_select == 1)
        mux_out <= dataread_from_mem ;
    else
        mux_out <= regdata2;
    end
endmodule

//DFlipFlop
module DFlipFlop(D,clock,Q);
input D; // Data input
input clock; // clock input
output reg Q; // output Q
always @(posedge clock)
begin
 Q <= D;
end
endmodule

///DATA path


module DATAPATH(
    input [4:0]Read_reg_add1,
    input [4:0]Read_reg_add2,
    input [4:0]Reg_write_add,
    input [3:0]Alu_control,
    input [11:0]Address,
    input Wr_reg_enable,Wr_mem_enable,Rd_mem_enable,
    input clock,
    input reset,
    output OUTPUT
    );

    // Declaring internal wires that carry data
    wire zero_flag;
    wire [31:0]Dataread_from_mem;
    wire [31:0]read_data1;
    wire [31:0]read_data2;
    wire [31:0]Mux_out;
    wire [31:0]Alu_result;
    //wire [31:0]datawrite_to_reg;

    // Instantiating the register file
    REG_FILE reg_file_module(.reg_read_add1(Read_reg_add1),.reg_read_add2(Read_reg_add2),.reg_write_add(Reg_write_add),.datawrite_to_reg(Alu_result),.read_data1(read_data1),.read_data2(read_data2),.wr_reg_enable(Wr_reg_enable),.clock(clock),.reset(reset));

    // Instanting ALU
    ALU alu_module(.A(read_data1), .B(Mux_out), .alu_control(Alu_control), .alu_result(Alu_result), .zero_flag(zero_flag));
    
    //Mux
    Mux_2X1 mux(.mem_rd_select(Rd_mem_enable),.dataread_from_mem(Dataread_from_mem),.regdata2(read_data2),.mux_out(Mux_out));

    //Data Memory
    Data_Mem DM(.clock(clock),.rd_mem_enable(Rd_mem_enable),.wr_mem_enable(Wr_mem_enable),.address(Address),.datawrite_to_mem(Alu_result),.dataread_from_mem(Dataread_from_mem));
    
    // Dflipflop
    DFlipFlop DF (.D(zero_flag), .Q(OUTPUT),.clock(clock));
endmodule


/*
A register file can read two registers and write in to one register.
The RISC V register file contains total of 32 registers each of size 32-bit.
Hence 5-bits are used to specify the register numbers that are to be read or written.
*/

/*
Register Read: Register file always outputs the contents of the register corresponding to read register numbers specified.
Reading a register is not dependent on any other signals.

Register Write: Register writes are controlled by a control signal RegWrite.  
Additionally the register file has a clock signal.
The write should happen if RegWrite signal is made 1 and if there is positive edge of clock.
*/
module REG_FILE(
    input [4:0] reg_read_add1,
    input [4:0] reg_read_add2,
    input [4:0] reg_write_add,
    input [31:0] datawrite_to_reg,
    output [31:0] read_data1,
    output [31:0] read_data2,
    input wr_reg_enable,
    input clock,
    input reset
);

    reg [31:0] reg_memory [31:0]; // 32 memory locations each 32 bits wide
    
    initial begin
        reg_memory[0] = 32'h00000000;
        reg_memory[1] = 32'hFFFFFFFF;
        reg_memory[2] = 32'h00000002;
        reg_memory[3] = 32'hFFFFFFFF;
        reg_memory[4] = 32'h00000004;
        reg_memory[5] = 32'h01010101;
        reg_memory[6] = 32'h00000006;
        reg_memory[7] = 32'h00000000;
        reg_memory[8] = 32'h10101010;
        reg_memory[9] = 32'h00000009;
        reg_memory[10] = 32'h0000000A;
        reg_memory[11] = 32'h0000000B;
        reg_memory[12] = 32'h0000000C;
        reg_memory[13] = 32'h0000000D;
        reg_memory[14] = 32'h0000000E;
        reg_memory[15] = 32'h0000000F;
        reg_memory[16] = 32'h00000010;
        reg_memory[17] = 32'h00000011;
        reg_memory[18] = 32'h00000012;
        reg_memory[19] = 32'h00000013;
        reg_memory[20] = 32'h00000014;
        reg_memory[21] = 32'h00000015;
        //reg_memory[22] = 32'h00000016;
        //reg_memory[23] = 32'h00000017;
        //reg_memory[24] = 32'h00000018;
        //reg_memory[25] = 32'h00000019;
        //reg_memory[26] = 32'h0000001A;
        //reg_memory[27] = 32'h0000001B;
        //reg_memory[28] = 32'h0000001C;
        //reg_memory[29] = 32'h0000001D;
        //reg_memory[30] = 32'h0000001E;
        reg_memory[31] = 32'hFFFFFFFF;
    end

    // The register file will always output the vaules corresponding to read register numbers
    // It is independent of any other signal
    assign read_data1 = reg_memory[reg_read_add1];
    assign read_data2 = reg_memory[reg_read_add2];

    // If clock edge is positive and regwrite is 1, we write data to specified register
    always @(posedge clock)
    begin
        if (wr_reg_enable) begin
            reg_memory[reg_write_add] = datawrite_to_reg;
        end     
    else
        reg_memory[reg_write_add] = 32'h00000000;
    end
endmodule


/////PROCESSOR


module PROCESSOR(
    input clock,
    input reset,
    output Output
);

    wire [31:0] instruction_Code;
    wire [3:0] ALu_control;
    wire WR_reg_enable;
    wire WR_mem_enable;
    wire RD_mem_enable;


    IFU IFU_module(.clock(clock), .reset(reset), .Instruction_Code(instruction_Code));
    
    CONTROL control_module(.opcode(instruction_Code[4:0]),.alu_control(ALu_control),.regwrite_control(WR_reg_enable),.memread_control(RD_mem_enable),.memwrite_control(WR_mem_enable));
    
    DATAPATH datapath_module(.Wr_mem_enable(WR_mem_enable),.Rd_mem_enable(RD_mem_enable),.Read_reg_add1(instruction_Code[9:5]),.Read_reg_add2(instruction_Code[14:10]),.Reg_write_add(instruction_Code[19:15]),.Address(instruction_Code[31:20]),.Alu_control(ALu_control),.Wr_reg_enable(WR_reg_enable), .clock(clock), .reset(reset), .OUTPUT(Output));

endmodule

**********************************************************************************************************************************************************

Below is my Synthesis.tcl file for genus synthesis

********************

set_attribute lib_search_path "/home/sameer23185/Desktop/VDF_PROJECT/lib"
set_attribute hdl_search_path "/home/sameer23185/Desktop/VDF_PROJECT"
set_attribute library "/home/sameer23185/Desktop/VDF_PROJECT/lib/90/fast.lib"
read_hdl Master.v
elaborate
read_sdc Min_area.sdc
set_attribute hdl_preserve_unused_register true
set_attribute delete_unloaded_seqs false
set_attribute optimize_constant_0_flops false
set_attribute optimize_constant_1_flops false
set_attribute optimize_constant_latches false
set_attribute optimize_constant_feedback_seqs false
#set_attribute prune_unsued_logic false
synthesize -to_mapped -effort medium
write_hdl > report/HDL_min_Netlist.v
write_sdc > report/constraints.sdc
write_script > report/synthesis.g
report_timing > report/synthesis_timing_report.rep
report_power > report/synthesis_power_report.rep
report_gates > report/synthesis_cell_report.rep
report_area > report/synthesis_area_report.rep
gui_show

**********************************************

WHEN I COMPARING MY GOLDEN.V WITH HDL_min_Netlist.v  during   conformal , I got  these  non-equivalent   point   for   every reg memory and for every data memory. I don't know what to do with these non-equivalent point. I've been stuck here for the past four days. Please help me in this and how can I remove this non- equivalent point , since I am new to this I really don't know what to do.

hi

How can I tell the LEC tool to ignore a combination of Primary input bus in both Golden and revised.

For example in both Golden and revised there is 

input [3:0] data_in

I want LEC not to check the case that data_in[3:0] == 4'b1000

I was trying to remove the cdn_loop_breaker cells from the netlist. 
When I tried the below 2 things, it removing the cdn_loop_breaker cells but while connecting the cdn_loop_breaker cell input to its proper connection, its somehow misleading the connections

Things i tried:
1.  remove_cdn_loop_breaker -instances *cdn_loop_breaker*
then i just ran remove_cdn_loop_breaker  comand without the -instances switch
2. remove_cdn_loop_breaker  
     
both of the above things are not providing the proper connections after removing the loop_breaker_cells

I want to use a transmission gate in my design, but it is not available as a standard cell for Genus RTL synthesis. How can I perform an analysis of area, power, and critical path delay that includes the transmission gate alongside standard cells?

Could you provide guidance or a methodology for integrating custom cells, like the transmission gate, into the synthesis flow for accurate analysis?

Hi ,

 I am using conformal v23.2 for LEC checking b/w netlist vs Netlist. I am getting 8 not mapped points(z) in revised but when i check in mapping manager it showing 0 Not mapped points and showing this 8 not mapped points in extra unmapped section z(f) snps_scan_out_6 .How to resolve this issue Pls help

regards,

We have a big circuit having 12K gates totally and trying to show it in one page slide visually. But it is so hard for us to shrink it down from gate-level to module-level. Do you have any function like these:

• Toggle wires on and off
• “Right click” elements and group them into black boxes
• Quickly left or right align elements to clean up pictures

Optimize Regression Suite, Accelerate Coverage Closure, and Increase hit count of rare bins using Xcelium Machine Learning. It is easy to use and has no learning curve for existing Xcelium customers. Xcelium Machine Learning Technology helps you discover hidden bugs when used early in your design verification cycle.(read more)

Artificial intelligence (AI) is everywhere. Machine learning (ML) and its associated inference abilities promise to revolutionize everything from driving your car to making your breakfast. Verification is never truly complete; it is over when you run...(read more)

With the DRAM fabrication advancing from 1x to 1y to 1z and further to 1a, 1b and 1c nodes along with the DRAM device speeds going up to 8533 for Lpddr5/8800 for DDR5, Data integrity is becoming a really important issue that the OEMs and other users have to consider as part of the system that relies on the correctness of data being stored in the DRAMs for system to work as designed.

It’s a complicated problem that requires multiple ways to deal with it.

Traditionally one of the main approaches to deal with data errors is to rely on the ECC. ECC requires additional memory storage in which the ECC codes will calculated and stored at the time of memory write to DRAM. These codes will be read back along with the memory data during to the reads and checked against the data to make sure that there are no errors. Typical ECC schemes use Hamming code that provide for single bit error correction and double bit error detection per burst. Also, while several of previous generation of DRAM required Host to keep aside system memory for ECC storage latest DRAMs like Lpddr5 and DDR5 support on die ECC as part of the normal DRAM function that can be enabled using mode registers. DDR5 further requires Host to run through an ECC Error Check and Scrub (ECS) cycle on an average every tECSint time (Average Periodic ECS Interval) to prevent data errors.

Not meeting the DRAM Refresh requirement is a major reason that can lead to loss of data. This could be challenging as the PVT variation can cause the refresh requirement to change over time. Putting the DRAM in Self Refresh mode can help off-loading Refresh tracking responsibilities to DRAM but may prevent Host to do other scheduling optimizations and should be carefully considered.

Some of the other things that can affect the DRAM data are

1. Row hammer where same or adjacent rows are activated again and again leading to loss or changing of data contents in the rows that has not being addressed. Latest DRAMs like Lpddr5/Ddr5 support Refresh Management (including DRFM and ARFM) that allows the Host to compensate for these problems by issuing dedicated RFM commands helping DRAMs deals with potential Data loss issues arising out of Row hammer attacks.
2. Device temperature is another important factor that the Host needs to be aware of and if the application requires DRAM to operate at elevated temperature. The user needs to check with DRAM Vendor on the temperature range that DRAM can still operate. Data integrity at thresholds greater than certain temperature is not assured regardless of refresh rate unless DRAM is manufactured to withstand that.
3. Loss of power to DRAM will cause DRAM to lose all its contents. If this is a real concern for the system designer, they should consider using NVDIMM-N devices which has an onchip controller and a power source which is just enough to allow the DRAM contents to be copied into a backup non-volatile memory before power is lost. When the power is stored back, the stored memory contents in the non-volatile memory will be written back to the DRAM and system can continue to operate as it was before the power loss event occurred.

For transmissions and manufacturing errors DRAMs support additional features like CRC, DFE, Pre-Emphasis and PPR which will be covered in the next blog.

Cadence MMAV VIPs for DDR5/DDR5 DIMM and LPDDR5 are compressive VIP solutions and supports all of the above-listed Data integrity features including support for ECC error injection and SBE correction/DBE detection to assist with the verification challenges dealing with data integrity issues.

More information on Cadence DDR5/LPDDR5 VIP is available at Cadence VIP Memory Models Website.

Shyam 

The automotive industry revolutionized the definition of a vehicle in terms of safety, comfort, enhanced autonomy, and internet connectivity. With this trend, the automotive industry rapidly adopted automotive Ethernet such as 10Base-T1, 100Base-T1, and in some cases, 1000Base-T1. 

Faster Speed (than CAN-FD), Scalability, embedded security protocols (like MacSec), cost and energy efficiency, and simple yet redundant network made Ethernet an obvious choice over CAN(FD) and FlexRay.  

Ethernet 10Base-T1 

10BASE-T1S is defined under IEEE with 802.3cg. The S in 10BASE-T1S stands for a short distance. 10BASE-T1S uses a multidrop topology, where each node connects to a single cable. Multidrop topology eliminates the need for switches and, as a result, fewer cables/less cost. The primary goal of 10BASE-T1S is a deterministic transmission on a collision-free multidrop network. 10BASE-T1S cables use a pair of twisted wires. As per IEEE, at least eight nodes can connect to each, but more connections are feasible.    

The Physical Layer Collision Avoidance [PLCA] protocol ensures that it uses the entire 10 Mbps bandwidth. In 10BaseTs, Reconciliation Sublayer provides optional Physical Layer Collision Avoidance (PLCA) capabilities among participating stations. Using PLCA-enabled Physical Layers in CSMA/CD half-duplex shared-medium networks can provide enhanced bandwidth and improved access latency under heavily loaded traffic conditions. The working principle of PLCA is that transmit opportunities on a mixing segment are granted in sequence based on a node ID unique to the local collision domain (set by the management entity). 10BASE-T1S also supports an arbitration scheme that guarantees consistent node access to the media within a predefined time.  

The 10BASE-T1S PHY is intended to cover the low-speed/low-cost applications in the industrial and automotive environment. A large number of pins (16) required by the MII interface is one of the significant cost factors that must be addressed to fulfill this objective. The 10BASE-T1S "Transceiver" solution is suited for embedded systems where the digital portion of the PHY is fully integrated, e.g., into an MCU or an Ethernet switch core, leaving only the analog portion (the transceiver) into a separate IC. 

Ethernet 100Base-T1/1000Base-T1 

100Base-T1 and 1000Base-T1 can be used for audio/video information. With Higher bandwidth capacity, 100Base-T1/ 1000Base-T1 paired with AVB (Audio video bridging) can be used for car infotainment systems. 100Base-T1/1000Base-T1 paired with time-sensitive networking [TSN] protocol can be used to fulfill the automotive industry's mission-critical, time-sensitive, and deterministic latency needs. 

 PTP Over MacSec  

With today's automotive network, all the Electronic Control Units connected require timing accuracy and network synchronization, Precision Time Protocol (PTP), defined in IEEE 1588, provides synchronized clocks throughout a network.  While maintaining the timing accuracy for mission-critical applications, protecting the vehicle network from vulnerable threats is mandatory, and PTP over MacSec provides the consolidated solution.  

With the availability of the Cadence Verification IP for 10/100/1000BaseT1 and TSN, adopters can start working with these specifications immediately, ensuring compliance with the standard and achieving the fastest path to IP and SoC verification closure. The 10/100/1000GBaseT1 and TSN provide a full-stack solution, including support to the PHY, MAC, and TSN layers with a comprehensive coverage model and protocol checkers. Ethernet BaseT1 and TSN VIP covers all features required for complete coverage verification closure. More details are available in the Ethernet Verification IP portfolio. 

Krunal 

The increase in compute and data-intensive applications and the need for lower power consumption have resulted in a rapidly growing number of Arm-based devices in various market segments; this requires fast time to market (TTM) and support for off-t...(read more)

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Speed increase requirements keep on flowing by in all the domains surrounding us. The same applies to memory storage too. Earlier mobile devices used eMMC based flash storage, which was a significantly slower technology. With increased SoC processing speed, pairing it with slow eMMC storage was becoming a bottleneck. That is when modern storage technology Universal Flash Storage (UFS) started to gain popularity. 

UFS is a simple and high-performance mass storage device with a serial interface. It is primarily used in mobile systems between host processing and mass storage memory devices. Another important reason for the usage of UFS in mobile systems like smartphones and tablets is minimum power consumption. 

To achieve the highest performance and most power-efficient data transport, JEDEC UFS works in collaboration with industry-leading specifications from the MIPI® Alliance to form its Interconnect Layer. MIPI UniPro is used as a transport layer, and MIPI MPHY is used as a physical layer with the serial DpDn interface. 

UFS 4.0 specification is the latest specification from JEDEC, which leverages UniPro 2.0 and MPHY 5.0 specification standards to achieve the following major improvements:

• Enables up to 4200 Mbps read/write traffic with MPHY 5.0, allowing 23.29 Gbps data rate. 
• High Speed Link Startup, along with Out of Order Data Transfer and BARRIER Command, were introduced to improve system latencies. 
• Data security is enhanced with Advanced RPMB. Advance RPMB also uses the EHS field of the header, which reduces the number of commands required compared to normal RPMB, increasing the bandwidth. 
• Enhanced Device Error History was introduced to ease system integration. 
• File Based Optimization (FBO) was introduced for performance enhancement. 

Along with many major enhancements, UFS 4.0 also maintains backward compatibility with UFS 3.0 and UFS 3.1. 

JEDEC has just announced the UFS 4.0 specification release, quoting Cadence support as a constant contributor in the JEDEC UFS Task Group, actively participating in these specifications development.  

With the availability of the Cadence Verification IP for JEDEC UFS 4.0, MIPI MPHY 5.0 and MIPI UniPro 2.0, early adopters can start working with the provisional specification immediately, ensuring compliance with the standard and achieving the fastest path to IP and SoC verification closure.  

More information on Cadence VIP is available at the Cadence VIP Website. 

Yeshavanth B N 

In a network containing multiple nodes, the need for synchronization between the various nodes is not just instrumental but also a complicated and highly complex process. This process becomes even more tricky if we synchronize the clocks between the Manager and the Peripheral. As we know, in a real-time network, some of the nodes would behave like Managers while some would be a Peripheral. If we must make the communication process smooth, then the local clocks of these nodes must be synchronized. 

The problem with this synchronization is that we have the clock running in the Manager as well. If we send the value of the Manager clock to the Peripheral, the synchronization doesn’t happen as we have a propagation delay of the messages, along with the propagation delay of the electronic circuits of Manager and the Peripheral.  

The cherry on the cake is that these electronic circuit propagation delays are not random and remain constant, so we can add a time offset to it to match the clock. To tackle this challenge, IEEE has come up with a protocol named “Precision Timing Protocol.” 

Operation of PTP: 

To synchronize the clocks, a Sync message is sent by the Manager to the Peripheral, which then timestamps the receiving time of the same. Following this, a ‘Follow up’ message is issued by the Manager stating the timestamp at which the Sync message was sent. 

The Peripheral then finds the difference between the two values and adds this to its current time. After this, the time difference between the Manager and the Peripheral narrows down to only the propagation delay of the messages.  

To overcome this, the Peripheral issues a ‘Delay Request’ to the Manager, and the Manager, in turn, issues a ‘Delay Response.’ Both these messages have the timestamp of when they were issued. The time at which they are received is then noted. Since two messages are sent, one from the Peripheral and the other from the Manager, there are two propagation delays. Then half of this value is our propagation delay. 

The Peripheral then adds this propagation delay to its clock, and hence the clock gets synchronized. 

Advantages of PTP: 

1. It provides accurate time stamping. 
2. It is a well-known clock synchronization protocol. 
3. It provides intensified security inside the premises. 
4. It provides the possibility of setting coordinated actions and synchronized communication. 

There are various versions of PTP that have been developed over time, namely PTPv1, PTPv2, PTPv2_1, and the latest PTP-AS. 

Cadence Verification IP for Ethernet is available to support the newer version of PTP, allowing simulation of the device for efficient IP, SoC, and system-level design verification. Semiconductor companies can start using it to fully verify their controller design and achieve functional verification closure on it within no time. 

The rising customer expectations, intermingling fields and high performance needs can be satisfied with the system based design. An intelligent Systems Design strategy can offer a quicker route to an optimum design and helps to increase designers' productivity and analyzes efficiency by providing the ability to explore the entire design space. Cadence Intelligent System Strategy enables a system design revolution and reduces project schedules with optimized continuous integration.(read more)

One of the key goals for USB4 is to retain compatibility with the existing ecosystem of USB3.2, USB 2.0 and Thunderbolt  products, and the resulting connection scales to the best mutual capability of the devices being connected. USB4 is designed to work with older versions of USB and Thunderbolt . USB4 Fabric support high throughput interconnects of 10 Gbps (for Gen 2) and 20 Gbps (for Gen 3) and supports Thunderbolt 3-compatible rates of 10.3125 Gbps (for Gen 2) and 20.625 Gbps (for Gen 3). It becomes very important to verify the Thunderbolt  backward compatibility with the designs. Though the support of USB4 Interoperability with Thunderbolt  3 (TBT3) is optional in USB4 host or USB4 peripheral device and required USB4 Hub and USB4 Based Dock but it is very essential to work in the existing ecosystem. 

Few Main features of USB4 Interoperability with Thunderbolt  3 (TBT3) Systems

• Support for Bi-Directional Pins & Retimers: TBT3 Active Cables can contain two bidirectional Re-timers which have the capability to send AT Responses on its RX channel. Router connected directly to such Retimer needs to support A Router that is connected directly to a bidirectional Re-timer shall support reception of Transactions on both TX and RX channels. 

• Bounce Mechanism: This feature is used by Router to access the Register Space of a Cable Re-timer that can only be accessed by its Link Partner.
• Asymmetric Negotiation: The Router which connects with Cable Retimers needs to follow Asymmetric TxFFE in Phase 5 of Lane Initialization. 
• USB4 Link Transitions: In TBT3 mode, the configuration of two independent Single Lane Links can be used non-transient state or Single Lane Link just using the Lane1 Adapter.

Cadence has a mature USB4 Verification IP solution that can help in the verification of USB4 designs with TBT3. Cadence has taken an active part in the Cairo group that defined the USB4 specification and has created a comprehensive Verification IP that is being used by multiple members. If you plan to have a USB4-compatible design, you can reduce the risk of adopting new technology by using our proven and mature USB4 Verification IP. Please contact your Cadence local account team, for more details.

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Introduction

Multiphysics is an integral part of the concepts around digital twins. In this post, I want to discuss the mechanical aspects of multiphysics in system simulations, which are critical for 3D-IC, multi-die, and chiplet design.

The physical world in which we live is growing ever more electrified. Think of the transformation that the cell phone has brought into our lives, as has the present-day migration to electronic vehicles (EVs). These products are not only feats of electronic engineering but of mechanical as well, as the electronics find themselves in new and novel forms such as foldable phones and flying cars (eVOTLs). Here, engineering domains must co-exist and collaborate to bring about the best end products possible.

Start with the electronics—chips, chiplets, IC packaging, PCB, and modules. But now put these into a new form factor that can be dropped or submerged in water or accelerated along a highway. What about drop testing, aerodynamics, and aeroacoustics? These largely computational fluid dynamics (CFD) and/or mechanical multiphysics phenomena must also be accounted for. And then how does the drop testing impact the electrical performance? The world of electronics and its vast array of end products is pushing us beyond pure electrical engineering to be more broadly minded and develop not only heterogeneous products but heterogeneous engineering teams as well.

Cadence's Unique Expertise

It's at this crossroad of complexity and electronic proliferation that Cadence shines. Let's take, for example, the latest push for higher-performing high-bandwidth memory (HBM) devices and AI data center expansion. These technologies are growing from several layers to 12, and I can't emphasize enough the importance of teamwork and integrated solutions in tackling the challenges of advanced packaging technologies and how collaboration is shaping the future of semiconductor innovation and paving the way for cutting-edge developments in the industry.

These layered electronics are powered, and power creates heat. Heat needs to be understood, and thus, the thermal integrity issues uncovered along the way must be addressed. However, electronic thermal issues are just the first domino in a chain of interdependencies. What about the thermal stress and warpage that can be caused by the powering of these stacked devices? How does that then lend to mechanical stress and even material fatigue as the temperature cycles from high to low and back through the use of the electronic device? This is just one example in a long list of many...

Cadence Multiphysics Analysis Offerings

The confluence of electrical, mechanical, and CFD is exactly why Cadence expanded into multiphysics at a significant rate starting in 2019 with the announcement of the Clarity 3D Solver and Celsius Thermal Solver products for electromagnetic (EM) and thermal multiphysics system simulations. Recent acquisitions of Numeca, Pointwise, and Cascade (now branded within Cadence as the Fidelity CFD Platform) as well as Future Facilities (now the Cadence Reality Digital Twin product line) are all adding CFD expertise. The recent addition of Beta CAE brings mechanical multiphysics to the suite of solutions available from Cadence. The full breadth of these multiphysics system analyses, spanning EM, thermal, signal integrity/power integrity (SI/PI), CFD, and now mechanical, creates a platform for digital twinning across a wide array of applications. You can learn more by viewing Cadence's Reality Digital Twin platform launch on the keynote stage at NVIDIA's GTC in March, as well as this Designed with Cadence video: NV5, NVIDIA, and Cadence Collaboration Optimizes Data Centers.

Conclusion

Ever more sophisticated electronic designs are in demand to fulfill the needs of tomorrow's technologies, driving a convergence of electrical and mechanical aspects of multiphysics in system simulations. To successfully produce the exciting new products of the future, both domains must be able to collaborate effectively and efficiently. Cadence is fully committed to developing and providing our customers with the software products they need to enable this electrical/mechanical evolution. From EM, to thermal, to SI/PI, CFD, and mechanical, Cadence is enabling digital twinning across a wide array of applications that are forging pathways to the future.

For more information on Cadence's multiphysics system analysis offerings, visit our webpage and download our brochure.

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Power network design and analysis of 3D-ICs is a major challenge due to the complex nature and large size of the power network. In addition, designers must deal with the complexity of routing power through the interposer, multiple dies, through-silicon vias (TSVs), and through-dielectric vias (TDVs).
Cadence’s Integrity 3D-IC Platform and Voltus IC Power Integrity Solution provide a fully integrated solution for early planning and analysis of 3D-IC power networks, 3D-IC chip-centric power integrity signoff, and hierarchical methods that significantly improve capacity and performance of power integrity (PI) signoff while maintaining a very high level of accuracy at signoff. This blog summarizes the typical design challenges faced by today’s 3D-IC designers, as discussed in our recent webinar, “Addressing 3D-IC Power Integrity Design Challenges.” Please click here to view the full webinar.

Major Trends in Advanced Chip Design

From chips to chiplets, stacked die, 3D-ICs, and more, three major trends are impacting advanced semiconductor packaging design. The first is heterogenous integration, which we define as a disaggregated approach to designing systems on chip (SoCs) from multiple chiplets. This approach is similar to system-in-package (SiP) design, except that instead of integrating multiple bare die – including 3D stacking – on a single substrate, multiple IPs are integrated in the form of chiplets on a single substrate.

The second major trend is around new silicon manufacturing techniques that leverage silicon vias (TSVs) and high-density fanout RDL. These advancements mean that silicon is becoming a more attractive material for packaging, especially when high bandwidth and form factor become key attributes in the end design. This brings new design and verification challenges to most packaging engineers who typically work with organic and ceramic substrate materials.

Finally, on the ecosystem side, all the large semiconductor foundries now offer their own versions of advanced packaging. This brings new ways of supporting design teams with technologies like reference flows and PDKs, concepts that have typically been lacking in the packaging community. Cadence has worked with many of the leading foundries and outsourced semiconductor assembly and test facilities (OSATs) to develop multi-chip(let) packaging reference flows and package assembly design kits. The downside is that, with the time restrictions designers are under today, there isn’t enough time to simulate the details of these flows and PDKs further.

For those who must make the best electro/thermal/physical decisions to achieve the best power/performance/area/cost (PPAC), factors can include accurate die size estimations, thermal feasibility, die-to-die interconnect planning, interposer planning (silicon/organic), front-to-front and front-to-back (F2F/F2B) planning, layer stack and electromigration/ IR drop (EMIR)/TSV planning, IO bandwidth feasibility, and system-level architecture selection.

3D-IC Power Network Design and Analysis

The key to success in 3D-IC design is early power integrity planning and analysis. Cadence’s Integrity 3D-IC platform is a high-capacity 3D-IC platform that enables 3D design planning, implementation, and system analysis in a single, unified cockpit. Cadence’s Voltus IC Power Integrity Solution is a comprehensive full chip electromigration, IR drop, and power analysis solution. With its fully distributed architecture and hierarchical analysis capabilities, Voltus provides very fast analysis and has the capacity to handle the largest designs in the industry. Typically, 3D-IC PDN design and analysis is performed in four phases, as shown in Figure 1.

Phase 1 - Perform early power delivery network (PDN) exploration with each fabric’s PDN cascaded in system PI with early circuit models.

Phase 2 – Plan 3D-IC PDNs in Cadence’s Integrity 3D-IC platform, including micro bumps, TSVs, and through dielectric vias (TDVs), power grid synthesis for dies, and early rail analysis and optimization.

Phase 3 – Perform full chip-centric signoff in Voltus with detailed die, interposer, and package models, including chip die models, while keeping some dies flat.

Phase 4 – Perform full system-level signoff with Cadence’s Sigrity SystemPI using detailed extracted package models from Sigrity XtractIM, board models from Sigrity PowerSI or Clarity 3D Solver, interposer models from XtractIM or Voltus, and chip power models from Voltus.

Figure 1. 3D-IC PDN design and analysis phases

3D-IC Chip-Centric Signoff

The integration of Integrity 3D-IC and Voltus enables chip-centric early analysis and signoff. Figure 2 and Figure 3 highlight the chip centric early PI optimization and signoff flows. In early analysis, the on-chip power networks are synthesized, and the micro bumps and TSVs can be placed and optimized. In the signoff stage, all the detailed design data is used for power analysis, and detailed models are extracted and used for package, interposer, and on-die power networks.

Figure 2. Early chip-centric PI analysis and optimization flow

Figure 3. Chip-centric 3D-IC PI signoff

Hierarchical 3D-IC PI Analysis

To improve the capacity and performance of 3D-IC PI analysis, Voltus enables hierarchical analysis using chiplet models. Chiplet models can be reduced chip models in spice format or more accurate xPGV models which are highly accurate proprietary models generated by Voltus. With xPGV models, the hierarchical PI analysis has almost the same accuracy as flat analysis but offers 10X or higher benefit in runtime and memory requirements.

Conclusion

This blog has highlighted the major design trends enabled by advanced 3D packaging and the design challenges arising from these advancements. The design of power delivery networks is one of these major challenges. We have discussed Cadence solutions to overcome this PI challenge. To learn more, view our recent webinar, "Addressing 3D-IC Power Integrity Design Challenges" and visit the Voltus web page.

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Melika Roshandell, Cadence product marketing director for the Celsius Thermal Solver, recently published an article in Designing Electronics discussing how the use of modern thermal analysis techniques can help engineers meet the challenges of today’s complex electronic designs, which require ever more functionality and performance to meet consumer demand.

Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These requirements make scaling traditional, flat, 2D-ICs very challenging. With the recent introduction of 3D-ICs into the electronic design industry, IC vendors need to optimize the performance and cost of their devices while also taking advantage of the ability to combine heterogeneous technologies and nodes into a single package. While this greatly advances IC technology, 3D-IC design brings about its own unique challenges and complexities, a major one of which is thermal management.

To overcome thermal management issues, a thermal solution that can handle the complexity of the entire design efficiently and without any simplification is necessary. However, because of the nature of 3D-ICs, the typical point tool approach that dissects the design space into subsections cannot adequately address this need. This approach also creates a longer turnaround time, which can impact critical decision-making to optimize design performance. A more effective solution is to utilize a solver that not only can import the entire package, PCB, and chiplets but also offers high performance to run the entire analysis in a timely manner.

Celsius Thermal Management Solutions

Cadence offers the Celsius Thermal Solver, a unique technology integrated with both IC and package design tools such as the Cadence Innovus Implementation System, Allegro PCB Designer, and Voltus IC Power Integrity Solution. The Celsius Thermal Solver is the first complete electrothermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. Based on a production-proven, massively parallel architecture, the Celsius Thermal Solver also provides end-to-end capabilities for both in-design and signoff methodologies and delivers up to 10X faster performance than legacy solutions without sacrificing accuracy.

By combining finite element analysis (FEA) for solid structures with computational fluid dynamics (CFD) for fluids (both liquid and gas, as well as airflow), designers can perform complete system analysis in a single tool. For PCB and IC packaging, engineering teams can combine electrical and thermal analysis and simulate the flow of both current and heat for a more accurate system-level thermal simulation than can be achieved using legacy tools. In addition, both static (steady-state) and dynamic (transient) electrical-thermal co-simulations can be performed based on the actual flow of electrical power in advanced 3D structures, providing visibility into real-world system behavior.

Designers are already co-simulating the Celsius Thermal Solver with Celsius EC Solver (formerly Future Facilities’ 6SigmaET electronics thermal simulation software), which provides state-of-the-art intelligence, automation, and accuracy. The combined workflow that ties Celsius FEA thermal analysis with Celsius EC Solver CFD results in even higher-accuracy models of electronics equipment, allowing engineers to test their designs through thermal simulations and mitigate thermal design risks.

Conclusion

As systems become more densely populated with heat-dissipating electronics, the operating temperatures of those devices impact reliability (device lifetime) and performance. Thermal analysis gives designers an understanding of device operating temperatures related to power dissipation, and that temperature information can be introduced into an electrothermal model to predict the impact on device performance. The robust capabilities in modern thermal management software enable new system analyses and design insights. This empowers electrical design teams to detect and mitigate thermal issues early in the design process—reducing electronic system development iterations and costs and shortening time to market.

To learn more about Cadence thermal analysis products, visit the Celsius Thermal Solver product page and download the Cadence Multiphysics Systems Analysis Product Portfolio.

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Cadence is super excited to announce SPB 23.1 release —Your freedom to design boldly!  

These tools help engineers build better PCBs faster with the new 3D engine and optimized interface.  

We have been hard at work to bring you this release and believe that it will help you take control of the PCB design process with the powerful new features in Allegro X APD like: 

• Packaging Support in 3DX Canvas 

• 3DX Wire DRCs 

• Aligning Components by Offset 

• Text Wizard Enhancements 

• Device File Reuse for Existing Components for Netlist and Logic Import 

Watch this space to know all about What’s New in SPB 23.1.  

Regards 

Team PCBTech 

Cadence Design System 

For individuals, small businesses, or teams, START YOUR FREE TRIAL. 

Does anyone know how to not include a pbar in a constraint manager analysis? I have some relative delay constraints applied on a group of differential nets. When I analyze the design these all show an error. If I delete the plating bar from the design they are all passing. The plating bar gets generated on the Substrate Geometry / Plating_Bar class. I understand that I could just delete the plating bar to verify the constraint but the issue is when I archive this design I would like it to be clean meaning it is in the final state for manufacturing AND passing all constraints according to design reviews.

Anyone have an idea? 

Thank you!

Does anyone know whether it is possible to have multiple contact points for a bond wire on a large die pad? Note: This is different from adding multiple wires which I will also be doing. I need to add multiple bond connections to the same large die pad for redundancy connections to each pad for each wire. I have a large die pad which I need to have 5 wires with each wire having 3 bond connections to the same die pad.

Starting SPB 23.1, in Allegro X PCB Editor and Allegro X Advanced Package Designer, you can align components by using offset mode. Earlier only spacing mode was available.

Follow these steps to Align Components using Offset Mode:

1. Set Application Mode to Placement Edit.
2. Drag the components that need to be aligned and right-click and choose Align Components.
3. Now, in the Options tab, you will notice Spacing Section with Equal Offset. You can equally and individually offset the components by using the +/- buttons for increment or decrement.

Have you ever encountered ERROR(SPMHNI-67) while importing logic? If yes, you might already know that you had to export libraries of the design and make sure that paths (devpath, padpath, and psmpath) include the location of exported files.  

Starting in SPB23.1, if you go to File > Import > Logic/Netlist and click on the Other tab, you will see an option, Reuse device files for existing components. 

After selecting this option, ERROR(SPMHNI-67) will no longer be there in the log file, because the tool will automatically extract device files and seamlessly use them for newly imported data. In other words, SPB_23.1 lets you reuse the device / component definitions already in the design without first having to dump libraries manually. An excellent improvement, don’t you think?  

Have you ever thought of a handy utility to specify all necessary transmission line parameters to decide upon the stackup?   

Starting SPB 23.1, a handy feature Transmission Line Calculator, is built into Allegro X Advanced Package Designer (Allegro X APD). This feature will require either an SiP Layout license or can be accessed through SiP Layout Bundle. 

From the Analyze dropdown menu in the 23.1 Allegro X APD toolbar, you can choose Transmission Line Calculator. 

You can use this calculator to help decide constraints and stackup for laminate-based PCB or Packages. You can calculate the correct stackup material and width/spacing to meet any requirements that may be later entered in a constraint. This is truly a calculated number and not a true field solver. 

The different types of calculations that the Transmission Line Calculator can provide are Microstrip, Embedded microstrip, Stripline, CPW (Coplanar), FGCPW (frequency-dependent Coplanar), Asymmetric stripline, Coupled microstrip (Differential Pair), Coupled stripline (Differential Pair), and Dual striplines. 

This feature is important for customers relying on fabricators/spreadsheets to provide this information or need to test a quick spacing/width as per the impedance value. 

Let us know your comments on this new feature in 23.1 Allegro X APD. 

Starting SPB 23.1, Allegro X APD lets you import/export the symbol and component properties by using Die Text-In/Out wizards. 

Exporting the symbol 

You can export the symbol by using File > Export > Die Text-Out Wizard. 

In the Die Text-Out Wizard window, you can see the newly added options, that is, Component Properties and Symbol Properties. 

This entire information including the properties will be saved in a text file. 

Importing the symbol 

You can import the same text file in Allegro X APD by using Die Text-In Wizard. 

Choose the text file you want to import. 

Symbol properties added in the text file will be visible in the Die Text-In Wizard window. 

hello, help me!

There are many change in the bump design. I want to design bump by APD.

The bump(die) is a stagger , create it by die generator. 

Because，the pin is not isometric. In order to RDL routing, so the bump is not isometric.

I move the symbol pin in APD symbol edit（as show in the picture）,  and selected symbol RBM write device file, write library symbol.

Export the bga text( bga text out) ,But the bump is not modified, the bump is still stagger.

Can you help me!

pitch2> pitch1

thanks

The vision manager is good tool for routing check. but no quickly or effective  tool to fix or optimize this  problems to be optimized.

For example, parallel Gap less than preferred, min seg/Arc length,uncoupled diff-pair segs，and so on.

I only know use spread between voids to fix the non-optimized segs. in fact it is inefficient.

the parallel gap less than preferred is only to slice evry trace, its inefficient.

If i set the paraller gap less than 50um, Is there any tool to quickly fix these problems（gap less than 50um）?

For other problems，i can use tool to quickly fix the min seg/Arc length，uncoupled diff pair segs，accoding to select by polygon or select  by windows.

Hi，

There are mang components in BGA ball side of flipchip package.

Are there DFA check space of compont body or pin soldermask to BGA ball or BGA PAD or bga  soldermask in allegro APD?

I only find space of compont to compont in APD DFA. 

Hello, SKILL experts. 

I'm studying SKILL language to build some useful function in APD+.

Now, I want to execute 'Import Sub-drawing' function in new form.

But I cannot find how to do execute APD+ embedded function in a field of new form. 

Has anyone experienced this or idea to solve this problem? 

The DBDoctor application checks the database for errors and other problems, and presents a report about them. DBDoctor supports .brd, .mcm, .mdd, .psm, .dra, .pad, .sav, and .scf databases.

DBDoctor can:

• Analyze and fix database problems.
• Eliminate duplicate vias.
• Perform batch design rule checking (DRC).
• Upgrade databases more than one revision old.

To verify the integrity of a drawing database at any time during the design cycle, run DBDoctor at regular intervals but make sure you always run it after completing a design.

You can run DBDoctor to verify work in progress, or from a terminal window outside the layout editor, perhaps to check multiple input designs in batch mode by using wildcards and various switches. You do not have to run the layout editor to use DBDoctor.

To run this from Allegro X APD and Allegro PCB Editor, go to Tools > Database Check.

You can also go to the Start menu and select Cadence PCB Utilities 2023 > PCB DB Doctor 2023.

You can also use the following command to run DBDoctor in batch mode in the system command prompt:

dbdoctor [-check_only] [-drc] [-drc_only] [-shapes][-no_backup] [-outfile <newboardname.brd>]>

Comment below if you want to know more about this command and its integration with SKILL programming!!