This is the 22nd installment of The Rationalist, my column for the Times of India.

Trade wars are on the rise, and it’s enough to get any nationalist all het up and excited. Earlier this week, Narendra Modi’s government announced that it would start imposing tariffs on 28 US products starting today. This is a response to similar treatment towards us from the US.

There is one thing I would invite you to consider: Trump and Modi are not engaged in a war with each other. Instead, they are waging war on their own people.

Let’s unpack that a bit. Part of the reason Trump came to power is that he provided simple and wrong answers for people’s problems. He responded to the growing jobs crisis in middle America with two explanations: one, foreigners are coming and taking your jobs; two, your jobs are being shipped overseas.

Both explanations are wrong but intuitive, and they worked for Trump. (He is stupid enough that he probably did not create these narratives for votes but actually believes them.) The first of those leads to the demonising of immigrants. The second leads to a demonising of trade. Trump has acted on his rhetoric after becoming president, and a modern US version of our old ‘Indira is India’ slogan might well be, “Trump is Tariff. Tariff is Trump.”

Contrary to the fulminations of the economically illiterate, all tariffs are bad, without exception. Let me illustrate this with an example. Say there is a fictional product called Brump. A local Brump costs Rs 100. Foreign manufacturers appear and offer better Brumps at a cheaper price, say Rs 90. Consumers shift to foreign Brumps.

Manufacturers of local Brumps get angry, and form an interest group. They lobby the government – or bribe it with campaign contributions – to impose a tariff on import of Brumps. The government puts a 20-rupee tariff. The foreign Brumps now cost Rs 110, and people start buying local Brumps again. This is a good thing, right? Local businesses have been helped, and local jobs have been saved.

But this is only the seen effect. The unseen effect of this tariff is that millions of Brump buyers would have saved Rs 10-per-Brump if there were no tariffs. This money would have gone out into the economy, been part of new demand, generated more jobs. Everyone would have been better off, and the overall standard of living would have been higher.

That brings to me to an essential truth about tariffs. Every tariff is a tax on your own people. And every intervention in markets amounts to a distribution of wealth from the people at large to specific interest groups. (In other words, from the poor to the rich.) The costs of this are dispersed and invisible – what is Rs 10 to any of us? – and the benefits are large and worth fighting for: Local manufacturers of Brumps can make crores extra. Much modern politics amounts to manufacturers of Brumps buying politicians to redistribute money from us to them.

There are second-order effects of protectionism as well. When the US imposes tariffs on other countries, those countries may respond by imposing tariffs back. Raw materials for many goods made locally are imported, and as these become expensive, so do those goods. That quintessential American product, the iPhone, uses parts from 43 countries. As local products rise in price because of expensive foreign parts, prices rise, demand goes down, jobs are lost, and everyone is worse off.

Trump keeps talking about how he wants to ‘win’ at trade, but trade is not a zero-sum game. The most misunderstood term in our times is probably ‘trade-deficit’. A country has a trade deficit when it imports more than what it exports, and Trump thinks of that as a bad thing. It is not. I run a trade deficit with my domestic help and my local grocery store. I buy more from them than they do from me. That is fine, because we all benefit. It is a win-win game.

Similarly, trade between countries is really trade between the people of both countries – and people trade with each other because they are both better off. To interfere in that process is to reduce the value created in their lives. It is immoral. To modify a slogan often identified with libertarians like me, ‘Tariffs are Theft.’

These trade wars, thus, carry a touch of the absurd. Any leader who imposes tariffs is imposing a tax on his own people. Just see the chain of events: Trump taxes the American people. In retaliation, Modi taxes the Indian people. Trump raises taxes. Modi raises taxes. Nationalists in both countries cheer. Interests groups in both countries laugh their way to the bank.

What kind of idiocy is this? How long will this lose-lose game continue?

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

This is the 23rd installment of The Rationalist, my column for the Times of India.

I had a strange dream last night. I dreamt that the government had passed a law that made using laptops illegal. I would have to write this column by hand. I would also have to leave my home in Mumbai to deliver it in person to my editor in Delhi. I woke up trembling and angry – and realised how Indian farmers feel every single day of their lives.

My column today is a tale of two satyagrahas. Both involve farmers, technology and the freedom of choice. One of them began this month – but first, let us go back to the turn of the millennium.

As the 1990s came to an end, cotton farmers across India were in distress. Pests known as bollworms were ravaging crops across the country. Farmers had to use increasing amounts of pesticide to keep them at bay. The costs of the pesticide and the amount of labour involved made it unviable – and often, the crops would fail anyway.

Then, technology came to the rescue. The farmers heard of Bt Cotton, a genetically modified type of cotton that kept these pests away, and was being used around the world. But they were illegal in India, even though no bad effects had ever been recorded. Well, who cares about ‘illegal’ when it is a matter of life and death?

Farmers in Gujarat got hold of Bt Cotton seeds from the black market and planted them. You’ll never guess what happened next. As 2002 began, all cotton crops in Gujarat failed – except the 10,000 hectares that had Bt Cotton. The government did not care about the failed crops. They cared about the ‘illegal’ ones. They ordered all the Bt Cotton crops to be destroyed.

It was time for a satyagraha – and not just in Gujarat. The late Sharad Joshi, leader of the Shetkari Sanghatana in Maharashtra, took around 10,000 farmers to Gujarat to stand with their fellows there. They sat in the fields of Bt Cotton and basically said, ‘Over our dead bodies.’ ¬Joshi’s point was simple: all other citizens of India have access to the latest technology from all over. They are all empowered with choice. Why should farmers be held back?

The satyagraha was successful. The ban on Bt Cotton was lifted.

There are three things I would like to point out here. One, the lifting of the ban transformed cotton farming in India. Over 90% of Indian farmers now use Bt Cotton. India has become the world’s largest producer of cotton, moving ahead of China. According to agriculture expert Ashok Gulati, India has gained US$ 67 billion in the years since from higher exports and import savings because of Bt Cotton. Most importantly, cotton farmers’ incomes have doubled.

Two, GMO crops have become standard across the world. Around 190 million hectares of GMO crops have been planted worldwide, and GMO foods are accepted in 67 countries. The humanitarian benefits have been massive: Golden Rice, a variety of rice packed with minerals and vitamins, has prevented blindness in countless new-born kids since it was introduced in the Philippines.

Three, despite the fear-mongering of some NGOs, whose existence depends on alarmism, the science behind GMO is settled. No harmful side effects have been noted in all these years, and millions of lives impacted positively. A couple of years ago, over 100 Nobel Laureates signed a petition asserting that GMO foods were safe, and blasting anti-science NGOs that stood in the way of progress. There is scientific consensus on this.

The science may be settled, but the politics is not. The government still bans some types of GMO seeds, such as Bt Brinjal, which was developed by an Indian company called Mahyco, and used successfully in Bangladesh. More crucially, a variety called HT Bt Cotton, which fights weeds, is also banned. Weeding takes up to 15% of a farmer’s time, and often makes farming unviable. Farmers across the world use this variant – 60% of global cotton crops are HT Bt. Indian farmers are so desperate for it that they choose to break the law and buy expensive seeds from the black market – but the government is cracking down. A farmer in Haryana had his crop destroyed by the government in May.

On June 10 this year, a farmer named Lalit Bahale in the Akola District of Maharashtra kicked off a satyagraha by planting banned seeds of HT Bt Cotton and Bt Brinjal. He was soon joined by thousands of farmers. Far from our urban eyes, a heroic fight has begun. Our farmers, already victimised and oppressed by a predatory government in countless ways, are fighting for their right to take charge of their lives.

As this brave struggle unfolds, I am left with a troubling question: All those satyagrahas of the past by our great freedom fighters, what were they for, if all they got us was independence and not freedom?

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

Read on to know about the Operating Point Parameters Summary window that gives you a one-stop view of the categorized and tabulated details on all operating point parameters in your design. This window improves your review cycle with its many benefits.(read more)

During a mixed-signal simulation, the analog engine usually dominates the simulation time and resources. If you need to run only the analog engine in several windows, or if you would like to to run multiple tests of the same circuit with different stimuli or test pattern, then you need to run the simulation multiple times. View this blog to know more about the the two advanced technologies that Spectre AMS Designer provides to help you improve the efficiency of your mixed-signal designs and to increase the simulation speed.(read more)

This blog describes an efficient way to name the histories saved by the simulation runs in Virtuoso ADE Assembler.(read more)

Read this blog to know how you can easily create and insert connect modules using Spectre AMS Designer with the Verilog-AMS standard language defined by Accellera. (read more)

At a bustling Cadence event, we met Adrian, an intern at a startup who immerses himself in Cadence tools for his research and work.

Adrian was enthusiastic about the innovative technologies at his disposal but faced a significant challenge: internet access was limited to a single machine for new joiners, forcing interns to wait in line for their turn to use online resources.

Adrian's excitement soared when he discovered a game-changing solution: Doc Assistant. The cloud-based help viewer, Doc Assistant, ships with all Cadence tools, enabling Adrian to access help resources offline from any machine equipped with the software. This meant Adrian could continue his research and work seamlessly, irrespective of internet availability!

Meeting Cadence users and customers at such events has given us the opportunity to showcase how they can benefit from the diverse features that Doc Assistant offers.

With that note, welcome back to our Doc Assistant A-Z blog series! In Part 1, we explored key features and benefits that our innovative viewer brings to the table. Today, in Part 2, we'll dive deeper into the advanced functionalities and customization options that make Doc Assistant indispensable for its users.

Whether you're looking to streamline your workflow or enhance your user experience, this blog will provide the insights you need to fully leverage the capabilities of our documentation viewer. Let’s get started!

What Makes Doc Assistant Stand Out?

Here are a few (more) cool features of Doc Assistant!

That's not all. We have more coming your way. Until next time, take care and stay tuned for our next edition!

Want to Know More?

For any questions or general feedback, write to docassistant.support@cadence.com.

Subscribe to receive email notifications about our latest Custom IC Design blog posts.

Happy reading!

-Priya Sriram, on behalf of the Doc Assistant Team

Read this blog to know more about the innovation behind Universal Connect Modules (UCM).(read more)

Welcome back to the Doc Assistant A-Z blog series!

Since the launch of Doc Assistant, we've been gathering feedback and input from our customers regarding their experiences with our latest documentation viewer. My interaction with Ralf was particularly useful and interesting.

Ralf is a design engineer who works on complex schematics and intricate layouts. For each release, he is challenged with the task of verifying the tool and feature changes across multiple releases. He shared with me that he has been using Doc Assistant’s capabilities to help him achieve this.

Ralf explained that he utilizes Doc Assistant to open and compare documents from different releases side-by-side, seamlessly tracking updates across multiple releases and verifying those updates in his Cadence tools. Additionally, in Doc Assistant’s online mode, he compares documents across previous tool versions, ensuring a thorough review of any changes. Finally, he was happy to share with me that Doc Assistant features have helped him significantly reduce the time he spends on identifying such changes.

You, of course, can also achieve such productivity gains using several Doc Assistant features designed to help simplify such tasks!

In previous editions of this blog series, we looked at some key features and benefits of Doc Assistant. If you've missed these editions, I would highly recommend that you read them:

• Doc Assistant A-Z: Making the Most of the Cadence Cloud-Based Help Viewer: Part 1
• Doc Assistant A-Z: Making the Most of the Cadence Cloud-Based Help Viewer: Part 2
  

In this third installment, we're diving into some more of Doc Assistant's key capabilities.

To learn more about how to use the above features, check out the Doc Assistant User Guide.

These are just a few of the productivity gain features in Doc Assistant. We’ll cover more in the next blog in the series.

Want to Know More?

If you have any feedback on Doc Assistant or would like to request more information or a demo, please contact docassistant.support@cadence.com.

Subscribe to receive email notifications about our latest Custom IC Design blog posts.

Happy reading!

- Priya Sriram, on behalf of the Doc Assistant Team

Hi 

I am looking into chamfering the edge of PCB for Board edge connectors. I have performed fillet command earlier but new to chamfering.

Below is the description :

As seen above, the PCB edge are chamfered in thickness as well as at the corners.

Using OrCAD PCB hotfix S023.

Hello Fellow PCB Designers,

We have a 10 layer PCB design that originated in Pads and was converted over to Allegro 17.4, this is an old design but is manufacturable and works perfectly fine.  When I try to generate a Gerber for the Top or Bottom layers

the Gerber comes out fine.  But Most of the middle layers are Etch's and via's for power and grounds, but the Gerber's come mostly blank, there might be some details, but in the Gerber view everything is displayed correctly.

The design does have many close spacings, I have not changed anything in the constrains manager yet, turned off a lot of the DRC's, but thinking there might be something wrong with the constrains.

  I find that the CSet is set to 2_18, not sure yet what this means, also there are many of these definitions, PCS 3,4,5,ect, are the same as CSet 2_18 any suggestions would be great, we are currently looking into this, have seen

that even small change in constraint manager can cause long processing and even Allegro crashing, this is a large project.

Thanks Much, Thanks, Mike Pollock.

Hi,

So I was trying to update the title block of a schematic that I have. The title block that was on there was out of date . I clicked on place --> title block and was able to find the title block that I need. I also have a .OLB file that contains that title block. Then I created a Netlist with the old BRD file as the input file (To keep it as is but modify changes) but when I do that I still do not see / cannot place the title block that I need. Under Place --> format symbols in Allegro , I do see a title block that is coming from the database (But it's the old one). I don't know what to do at this point and would appreciate any tips. I did make sure that the path to where the library is , is defined in the user preferences. 
I also tried copying the title block under the library folder in capture before creating my Netlist and that did not work either.

Thank you all.

I'd like to be able to edit a footprint for a part in my design without needing to find the footprint filepath and directly open that file in PCB Editor. I see that I can view footprints from Capture, and that doing so shows me the footprint path, but I can't find any way to launch the editor. Is there any way to go directly from a part in a Capture schematic or a placed part in a PCB Editor board design to editing that part's footprint?

Hello..

I'm updating part in part editor in orcad capture, and I wonder how to align pin numbers using menu or tcl/tk command.

Please, let me know. Thank you.

I'm not able to export a CIS Standard BOM to a Microsoft 365 Excel (business subscription, version 2111).
Selecting the "Export BOM report to Excel" option opens a new Excel window, but OrCAD (17.4-2019 S023) won't fill it with any data...

I tried it on a different PC with Microsoft Office Professional Plus 2019 Excel (strangely the version number is the same: 2111) and with OrCAD 17.4-2019 S016 and it worked flawlessly.

Does anybody experiencing the same issue?
Does the Excel variant, the OrCAD version or the PC itself causing this?
Thanks for any help!

The default position of the pin number is incorrect.

I have managed to convert our old schematic and PCD file to from Layout 16.2 to 17.4

I have exported the footprints and moved them to the correct lib directory. 

I get no DRC errors and I can build a new netlist file. The problem is I can't get the PCB editor to update using the new netlist and get the following error:

I cannot figure out how to fix the Name is too long error. 

(---------------------------------------------------------------------)

(                                                                     )

(    Allegro Netrev Import Logic                                      )

(                                                                     )

(    Drawing          : 70055R2.brd                                   )

(    Software Version : 17.4S023                                      )

(    Date/Time        : Tue Dec 14 18:54:25 2021                      )

(                                                                     )

(---------------------------------------------------------------------)

------ Directives ------------

Ripup etch:                  Yes

Ripup delete first segment:  No

Ripup retain bondwire:       No

Ripup symbols:               IfSame

Missing symbol has error:    No

DRC update:                  Yes

Schematic directory:         'C:/AFS/70055 PCB Test 2'

Design Directory:            'C:/AFS/70055 PCB Test 2'

Old design name:             'C:/AFS/70055 PCB Test 2/70055R2.brd'

New design name:             'C:/AFS/70055 PCB Test 2/70055R2.brd'

CmdLine: netrev -$ -i C:/AFS/70055 PCB Test 2 -x -u -t -y 2 -h -z -q netrev_constraint_report.xml C:/AFS/70055 PCB Test 2/#Taaaaae57776.tmp

------ Preparing to read pst files ------

Starting to read C:/AFS/70055 PCB Test 2/pstchip.dat 

   Finished reading C:/AFS/70055 PCB Test 2/pstchip.dat (00:00:00.02)

Starting to read C:/AFS/70055 PCB Test 2/pstxprt.dat 

   Finished reading C:/AFS/70055 PCB Test 2/pstxprt.dat (00:00:00.00)

Starting to read C:/AFS/70055 PCB Test 2/pstxnet.dat 

   Finished reading C:/AFS/70055 PCB Test 2/pstxnet.dat (00:00:00.00)

------ Oversights/Warnings/Errors ------

#1   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_9_SWITCH_OTTO_ALT_SW DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_9_SWITCH_OTTO_ALT_SW DP' has library errors. Unable to transfer to Allegro.

#2   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_10_SWITCH_OTTO_LIGHTS_SW DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_10_SWITCH_OTTO_LIGHTS_S' has library errors. Unable to transfer to Allegro.

#3   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_7_SWITCH_OTTO_ALT_SW DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_7_SWITCH_OTTO_ALT_SW DP' has library errors. Unable to transfer to Allegro.

#4   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_3_SWITCH_OTTO_MASTER_SW DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_3_SWITCH_OTTO_MASTER_SW' has library errors. Unable to transfer to Allegro.

#5   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_6_SWITCH_OTTO_LIGHTS_SW DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_6_SWITCH_OTTO_LIGHTS_SW' has library errors. Unable to transfer to Allegro.

#6   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_3_SWITCH_OTTO_MASTER_DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_3_SWITCH_OTTO_MASTER_DP' has library errors. Unable to transfer to Allegro.

#7   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'CONNECTOR DB15_DSUBVPTM15_CONNECTOR DB15': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'CONNECTOR DB15_DSUBVPTM15_CONNE' has library errors. Unable to transfer to Allegro.

#8   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'CONNECTOR DB9_DSUBVPTM9_CONNECTOR DB9': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'CONNECTOR DB9_DSUBVPTM9_CONNECT' has library errors. Unable to transfer to Allegro.

#9   ERROR(SPMHNI-175): Netrev error detected.

ERROR(SPMHDB-195): Error processing 'M6': Text line is outside of the extents..

------ Library Paths ------

MODULEPATH =  . 

           C:/Cadence/SPB_17.4/share/local/pcb/modules 

PSMPATH =  . 

           symbols 

           .. 

           ../symbols 

           C:/Cadence/SPB_17.4/share/local/pcb/symbols 

           C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols 

           C:/Cadence/SPB_17.4/share/pcb/allegrolib/symbols 

           C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols 

PADPATH =  . 

           symbols 

           .. 

           ../symbols 

           C:/Cadence/SPB_17.4/share/local/pcb/padstacks 

           C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols 

           C:/Cadence/SPB_17.4/share/pcb/allegrolib/symbols 

           C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols 

------ Summary Statistics ------

#10  Run stopped because errors were detected

netrev run on Dec 14 18:54:25 2021

   DESIGN NAME : '70055R2'

   PACKAGING ON Nov  2 2021 14:32:04

   COMPILE 'logic'

   CHECK_PIN_NAMES OFF

   CROSS_REFERENCE OFF

   FEEDBACK OFF

   INCREMENTAL OFF

   INTERFACE_TYPE PHYSICAL

   MAX_ERRORS 500

   MERGE_MINIMUM 5

   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'

   NET_NAME_LENGTH 24

   OVERSIGHTS ON

   REPLACE_CHECK OFF

   SINGLE_NODE_NETS ON

   SPLIT_MINIMUM 0

   SUPPRESS   20

   WARNINGS ON

 10 errors detected

 No oversight detected

 No warning detected

cpu time      0:00:27

elapsed time  0:00:00

I have a small board that is not readable even though the document is 11' x 17'. Is there a way I could expand/magnify the board along with the components on them to make them legible? 
I have created a new film and is displaying the bottom and top side of the board but the board is too small and the components are not legible. Perhaps there is a way to upscale it or expand it?
Please note I have other stuff in the document that I am not showing , notes and other things, and I am trying to make just the boards look bigger in some way.
I do have a PDF image of the same file where the board appears to be MUCH bigger and is fully legible and I am trying to match that.

Thank you all.

Hi,

I found that under the Dark Theme of PCB Environment Editor 17.4,

the window background is not all dark, resulting in unclear text display。

As shown in the figure below：

Hi,

I have a question about printing noise summary via maestro output expressions.

How can I print noise data using output expressions, for multiple levels of the hierarchy?

I have found this article which describe the procedure using ocnGenNoiseSummary() function: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000007MViHEAW&pageName=ArticleContent

I see also Andrew Beckett referring to the above mentioned article as a solution to a similar question: community.cadence.com/.../noise-summary-per-instance

However, this seems to work only if I'm to extract noise data from a single level of hierarchy.

If I have the output expression "ocnGenNoiseSummary(2 ?result 'hbnoise)", it will generate a "noisesummary" directory under results directory for a hierarchy level of 2.

If I am to extract data from various hierarchy levels, I should be able to generate multiple noise summary directories, such as noisesummary1, noisesummary2 where they correspond to "ocnGenNoiseSummary(1 ?result 'hbnoise)" & "ocnGenNoiseSummary(2 ?result 'hbnoise)", respectively. However this does not seem to be possible.

Can you please advice? Thanks.

My Cadence version: IC23.1-64b.ISR7.27

BR,

Denizhan Karaca

Hi

In the environment I'm currently working, axes are shown for schematic, symbol, and layout views.For schematics and symbols, I'd prefer a dim gray, such that the axes are just visible but not dominant. For the layout, I'd prefer a brighter color. Is there a way to realize this? So far when I change the color of the 'axis' layer in the display resource editor, the axes in all three views get changed together:

Thanks very much for your input!

Dear all,

I defined two design variables in ADE Assembler, say V1 and V2, that define the voltage 1 and voltage 2 of a "vpulse" voltage source in my schematic.

Then, I define V1 = 1.0, and V2 = 2.0, run a transient simulation, and everything is as expexcted. The source provides pulses between 1.0 V and 2.0 V.

Next, I set V1 = 1.0:0.5:1.5, thereby creating a parametric sweep with 1.0 V and 1.5 V for V1. I keep V2 at 2.0 V. Then the simulation fails, and all I get is "netl err" in my Output Expressions and an error message that the results directory does not exist and nothing can be plotted: This is reasonable, as the results directory is deleted on starting a new simulation, and as there is no simulation result, none of my output expressions can be plotted.

WARNING (OCN-6040): The specified directory does not exist, or the directory does not contain valid PSF results.
        Ensure that the path to the directory is correct and the directory has a logFile and PSF result files.
WARNING (ADE-1065): No simulation results are available.
ERROR (WIA-1175): Cannot plot waveform signals because no waveform data is available for plotting.
One of the possible reasons can be that 'Save' check box for these signals are not selected in the Outputs Setup pane. Ensure that these check boxes are selected before you run the simulation.

Normally, this kind of para,metric sweep is not a problem, I have done this many times before. There must be something special in THIS PARTICULAR test bench or simulator setup. The trouble is, I don't get any useful error messages.

Does anyone know what might be the problem here OR where to find useful information to investigate further (log files stored somewhere)? Thank you!

Regards,

Volker

P.S. Using Corners instead does not help either. Running it through all values by hand works, though.

Hi,

I have a LEF file with simple definitions of pad design which uses M8, M9, and AP layers. However, I failed to import the design with CIW > Import > LEF... as I encountered "ERROR: (OALEFDEF-90019): Ignoring the line 30 in the layer map file ... as it contains a syntax error. Each entry in the layer map file must have two values, LEFLayerName and OALayerNumber separated by a blank space." All lines in the file report the same OALEFDEF-90019 error.

The tech.layermap file looks like this:


# techLayer       techPurpose     stream# dataType

ref drawing 0 0
DNW drawing 1 0
PW drawing 2 0

Hi, 

When I try to run Monte Carlo it gives me a 3 items message for possible failure:

1. It says the machine selected in the current job setup policy isnot reachable

2. The Cadence hierarchy is not detected, not installed properly. or

3. Job start script (with a path and a name like swiftNetlistService#) is not found on the remote machines.

Any recommendation on how to fix this?

I have tried replicating the setup described in a previous post (here), with the proposed solution.

The MDL measurements return a value of 0 for all exported result but the first.

Using Viva I can actually see the correct value for each contribution.

I am using :
- Spectre 23.1.0.538.isr10
- Viva IC23.1-64b.ISR8.40

What should I do differently?

Thanks!

**** test.measure ****

Measurement Name   :  noi_test
Analysis Type      :  noise
noi_total             =  6.9282e-06
r1_flicker            =  0
r1_thermal            =  0
r1_total              =  0
r2_flicker            =  0
r2_thermal            =  0
r2_total              =  0

IC 23.1-64b.ISR8.40

Hi all, I'm trying to run an stb analysis in a dspf extracted view via Probe terminal. The instance exist in the dspf and I already prepended the X that is placed in the dspf extraction.

Spectre complains with the following error:

Error found by spectre during STB analysis `stb'.
    ERROR (SPECTRE-16408): The probe parameter must be specified to perform stability analysis.

Analysis `stb' was terminated prematurely due to an error.

What is missing here?

How can I place stacked vias with the size exact same cut width without metals around?
As the red part only in the image below?

For reasons too complicated to go into here, I need to generate the code for a veriloga view from a outside the normal Verilog-A editor. I would start with an "empty" veriloga view generated from the symbol in the normal way so I get the port order correct, then use external code to provide "guts" of the veriloga view by overwriting the generated code.

My understanding is that and code changes made external to the normal flow do not get picked up by Cadence - the Verilog-A code gets read at design time, not at netlist time. Would simply forcing a check and save of the veriloga view after the code is modified fix that problem? Or is there an easier way to incorporate externally generated Verilog-A code?

Dear community

We would like to have more minimalistic and customized sheet borders for our schematics. I used this guide to create a starting point. Essentially, I made a copy of the US_8ths library and modified the Title symbol to look something like that:

Problem 1

The variable ilInst~>libName points to the library of the sheet border symbols, not to the library of the schematic. How do I need to modify this field in order to see the library name of the schematic where the border is instantiated?

Problem 2

The function CCSgetCreator() was taken from here. This solution does not seem to work with our management toll (we use VersIC); the function always returns nil as value. What is the simplest way to display the name of the user that created the schematic? A custom field that could be filled manually would also do the job for us; it doesn't need to be something that automatically fetches data from a database system.

Thanks for any input.

I need to include Verilog-A files which live outside the Cadence ecosystem (i.e., they are not in veriloga views but rather are just text files) into a veriloga view. These external modules are not compatible with OA (parametized port widths) so I can't put them into cellviews and hook them together using schematics.

Example: I have a cellview "test" which has a symbol and veriloga view. I have three "externaI" modules mod1 (inside an external file mod1.va),  mod2 (inside an external file mod2.va),  and mod3 (inside an external file mod3.va). I instantiate one instance of each module in "module test". The three modules have some parametized ports which are interconnected by parameterized signals p1 and p2. These two signals are strictly local to the module.

At the bottom of the module I use "`include mod1.va", "`mod2.va", etc.

When I check and save test->veriloga it checks all the included modules as well as the "test" module. However, I get a warning:

Warning from spectre during AHDL compile.
WARNING (VACOMP-1047): The Verilog-A file contains more than one module
definition. ADE can process only one module per Verilog-A file. Put
only one module in each Verilog-A file so that ADE can identify pin
names, directions, and hierarchy within each separate module.

Is this just a SUGGESTION that I can safely ignore, or are my included modules going to be ignored?

Hello,


I would like to use the simulation software xrun/simvision that comes with XCELIUM. We are currently using classroom licenses and want to disable all ip addresses on the student pcs except the license server ip. We want to make sure that students cannot copy confidential data from the Cadence tools.


Problem:

When I launch the xrun simulation while all ip addresses are blocked, it starts but the performance is very slow. The GUI starts after 5 minutes and the simulation is ready after 10 minutes. The interesting thing is that when I enable all blocked ip addresses, everything works at a reasonable speed.

Terminal Output (execution without internet connection):

xrun -gui design.vhd

waiting for SimVision/Verisium Debug to connect...


Is there a way to run the simulation tools without an Internet connection? Or can you give me the ip addresses that are used by the simulation tools so that I can enable only those specific ips?


Regards,

Max

Hello Everybody

Recently, I want to design a high output Power Amplifier at 2.4GHz using TSMC 1P6M CMOS Bulk Process. I use its nmos_rf_25_6t transistor model to determine the approximate mosfet size

I use the most common Common-Source Differential Amplifier topology with neutralizing capacitor to improve its stability and power gain performance

Because I want to output large power, the size of mosfet is very large, the gate width is about 2mm, when I perform harmonic balance analysis, everything is alright, the OP1dB is about 28dBm (0.63Watt)

But When I perform Transient simulation, the magnitude of voltage and current waveform at the saturation point is too small, for voltgae, Vpeaking is about 50mV, for current, Ipeaking is about 5mA

I assume some reasons: the bsim4 model is not complete/ the virtuoso version is wrong (My virtuoso version is IC6.1.7-64b.500.21)/the spectre version is wrong (spectre version is 15.1.0 32bit)/the MMSIM version is wrong/Transient Simulation setting is wrong (the algorithm is select gear2only, but when I select other, like: trap, the results have no difference), the maxstep I set 5ps, minstep I set 2ps to improve simulation speed, I think this step is much smaller than the fundamental period (1/2.4e9≈416ps)

I have no idea how to solve this problem, please help me! Thank you very very much!

Hello

i did a sp-Analysis and now i want to extract the maximum value of the s11 trace and the corresponding frequency.

I already tried ymax() in the calculator but i am suspecting it only works on transient Signals.

Hello,
I'm trying to characterize a full adder that use transmission gate.
Unfortunately, the power calculation are wrong for the cell are always negative.
Is there any method or commands that can can help in power calculation or add the power consumption by the input pins to the power calculation ?
Another question, Is liberate support the characterization or transmission gate cells as standard cells or I should use liberate AMS for these type of cells ?
Thanks in advance,
Tareq 

Hello everyone, 
I have a testbench for generating s2p files from a SP simulation that was working until few months ago. Today I have reopened (w/o making changes that I am aware of) and I get the error as shown below:

first I show the testbench settings:

notice how the s2p generation is disabled: the field "file" is left blank

in the corner I defined some parameters, "filename" is the word that is suppose to generate the name for the s2p. 

where the two variables are defined as follows

And now the output log:

spectre.out file gives the following error:


When clicking on the error message at "9", the input.scs file opens up and the line 9 gets highlighted in green



now, so far I understood that the problem seem to be related tom the "pathcds" variable, but I really don't understand what the error message here means, since I don't see any error in the input.scs file

by the way - if for instance I define the variable "filename" as shown below, then I get no errors:

thanks
Tommaso

Hi,

I'm searching for a way to get a quick overview of too low cpk-values after a montecarlo sim. The non-MC results have the spec and thus the easy/understandable red/green/(yellow) colorcoding, but for MC sims I don't get a highlight for high variations inside the limits.

Is this possible (besides copying each expression into avg()+3*std()) and ..-..)?

It would be really handy to scan through finished sims...

(My final application is then to export the table for my reports and documentation...)

Regards,

leo

Hi

I have a rather strange question - is there a way to tell layout XL to NOT place the error/warning markers on a design when I open a cell?  I do a lot of my layout by using arrays from placed instances and create mosaics that completely ignore the metadata that Layout XL uses with its bindings with schematic (and instances get deleted etc. but I do like using it to generate all my pins etc.) and it's just really annoying when I open a design that I know is LVS clean and since the connectivity metadata is all screwed up (because I did not use it to actually complete the layout) I have a design that's just blinking at me at every gate, source and drain.  I typically delete them at the high level heirarchically but the second I go in and modify something and come back up it places all of them again.  I know that if I flatten all the p cells it goes away but sometimes it's nice to have that piece of metadata but that's about it.  Is there a way to "break" the features of XL like this?  I realize what a weird question this is but it's becoming more of an issue since we moved to IC 23 from IC 6 where there is no longer a layout L that I can use free from these annoyances that can't use any of the connectivity metadata.

Thanks

Chris

Hello all,

I have run a simulation with a lot of instnaces extraction and the psf.trn is >= 200 Gb, I tried to load it with simvision and it just breaks.

I would like to ask if there is a way to open this file, e.g. if I could read only some time window e.g. from 10us -> 15us.

getVersion(t)
"sub-version  ICADVM20.1-64b.500.34 "

XCELIUMMAIN23.03.001

thank you in advance

Hello everyone,

I hope you're all doing well. I’ve set up two testbenches (TB1 and TB2) for my Design Under Test (DUT) using Cadence IC6.1.8-64b.500.21 tools, as shown in the attached figure. The DUT has multiple views available: schematic, Calibre, Maestro, and Symbol, and each testbench uses the same DUT in different scenarios. Currently, I have to manually switch between these views, but I would like to streamline this process.

My goal is to use a single config view that allows me to switch between the schematic and the extracted (Calibre) views. Ideally, I would like to have a configuration file where making changes once would update both testbenches (TB1 and TB2) automatically. In other words, when I modify one config, both testbenches should reflect this update for a single simulation run.

I would really appreciate it if you could guide me on the following:

1. How to create a config view for my DUT that can be used to easily switch between the schematic and extracted views, impacting both TB1 and TB2.
2. Where to specify view priorities or other settings to control which view is used during simulation.
3. Best practices for using a config file in this scenario, so that it ensures consistency across multiple testbenches.

Please refer to the attached figure to get a better understanding of the setup I’m using, where both TB1 and TB2 include the same DUT with multiple available views.

Thank you so much for your time and assistance!

Hi,

Do anyone know if it's possible in simvision waveform viewer to see a timestamp of where uvm_errors/$errors occurred in a simulation via post-processing? 

Cheers,

Antonio

I want to use jaspergold to formally verify functionality of my custom multiplier. I am computing the expected result using A*B to check against output of my multiplier. Here, A and B are two logic signed operands. However, jaspergold is performing the operation A*B incorrectly.

I have reproduced this issue using the attached example. JasperGold compiles and elaborates the module and subsequently runs a formal proof. The tool raises a counterexample to assertion whose screenshot is attached below:

I simulated the same example using xrun and it was giving the correct product output in simvision waveform. Please help me resolve this issue. I am using 2023.03 version of Jasper Apps.

Thanks and regards

Anubhav Agarwal

I'm trying to use Jasper for checking parameter propagation in a large design. I have a list of top-level parameters, each with a HDL path of a module parameter somewhere lower in the hierarchy that's supposed to receive its value from the top-level module. The FPV app seems like an excellent tool for this, but elaborating the entire design in it is extremely time-consuming and memory-intensive. So, I'm trying to black-box everything but the interesting HDL paths. I thought using `elaborate -top dut_module_name -bbox_i * -no_bbox_i inst_foo -no_bbox_i inst_bar (...)` would work, but it doesn't. Jasper just starts flooding the log with warnings from modules that are definitely not on the whitebox list, and eventually dies due to insufficient memory. When I use -bbox_m * it correctly elaborates the top-level module with all of its sub-modules black-boxed. But then the -no_bbox_i switches have no effect. Could anyone suggest a working solution for this use case?

Hello,

I have been running this `uvm_reg_hw_reset_seq` sequence for the AHB protocol. My UVM Adapter looks like:

Issue: When I use basic reg.write, my write access are working well, as that is managed by the driver i.e. once adapter gives the packet to the driver, the driver supplies the address and the control signals to the DUT on the first clock cycle and then the write data on the next clock cycle. But when I am performing the read operation, somehow the UVM adapter is reading the data at the same clock cycle where read address + Controls are supplied and this is triggering read failure messages from the `uvm_reg_hw_reset_seq` sequence. What should I modify in the driver/sequencer/adapter so that the UVM adapter can read the data on the next cycle instead of the same clock cycle.

Just FYI: The waveforms of the read operation are correct, it is just the Adapter and the `uvm_reg_hw_reset_seq`. The AHB Driver + AHB Monitor is fully proven and verified to be working correctly.

I'm completely new to Cadence. I've been able to run a very simple simulation with the -gui option. Simvision opens, I add the variables to the waveform viewer, and press run. All is good.

I don't understand the flow when using the -nogui option. It appears that the simulation runs and returns control to the OS. When I launch Simvision, is there a database or file that I can open to display the already-simulated data?

My command is of the form:

xrun -gui -64bit -sv -access +rwc -top tb_top.sv <src files>

I exported vplan to .odf file in vManager and after editing it I imported it to vManager. The vplan was expected to be synchronized and updated. However, nothing has changed to it. Does anyone know why?

Hello,

I am aware of command script .svcf file that saves signals and loads them in while opening Simvision.

I am wondering, if there is a way for saving signals while we are in an interactive session and loading them next time when we open Simvision interactively.

Any ideas on how to do this?

Thank you in advance.

Swetha. C

I would like to send an update about a vmanager regression status x days after the regression has been run. In the current environment, the vmanager regression is creating a new filepath for logs automatically based on regression name/date, so I can't use a cron job to gather logs, as the log location is not known. 

I tried to use the pre session script to launch a detached shell script that would run after a delay, but when the pre_script runs, it waits until everything is completed before finishing and moving on to starting the regression.

Here is the test pre_script I am using:

#!/bin/sh

echo "pre_script start"

delay_script "FIRST" 1
nohup delay_script "SECOND" 30 & disown
delay_script "THIRD" 1

echo "pre_script end"
exit 0

Here is the test delay_script I am using:

#!/bin/sh

echo "Starting $1"

sleep $2

echo "Ending $1"

Here is the script output when run from terminal. After the "pre_script end", I get control back.

Here is the script output when run from vmanager. There is no "nohup", and the pre_session phase doesn't complete until all the delay scripts complete.

My question is, is there a better way to achieve my goal here? (The goal being to run a script from the vmanager log directory automatically x days after the regression). I think I could use the pre_script to send directory information for an auxiliary cron job to pick up, but I would prefer to not have to have extra cronjobs needed for this.

When analyzing multiple sessions simultaneously Verisium Manager crashed and reported below error messages:

# A fatal error has been detected by the Java Runtime Environment:
#
#  SIGSEGV (0xb) at pc=0x00007efc52861b74, pid=14182, tid=18380
#
# JRE version: OpenJDK Runtime Environment Temurin-17.0.3+7 (17.0.3+7) (build 17.0.3+7)
# Java VM: OpenJDK 64-Bit Server VM Temurin-17.0.3+7 (17.0.3+7, mixed mode, sharing, tiered, compressed oops, compressed class ptrs, g1 gc, linux-amd64)
# Problematic frame:
# C  [libucis.so+0x238b74]

......

For more details please refer to the attached log file "hs_err_pid21143.log".

Two approaches were tried to solve this problem but neither has worked.
Method.1:

Setting larger heap size of Java process by "-memlimit" options.For example "vmanager -memlimit 8G".

Method.2:

Enlarging stack memory size limit of the Coverage engine by setting "IMC_NATIVE_STACKSIZE" environment variable to a larger value. For example "setenv IMC_NATIVE_STACKSIZE 1024000"

According to "hs_err_pid*.log" it is almost certain that the memory overflow triggered Java's CrashOnOutOfMemoryError and caused Verisium Manager to crash. There are some arguments about memory management of Java like "Xms, Xmx, ThreadStackSize, Xss5048k etc" and maybe this problem can be fixed by setting these arguments during analysis. However, how exactly does Verisium Manager specify these arguments during analysis? I tried to set them by the form of setting environment variables before analysis but it didn't work in analysis and their values didn't change.

Is there something wrong with my operation or is there a better solution?

Thank you very much.

I'm working on the code coverage. Doing a metrics analysis by default we see overall average grade and overall covered. But when i do a block analysis on an instance i see overall covered grade, code covered grade, block covered grade, statement covered grade, expression covered grade, toggle covered grade.

As I dont know the difference I started to read the IMC user guide and came to know there are 3 things we come across while doing a code coverage local, covered, average

From my understanding

local - child instances metrics doesnt reach the parent level. For example, we have an instance Q and its sub instances like Q.a, Q.b. Block Local grade of Q can be 100% even when its instances Q.a and Q.b a block local grades isnt at 100%.

In the attached image there is formula 

The key difference between average and covered is the weights.

Average : Mathematically taking the above scenario where Q.a, and Q.b has 10 blocks each. Q.a has covered 8 blocks and q.b has covered 2 blocks. Now if we take the normal average it should be total covered/ totatl number = 8+2/10+10 yielding 50%. But when we add weights saying Q.a is 70% and Q.b is 30% the new number would be (8*0.7+2*0.3) / (10*0.7+10*0.3) resulting 62%. Because of the weights we see 12% bump.

Covered: there is no role of weights.

Among these 3 metrics i've changed my default view to this in the image to get more realistic picture when i do analyze metrics. Do you guys agree with the approach?

Hi,
I want to parameterized width and length of a NMOS, but it ignore it and I face this error:
*WARNING* Value input must be a number - setting back to previous value.

Does anybody know how I can fix this issue?
Thanks