Hi,

My Virtuoso and Spectre Version: ICADVM20.1-64b.NYISR30.2

I have an expression where the EvalType is "sweeps". Here is the expression (I also attached the snapshot):

(peakToPeak(leafValue(swapSweep(delay(?wf1 clip((VT("/clk0") - VT("/clk180")) (VAR("mt_stop") - (4.0 / VAR("datarate"))) VAR("mt_stop")) ?value1 0 ?edge1 "rising" ?nth1 1 ?td1 0 ?tol1 nil ?wf2 clip((VT("/tx_padp") - VT("/tx_padn")) (VAR("mt_stop") - (4.0 / VAR("datarate"))) VAR("mt_stop")) ?value2 0 ?edge2 "rising" ?nth2 1 ?tol2 nil ?td2 nil ?stop nil ?multiple nil) "VDD_FIXED_NOISE") "VREGLN_cmode" 0.85 "VREGDRV_novn" 0.4 "datarate" 1.658e+10) ?overall t) / 10.0)

What this expression does is that it compares the delay between the output data with respect to a reference clock. I then get this information for two conditions (VDD_FIXED_NOISE = 0 or 10mV) to get the effect of the supply-induced jitter. In the expression, I need to give the value of each parameter in different modes to distinguish them from each other. Now I want to sweep the base supply values and see the supply variation effects. For example, I want to change VREGLN_cmode from 0.85 to 0.81 and see how my supply-induced jitter changes. For that, the hard way is to copy the expression and change that value accordingly (e.g. "VREGLN_cmode" 0.81). I'm looking for an easier way to use a variable in the expression. Something like VAR("VREGLN_Sweep"). But I see it doesn't work in my expression and it gives an eVal error. I tested this before in other expressions (not sweep type) and it always worked. I have only one test and these variables are all Design Variables and not Global variables.
I want to know what mistake am I doing here and is there a way to make this work. Sorry that if I could not explain better my inquiry. Thank you.

Hi,
My Virtuoso and Spectre Version: ICADVM20.1-64b.NYISR30.2
I plot an eye diagram using a built in function. I want to see the data-dependent jitter. I want to measure the eye diagram edges at zero crossing (width of that diamond part) shown in the pic by vertical and horizontal markers. I can put a marker and read the numbers there and get what I want. But now I want to run Monte Carlo and I can't do this for all samples. I wish I could write an expression for this. Unfortunately, I see that the function "cross" is not working on the eye diagram. Basically, when I send the eye diagram data to a table, I see that it actually is just the prbs data and not the eye diagram data. Is there a hack that can help me achieve my goal which is: having an expression to measure the edges of the eye diagram at zero crossing?
There is a script that Andrew wrote (https://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin%3AViewSolution%3BsolutionNumber%3D11395772). This is a good script but it puts all edges on top of each other. I want to distinguish the two edges. In the attached pic (two-period eye diagram) you can see what I mean by the two edges (diamond shapes). I want to measure each of the two and take the maximum. Having all the edges on top of each other won't give me what I want. All edges together will lso include DCD. I purely want to measure DDJ. DCD is measured separately. I have very little experience with writing scripts and could not modify Andrew's script.
Your help is much appreciated. Thank you.

Hello,

I am trying to design an RF mixer for a TX.
Assume my input IF signal is at 1 GHz, my LO at 2 GHz and I want my RF at 3 GHz, and assume that the mixer fully works after testing it with HB.
How to simply set the envelope analysis to check the EVM ?
I read through the documentation but I couldn't get it (I couldn't fully understand the settings of the source, probe, analysis.)
Which source and probe to use? I want custom modulation with custom bandwidth and center frequency.
Is there some examples for the ENVLP analysis ?

I am using IC23.1 and spectre 20.1.354.

Hi,

In our design team, we're looking for a strategy to make all cell views self-contained. We are struggling to do so when nport devices are involved.

The nport file requires a full path, whereas what we need is a relative path to the current path of the cell in which we're using the nport.

I have browsed through the forums & cadence support pages, but could not find a solution.

1) There is a proposal from Andrew to add the file directory in ADE option "Simulation Files." :https://community.cadence.com/cadence_technology_forums/f/rf-design/27167/s-parameter-datafile-path-in-nport . This, however, is not suitable, because the cell is not self contained.

2) The new cadence version off DataSource "cellView" in nport options:

This however is not suitable for us due to two reasons:

i- Somehow we don't get this option in the nport cell (perhaps some custom modification from our PDK team)

ii- Even if we had this option, it requires to select the library, which again makes it unsuitable: We often copy design libraries for derivative products using "Hierarchical Copy" feature. And when the library is copied, the nport will still be pointing to the old library. Thus, it is still not self-contained.

In principle, it should not be difficult (technically) to point to a text file relative to the cell directory (f.ex we can make a folder under the same cell with name "sparFiles" & place all spar files under this folder), however it does not seem to be possible.

Could you perhaps recommend us a work-around to achieve our goal: making the cells which contain nport devices self-contained so that when we copy a cell, we do not have to update all the nport file destinations ?

Thanks in advance.

My Cadence Version: IC23.1-64b.ISR4.51

My Spectre version: 23.1.0.362.isr5

Hi

I'm learning Hb analysis for the IIP3 simulation of a gilbert mixer. My f_RF=5GHz, f_LO=4GHz and f_IF=1GHz . I'm a bit confused about setting the 1st order and 3rd order harmonic at the Direct plot form. I have set 1st order harmonic = 1GHz and 3rd order harminic = 2*f_LO-f_RF = 3GHz and it gives me the following results.

This is my 1dB compression point result

Hb analysis window

Direct plot window

Please let me know if my harmonic selection is correct and whether I'm getting a correct IIP3 and P1db curve

Hi *,

I am simulating a 32kHz high Q crystal oscillator with a pulse shaping circuit. I set up a PSS analysis using the Shooting Newton engine. I set a beat frequency of 32k and used the crystal output and ground as reference nodes. After the initial transient the amplitude growth was already pretty much settled such that the shooting iterations could continue the job.

My problem is: In 5...10% of my PVT runs the simulator detects a frequency divider in the initial transient simulation. The output log says:

Frequency divided by 3 at node <xxx>

The Estimated oscillating frequency from Tstab Tran is = 11.0193 kHz .

However, the mentioned node is only part of the control logic and is always constant (but it has some ripples and glitches which are all less than 30uV). These glitches spoil my fundamental frequency (11kHz instead of 32kHz). Sometimes the simulator detects a frequency division by 2 or 3 and the mentioned node <xxx> is different depending on PVT - but the node is always a genuine high or low signal inside my control logic.

How can I tell the simulator that there is no frequency divider and it should only observe the given node pair in the PSS analysis setup to estimate the fundamental frequency? I have tried the following workarounds but none of them worked reliably:

- extended/reduced the initial transient simulation time

- decreased accuracy

- preset override with Euler integration method for the initial transient to damp glitches

- tried different initial conditions

- specified various oscillator nodes in the analysis setup form

By the way, I am using Spectre X (version 21.1.0.389.ISR8) with CX accuracy.

Thanks for your support and best regards

Stephan

I get multiple results at the same frequency in a 3-tone simulation.

I try to determine the IP3 of a mixer. I have 3 large signal tones: 0.75 GHz, 1.25 GHz and 1.26 GHz.

At the IM3 frequency of 490 MHz I observe 4 results, see also the screenshot of the table output. The frequencies are exactly the same (even when I subtract 490 MHz by using xval() ).

Which of the values do I have to use to determine the correct IP3?

Is there an option to merge these results?

Hello everybody,

As you can find in the attached image, I am trying to simulate a Colpitts oscillator. However, using pss analysis it shows a high output power. 

My question is where is the problem of my structure or simulation setup?

Best,

Hello everyone,

I am trying to perform a load pull simulation of a transistor to verify some gain calculations I made using its S-parameters. Specifically, I have calculated the optimal conjugate impedances for the input and output to later calculate the power dissipated and transmitted in each stage of the transistor. Then, I only varied the output impedance and recalculated these powers, noticing that the power delivered to the load is lower.

Now, what I want to do is simulate this behavior using the Load Pull simulation. I have taken the model shown in the image, but I believe it is a linear model. My question is: if the chosen model is linear, is the load pull simulation accurate? In the calculations I made, nonlinearities are not considered. I don’t want to take nonlinearities into account.

In short, do you have any ideas on how to verify the calculations made with the transistor’s S-parameters through a load pull simulation?

Can you recommend any transistor model that is nonlinear and also has an S-parameter file?

Thank you very much in advance.

While adding an element created from a netlist file in AWR, I am getting the error 'The element type being dropped is not compatible with the window it is being dropped into'. The netlist file in AWR has the following contents:

.subckt BFG520W base collector emitter npn
.model BFG520W NPN(IS=1.016E-15 NF=1.000 BF=220.1 IKF=510E-3 VAF=48.06
+ ISE=2.83E-13 NE=2.035 NR=0.988 BR=100.7 IKR=2.352E-3
+ VAR=1.692 ISC=24.48E-18 NC=1.022 RB=10.00 RE=0.7753
+ RC=2.21 CJC=447.6E-15 MJC=0.07 VJC=0.1892
+ CJE=1.245E-12 TF=8.616E-12 TR=5.437E-12 mfg=NXP)

I have attached screenshots of the element BFG520W2 created due to the above netlist and the error I am getting while adding this element.

Hello everyone,

For my cross-coupled oscillator design, I have a problem with stability analysis. Based on my achieved results which are attached, where is my design problem?

Best,

https://ibb.co/bgKFP4N

https://ibb.co/3FGRLmV

https://ibb.co/pwSZDSF

Hi everyone,

I'm currently working on my thesis, which involves a beamformer system using CMOS 65nm technology. I'm trying to use the EMX tool for EM simulation but have encountered a few problems. Before diving into my questions about EMX, let me briefly explain how I conduct EM simulations with other software (ADS).

In ADS, I use the EM simulator with the Momentum microwave engine. However, my EM layout is quite large, and the mesh generated is extremely detailed, making it difficult to simulate the entire system. As a workaround, I divide the system into smaller parts and simulate each one individually. I've attached a snapshot of my setup, which includes an amplifier and a 1-to-2 Wilkinson power divider. I've separated these circuits and placed pins to facilitate EM simulations for each. I also placed ground pins at the boundaries of each circuit to connect them to the ground plane.

Here’s the link to the image (I'm unable to upload it due to an error): https://drive.google.com/file/d/13Qn4-DvMBj_K1JQLXrTWaWZ8uaLJr15u/view?usp=sharing

Now, moving on to EMX (version 6.3). For a maximum frequency of 31 GHz, I set the edge mesh = thickness = 0.4 µm (approximately the skin depth). However, when I simulate the circuit (amplifier + divider), the mesh on the ground plane becomes very dense, which makes running the simulation impossible due to excessive memory requirements. I reverted to my ADS approach and divided the circuit into two parts, placing ports to connect them. Unfortunately, EMX doesn't allow me to place multiple edge ports on the same edge for the ground plane, which has left me confused. Here are a couple of questions I have:

1. Is breaking the circuit into smaller parts a valid approach? Given the large ground plane, the mesh size for the ground is significant, making simulations challenging. Are there any methods to manage this issue?

2. Regarding the ground pins, why can't I place multiple edge ports to connect the ground planes of both circuits as I did in ADS? If this approach is incorrect, could you suggest alternative methods for simulating individual circuits and connecting them to estimate system performance?

Any insights would be greatly appreciated. Thank you in advance for your help!

Hi I noticed that some figures from the old posts in the cadence blogs have been missing.

I think this problem happened before and Andrew Beckett asked the original author to fix the issue:

 Figures missing in the RF Design Blogs article of "Measuring Fmax for MOS Transistors" 

Some of these posts are quite valuable, and would be nice to have access to the figures, which are a very important part of some posts,

Thanks

Leandro

Hello Everybody

Recently, I want to design a high output Power Amplifier at 2.4GHz using TSMC 1P6M CMOS Bulk Process. I use its nmos_rf_25_6t transistor model to determine the approximate mosfet size

I use the most common Common-Source Differential Amplifier topology with neutralizing capacitor to improve its stability and power gain performance

Because I want to output large power, the size of mosfet is very large, the gate width is about 2mm, when I perform harmonic balance analysis, everything is alright, the OP1dB is about 28dBm (0.63Watt)

But When I perform Transient simulation, the magnitude of voltage and current waveform at the saturation point is too small, for voltgae, Vpeaking is about 50mV, for current, Ipeaking is about 5mA

I assume some reasons: the bsim4 model is not complete/ the virtuoso version is wrong (My virtuoso version is IC6.1.7-64b.500.21)/the spectre version is wrong (spectre version is 15.1.0 32bit)/the MMSIM version is wrong/Transient Simulation setting is wrong (the algorithm is select gear2only, but when I select other, like: trap, the results have no difference), the maxstep I set 5ps, minstep I set 2ps to improve simulation speed, I think this step is much smaller than the fundamental period (1/2.4e9≈416ps)

I have no idea how to solve this problem, please help me! Thank you very very much!

Sample clues

18 across: Makoto Hagiwara and David Jung both claim to have invented it (7,6)

1 down: French impressionist who rejected that term (5)

3 down: Artificial surface used for playing hockey (9)

7 down: The sequel to Iliad (7)

12 down: Adipose tissue (4,3)

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6 across: Franchise revived by Frank Miller (6)

13 across: What Keanu Reeves and Zayed Khan have in common (5)

18 across: What Frank Sinatra and George Clooney have in common (6,6)

19 across: Dosa mix, for example (6)

2 down: Green, in a non-environmental way (7)

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5 down: Torso covering (6)

7 down: Government by rogues (12)

15 across: eBay speciality (7)

18 across: Demonic (8)

20 across: Common language (6,6)

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17 across: Beckham speciality (4,4)

4 down: Havana speciality (5)

19 across: Infamous 1988 commercial against Michael Dukakis (9,4)

11 down: Precisely (2,3,3)

13 down: City infamously ransacked by the Japanese in 1937 (7)

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11 across: Chandigarh’s is 0172 (3,4)

21 across: He’s a loser, baby (4)

1 down: Garment meant to shape the torso (6)

12 down: It’s slogan: “Life, Liberty and the Pursuit” (8)

18 down: Noise made by badminton players? (6)

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Sample clues

5 across: The US president’s bird (3,5,3)

11 down: Group once known as the Quarrymen (7)

10 across: Cavalry sword (5)

19 across: Masonic ritual (5,6)

1 down: Pioneer of Ostpolitik (6)

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Sample clues

14 across: FDR’s baby (3,4)

1 down: A glitch in the Matrix? (4,2)

4 down: Slanted character (6)

5 down: New Year’s venue in New York (5,6)

16 down: Atmosphere of melancholy (5)

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Sample clues

6 across: Alejandro González Iñárritu’s breakthrough film (6,6)

19 across: Soft leather shoe (8)

7 down: Randroids, for example (12)

12 down: First American World Chess Champion (7)

17 down: Circle of influence (5)

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Sample clues

5 across: Robbie Robertson song about Richard Manuel (6,5)

2 down: F5 on a keyboard (7)

10 across: Lionel Richie hit (5)

3 down: ALTAIR, for example (5)

16 down: The problem with Florida 2000 (5)

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9 across: Van Morrison classic from Moondance (7)

6 down: Order beginning with ‘A’ (12)

6 across: Fatal weakness (8,4)

19 across: Rolling Stones classic (12)

4 down: Massacre tool (8)

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Read through this blog to know more about the new Reliability Report view in Virtuoso ADE Assembler and Virtuoso ADE Explorer.(read more)

I have been involved in the Virtuoso RF Solution for the last four years. Most of the customers I work with have a SiP package already in progress. They often ask "How do I get my SiP design into Virtuoso RF Solution?" I am excited about new functionality in the latest ICADVM20.1 ISR25 release. It is a new GUI under the Tools menu called Enablement. (read more)

An AMS Designer Flex simulation gives you the most immediate access to the latest simulation technology on either side, gets out of the way of the core engines and allows the engine performance to shine while providing access to new features. Check out this blog to know more.

Che(read more)

The ICADVM20.1 ISR26 and IC6.1.8 ISR26 production releases are now available for download.(read more)

This blog describes the new capabilities in Spectre 21.1 ISR2 through which it provides support to the Voltus-XFi Custom Power Integrity Solution.(read more)

This blog introduces you to an efficient way to debug interface elements or connect modules in a mixed-signal simulation.(read more)

Read this blog for an overview to the Circuit physical verification and parasitic extraction design stage in the Custom IC Design methodology and the key design steps which can help you achieve this.(read more)

In my last blog, Getting Your Existing SiP File Into Virtuoso RF, I talked about the new enhancements in ICADVM20.1 ISR25 for Virtuoso RF Solution. At the end of the blog, I told you about the Fully Assisted Roundtrip flow, which includes importing SiP files that are compatible with the Virtuoso RF Solution assisted import flow into the Virtuoso platform. Let's examine how the Fully Assisted Roundtrip flow works in this blog.(read more)

The ICADVM20.1 ISR27 and IC6.1.8 ISR27 production releases are now available for download.(read more)

This blog introduces the new Voltus-XFi Custom Power Integrity Solution, a transistor-level EM-IR tool that enables designers to complete comprehensive analysis and debugging easily and quickly.(read more)

I am trying to figure out the most efficient workflow for adding test points. My use case involves adding ~100 or so SMT pads at the bottom for bed-of-nails ICT test that are required to be on a test point grid. A lot of the nets are on the top or from inner layers and so have to be brought to the bottom using stubs. I'm used to Xpediiton workflow of being able to set a test point padstack, set a test point grid, and then select a net, add the test point to the bottom layer on the grid with that net attached and then route the stub with gridless routing.

In Orcad, it seems I need to route the stub, switch layer pairs to be both bottom once I bring the stub to the bottom and then change the grid to be the test point grid and then add the test point on the grid. It requires a lot of clicks, very mistake prone requiring lots of oops and very slow for 100+ test points to be brought out at the bottom. 

I'm sure there is a better way that is used by folks with a lot of Orcad experience. Any suggestions?

hello

is there a way to update one dynamic shape instead of updating all dynamic shapes?

i have over 6000 dynamic shapes on my design and it takes over 10 mins to update them all.

i just would like to update only one dynamic shape sometimes to find out if placing vias and lines in a shape has enough space or not.

regards

masa

I want to make an opening in the solder mask right above a trace that is acting like a guard ring. Do I really need to go and buy the Allegro Productivity Toolbox add-on for using the Cross-Copy tool for a basic operation like that??

/F

Hi

I have fixed a SPACING RULE (SP1) for a CLASS_DIFF_PAIR whereas for via associated to the net (DP_VIA), the DISTANCE > 60mils respect to ANY other vias (PTH, BB, TEST vias)

Now my problem is that this rules should NOT be applied for GND VIAS (STICHING VIA) which must be placed at a distance < 40mils respect to DP_VIA

How to create an exemption to the SPACING RULE (SP1)?

I am using OrCAD PCB Designer Standard version 17.4-2019. I want to force update the Package_Height_Max property on the place bound top shape. The footprint library that we've created has that property set in the dra file, but I'd like to override that from capture so I can be certain that the height is correct.

This is coming from a place where we have created a very large footprint library over that past ++ years. Everyone who creates a new footprint is supposed to make sure that we add Package_Height_Max to the footprint, but of course footprints get reused for various parts, not all of which will have the same package height. What I want to do is export a list of package heights from our part database and then import the package heights into Capture and override the package height in the footprint.

I have found a post here  Using Height Property from Orcad Capture which says its not possible, but it also says its from 15 years ago, so maybe things have changed?

Loading new netlist into 23.1 Apparently it does not like many of the specified footprints or padstacks. I have to open the footprint in 231., save the pad stack then save the footprint. This is very time consuming and frustrating to say the least.

I also get the following message

WARNING(SPMHNI-194): Symbol 'SMD_SOD123_ANODE_PIN1' used by RefDes D30 for device 'DIODE_0_SMD_SOD123_ANODE_PIN1_1N4148W-7-F' not found.

The symbol either does not exist in the library path (PSMPATH) or is an old symbol from a previous release.  

Set the correct library path if not set or use dbdo

     The current version of software is unable to open design smd_sod123_anode_pin1.

The design was last saved using version 16.5 and must be updated using DB Doctor. [help]


Going to DB Doctor does nothing, no option to update a footprint?

Tom

hello:

i place a symbol into my design.

on my design, i change the symbol property by unlocking the symbol and unfixing pins so that i can move pins on the symbol.

i move some pins on my design.

but when i export the symbol from my design, the symbol is not current but has the original pin location.

is there a way to retain the pin locations after moving pins on a symbol when exporting the symbol?

regards

masa

Any tips or SKIL files to help create a thermal shaped openings for paste masks for a donut shaped pin for mics or stand-offs like below?

Hello,

Trying to figure out why this situation does not generate a DRC error.

A resistor was accidently placed so the pad was on top of another pad. See picture:

I have checked the CM and both Spacing Constraint Set and Same Net Spacing Constraint Set have Smd pin to Smd pin set to 0.1 mm.

I'm using Allegro PCB designer 22.1.

If someone has an idea why this does not give a DRC i would appreciate it. Thanks.

Regards,

Filip

Dear Community,

I have created a PCB layout with multiple high-speed nets, I want to check the SI like how signals are reflected and taken to each other.

I have the OrCAD X Professional, how to check the reflection and crosstalk using the OrCAD X Professional software version 24.1.

I want to create a topology flow to the PCB layout and perform the reflection and crosstalk.

Regards,

Rohit Rohan

Hai Community,

I have a PCB board which has multiple high speed nets and I want to perform the EMI and EMC checking.

Which Cadence tool should I use for checking the EMI and EMC coupling?

Regards,

Rohit Rohan

Dear Community,

I have created a PCB board and let's say I have found some parts of the PCB board where there are impedance issues, then how to resolve that impedance issue using the OrCAD X Professional.

Regards,

Rohit Rohan

Hai Community,

What are the differences between the Cadence OrCAD / Allegro 24.1 with the Altium Designer 24.

Can I get the grid matrix difference between these two tools?

Regards,

Rohit Rohan

Optimizing PCB thermal performance is essential in today’s high-density designs, as it ensures stability, prolongs component life, and prevents potential thermal issues. One of the first steps to achieving this is with strategic component placement. Positioning high-power components—such as regulators, power transistors, or processors—away from heat-sensitive parts can prevent thermal interference, and placing them near the edges of the PCB often helps dissipate heat more effectively. It’s also beneficial to group components by their heat generation, creating dedicated thermal zones that can manage localized heating and reduce impact on other areas of the board.

Using thermal vias is another effective technique. By placing thermal vias under components like BGAs or power ICs, heat can be transferred from the surface to internal layers or ground planes. Increasing the size and number of these vias, or using thicker plating, enhances heat conductivity and helps manage heat more evenly across layers in multilayer boards. Increasing copper thickness on the PCB also has a major impact. Opting for thicker copper layers (e.g., 2 oz or even 3 oz copper) significantly boosts the heat dissipation capabilities of power planes and traces, especially in high-current areas. Large copper planes, such as dedicated ground or power planes, are equally effective in spreading heat efficiently. Adding thermal pads directly beneath heat-generating components improves this heat distribution.

Thermal relief pads help regulate heat flow for through-hole components by controlling heat transfer, which reduces thermal stress during soldering and prevents excessive heat spread to nearby sensitive areas. Performing thermal analysis with software tools like Celsius can be invaluable, as it allows you to simulate and model heat distribution, spot potential thermal issues, and refine your design before finalizing it.

Using heat sinks and thermal pads provides a direct way to draw heat from high-power components. Heat sinks can be attached with thermal adhesives, screws, or clamps, while thermal interface materials (TIMs), such as thermal pads or conductive adhesives, further reduce thermal resistance, enhancing heat-transfer efficiency. Optimizing the PCB layer stackup is also a key factor. Dedicated ground and power layers improve heat conduction across the PCB, enabling heat transfer between layers, particularly in high-density and multilayer PCBs.

In designs with high power requirements, active cooling options like fans, blowers, or heat pipes can be essential, helping to direct airflow across the PCB and further improving heat dissipation. Adding ventilation slots around hot zones and considering passive cooling paths enhance natural airflow, making the design more thermally efficient. By combining several of these techniques, you can create a PCB that handles heat effectively, resulting in a robust, long-lasting, and reliable product.

Let us know if you’ve had any challenges with thermal management in your designs—I’d be glad to discuss further!

The blog discusses Voltus InsightAI RAK that is designed to give you an accelerated start on the execution of Voltus InsightAI flow.(read more)