Provided is a surface treated calcium carbonate filler for resins, which comprises calcium carbonate particles, the surface of which has been treated with at least one surface active agent (A) selected from the group consisting of saturated fatty acids, unsaturated fatty acids, alicyclic carboxylic acids, resin acids, and salts thereof and with at least one compound (B) having the ability to chelate alkaline earth metals, the compound (B) being selected from the group consisting of phosphonic acids, polycarboxylic acids, and salts thereof. The surface treated calcium carbonate filler for resins of the present invention deteriorates little with time, has satisfactory dispersibility in resins, and can give a sheet or film which has a satisfactory balance among durability, weatherability, strength, and thermal stability, and is useful as a battery separator or a light reflector.

Disclosed are methods for producing rubber-containing bituminous mixtures by pressurizing mixtures of bituminous materials, crumb rubber, and one or more suspension agents with a gas, and then reducing the pressure, creating bubbles of the gas in the mixture. Also disclosed are methods of introducing gas into such mixture by rapid mixing. Mixtures produced by the disclosed methods, such as rubber-containing asphalt mixtures and paving compositions thereof, and their use are also disclosed.

Set of compositions for preparing system-in-package type semiconductor device. The composition set consists of underfill composition for preparing underfill part and encapsulation resin composition for preparing resin encapsulation part. 1) A cured product of the underfill composition has a glass transition temperature, Tg, ≧100° C. and is the same with or differs from a Tg of a cured product of the encapsulation resin composition by ≦20° C. 2) Total linear expansion coefficient of the cured product of the underfill composition at a temperature not higher than (Tg−30)° C. and a linear expansion coefficient of the cured product of the encapsulation resin composition at a temperature not higher than (Tg−30)° C. is ≦42 ppm/° C. 3) A ratio of the linear expansion coefficient of the cured product of the encapsulation resin composition to the linear expansion coefficient of the cured product of the underfill composition ranges from 0.3 to 1.0.

The present invention relates to a process for the production of a ready-to-use epoxy composition having a filler content of at least 55 vol.-%, relative to the complete ready-to-use epoxy composition, which comprises: providing a liquid A, which comprises at least one epoxy resin,providing a liquid B, which comprises at least one curing agent,providing a solid component C, which comprises at least one filler,wherein in a first step one of the liquids A or B is filled in a mixing container,in a second step the solid component C is deposited on top of the liquid in the mixing container,in a third step the remaining liquid A or B is deposited on top of the solid component C, andin a fourth step the components are mixed to obtain the ready-to-use epoxy composition.

Bis-Phenol A (BPA) can now be replaced in industrial processes by BPA substitutes. The BPA substitutes can have structures that are derivatives of BPA. The BPA substitutes can be used in preparing epoxy composition, polycarbonate compositions, and polysulfonate compositions or for other uses in place of BPA.

Described herein are devices, compositions, and methods for improving color discernment.

A carrier composition for filling a tooth root canal, comprising a cross-linkable material.

An artificial silica marble comprises a matrix and a line pattern portion. The line pattern portion comprises fine lines having a width of about 50 to about 500 μm and forms a web- or net-like pattern. The line pattern portion divides or partitions the artificial silica marble into a plurality of irregularly shaped pattern portions to form an amorphous pattern in the cross section of the artificial silica marble.

A coating/sealant system that includes a coating and a sealant deposited over at least a portion of the coating, in which the coating includes a reaction product formed from reactants comprising a phosphated epoxy resin and a curing agent, and the sealant includes a sulfur-containing polymer.

Aqueous copolymer dispersions for a variety of uses, including coating compositions or binders for plasters and paints, are disclosed. The aqueous copolymer dispersions may comprise one or more silicon containing compounds, in particular hydrolyzable silane compounds without any additional reactive group.

The present invention relates to an item produced via thermoforming and comprising: i) a biodegradable polyester comprising:a) succinic acid;b) optionally one or more C6-C20 dicarboxylic acids; e) 1,3-propanediol or 1,4-butanediol; f) a chain extender or branching agent;ii) polylactic acid;iii) at least one mineral filler; The invention further relates to processes for producing the abovementioned items.

A non-skid coating described herein attempts to overcome the deficiencies of the conventional coatings with improved external durability and color retention, a reduced level of VOCs, and direct-to-metal (DTM) adhesion using organo-siloxane chemistry. The non-skid coating has a first component having an amino-functional siloxane resin; a second component having a non-aromatic epoxy resin; a spherical filler for lowering viscosity; a pigment; a coarse aggregate; and a thixotropic agent. The amino-functional siloxane resin can be an amino-functional methyl phenyl polysiloxane, diphenyl polysiloxane or silsesquioxane-based resin. The non-aromatic epoxy resin can be cycloaliphatic or aliphatic. The first component is about 5% to 20% weight of the coating, and the second component is about 80% to 95% weight of the coating.

Generally, compositions and methods of producing dimensionally stable three dimensional objects using an additive build up process. Specifically, materials combinable in an additive build up process using a materials printer for the production of stable three dimensional molds useful in the production of molded or formed parts.

The invention relates to a method for producing thermoplastic molding compounds, comprising: A) 40 to 99 wt % of at least one thermoplastic polymer, B) 1 to 60 wt % of a flame-proofing agent component containing an expandable graphite, and C) 0 to 60 wt % of further additives, by melt-mixing components A), B) and C) in a screw-type extruder, wherein the screw-type extruder, along the feed direction, comprises, in the following order, at least one dosing zone, a plastifying zone, a homogenizing zone, a second dosing zone, and a discharge zone, in that the dosing takes place into the screw-type extruder having the length L, wherein the length L is defined as the section starting with the first dosing unit for adding components A, B and/or C and ending, in the feed direction, at the discharge opening, a melt is generated after adding components A, B and C in the range of 0 liter to 0.15 liter in a first method step in the presence of component B1), and in a second method step, after the addition of component B1) in the range of 0.5 liter to 0.95 liter, component B1) is mixed into said melt, wherein said method offers technical advantages.

The disclosure provides an ink jet ink for color filter and a method for preparing the same, as well as a method for preparing of a color filter. The ink jet ink for color filter comprising, by weight, 10 to 50 parts of aqueous nano pigment dispersion and 51 to 95 parts of a cold curing component.

A facile synthesis of amphiphilic hyperbranched polymers consisting of poly(amic acid) and polyimide was developed via “A2+B3” approach from difunctional anhydride and trifunctional hydrophilic poly(oxyalkylene)triamine. Various amphiphilic hyperbranched poly(amic acid)s (HBPAAs) with terminal amine functionalities and amic acid structures were prepared through ring-opening polyaddition at room temperature, followed by thermal imidization process for the formation of hyperbranched polyimides (HBPIs), accordingly. The resulting HBPIs were analyzed by GPC, indicating the molecule weights of 5000˜7000 g/mol with a distribution of polydispersity between 2.0 and 3.8. The amine titration for HBPIs indicated the peripheral total-amine contents to be 8.32˜18.32 mequiv/g dependent on compositions.

The invention provides a process for monitoring and/or adjusting a dispersion polymerization of an olefin-based polymer, the process comprising monitoring the concentration of the carbon-carbon unsaturations in the dispersion using Raman Spectroscopy. The invention also provides a process for polymerizing an olefin-based polymer, the process comprising polymerizing one or more monomer types, in the presence of at least one catalyst and at least one solvent, to form the polymer as a dispersed phase in the solvent; and monitoring the concentration of the carbon-carbon unsaturations in the dispersion using Raman Spectroscopy.

Disclosed is an epoxy resin composition used for encapsulation of a semiconductor containing an epoxy resin (A), a curing agent (B), an inorganic filler (C) and a mold releasing agent, in which the mold releasing agent contains a compound (D) having a copolymer of an α-olefin having 28 to 60 carbon atoms and a maleic anhydride esterified with a long chain aliphatic alcohol having 10 to 25 carbon atoms.

Amphiphilic biomimetic phosphorylcholine-containing silicone compounds for use in both topical and internal applications as components in biomedical devices. The silicone compounds, which include zwitterionic phosphorylcholine groups, may be polymerizable or non-polymerizable. Specific examples of applications include use as active functional components in ophthalmic lenses, ophthalmic lens care solutions, liquid bandages, wound dressings, and lubricious and anti-thrombogenic coatings.

A method, system and computer program product for intelligently responding to hardware failures so as to optimize system performance. An administrative server monitors the utilization of the hardware as well as the software components running on the hardware to assess a context of the software components running on the hardware. Upon detecting a hardware failure, the administrative server analyzes the hardware failure to determine the type of hardware failure and analyzes the properties of the workload running on the failed hardware. The administrative server then responds to the detected hardware failure based on various factors, including the type of the hardware failure, the properties of the workload running on the failed hardware and the context of the software running on the failed hardware. In this manner, by taking into consideration such factors in responding to the detected hardware failure, a more intelligent response is provided that optimizes system performance.

Methods and apparatus for output of high-bandwidth debug data/traces in electronic devices using embedded high-speed debug port(s). Debug data is received from multiple blocks and buffered in a buffer. The buffer's output is operatively coupled to one or more high-speed serial I/O interfaces via muxing logic during debug test operations. The buffered data is encoded as serialized data and sent over the one or more high-speed serial I/O interfaces to a logic device that receives serialized data and de-serializes it to generate parallel debug data that is provided to a debugger. The buffer may be configured as a bandwidth-adapting buffer that facilitates transfer of debug data that is received at a variable combined data rate outbound via the one or more high-speed serial I/O interfaces at a data rate corresponding to the bandwidth of the serial I/O interfaces.

The invention in particular has as an object detecting incompatibility between equipment items of a on-board system. A logic interface associated with one equipment item comprises at least one input while a logic interface associated with another equipment item comprises at least one output. The input and the output are connected. After a minimal data definition level associated with the input and a data definition level associated with the output have been obtained (505), the said minimal data definition level associated with the input is compared (515) with the said data definition level associated with the output. Following this comparison, if the said minimal data definition level associated with the input is lower than the said data definition level associated with the output, an alarm indicating an incompatibility of these two equipment items is generated (545).

A computing system resource recovery method can include identifying a resource manager associated with a computing transaction, classifying the computing transaction to determine a predetermined metric, measuring an actual metric of the computing transaction, comparing the predetermined metric to the actual metric to detect abnormal behavior in the transaction and modeling the abnormal behavior to determine how the resource manager is affected by the abnormal behavior.

An approach for introspection of a software component and generation of a conditional memory dump, a computing device executing an introspection program with respect to the software component is provided. An introspection system comprises one or more conditions for generating the conditional memory dump based on operations of the software component. In one aspect, a computing device detects, through an introspection program, whether the one or more conditions are satisfied by the software component based on information in an introspection analyzer of the introspection program. In addition, the computing device indicates, through the introspection program, if the one or more conditions are satisfied by the software component. In another aspect, responsive to the indication, the computing device generates the conditional memory dump through the introspection program.

A system, method and computer program product for avoiding a processing flaw in a computer processor triggered by a predetermined sequence of hardware events. The system may include a detecting unit and a power-on reset unit. The detecting unit detects that the predetermined sequence of hardware events is going to occur at the computer processor. The power-on reset unit initializes the computer processor to a state stored in computer memory in response to detecting the sequence of hardware events.

Embodiments relate to a computer implemented information processing system, method and program product for data access. The information processing system includes a data store having a top tier store and at least another tier store with the top tier store including a counter for each entry of a symbol and another tier store including a representative frequency value defined for the another tier store. A sorter is also provided configured to sort the symbol in the top tier store and the another tier stores according to a value generated in the counter for the assessed symbol. The said sorter is also configured to restore entry of the symbol in the top tier store, in response to a symbol having moved from said top tier store to another tier store, by using the representative frequency value defined for said another store to which said symbol was moved.

Memory devices adapted to repair single unprogrammable cells during a program operation, and to repair columns containing unprogrammable cells during a subsequent erase operation. Programming of such memory devices includes determining that a single cell is unprogrammable and repairing the single cell, and repairing a column containing the single cell responsive to a subsequent erase operation.

A double data rate memory physical interface having self checking loopback logic on-chip is disclosed. Disposed on the chip is a first linear feedback shift register, which is capable of generating a set of test data values that comprise at least two data bits. Also disposed on the chip is a second linear feedback shift register. The second linear feedback shift register is capable of generating a set of expected data values that match the test data values. Further, an internal loopback error check element is disposed on the chip. The internal loopback error check element is used to compare the set of expected data values with the set of test data values.

An apparatus is equipped with a storage device including an error correction circuit. The apparatus performs a test of the storage device according to a predetermined testing procedure, and records a time-point at which error correction of the storage device has been performed by the error correction circuit during performance of the test. The apparatus determines, with predetermined accuracy, a first position within the storage device on which the error correction has been performed, based on a test speed at which the test is performed, a time-period from the time-point to current time, and a second position within the storage device on which the test is being performed at the current time. Then, the apparatus performs the test predetermined times on a range included in the storage device and including the first position, according to a testing procedure that has been used at the time-point.

A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to one or more Test Wrappers via an interconnect fabric. The Test Wrappers interface with one or more IP test ports to provide test data, control, and/or stimulus signals to the IP blocks to facilitate circuit-level testing of the IP blocks. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. Test wrappers may also be configured to test multiple IP blocks comprising a test partition.

In a wireless communication system, a compact control signaling scheme is provided for signaling the selected retransmission mode and codeword identifier for a codeword retransmission when one of a plurality of codewords being transmitted over two codeword pipes to a receiver fails the transmission and when the base station/transmitter switches from a higher order channel rank to a lower order channel rank, either by including one or more additional signaling bits in the control signal to identify the retransmitted codeword, or by re-using existing control signal information in a way that can be recognized by the subscriber station/receiver to identify the retransmitted codeword. With the compact control signal, the receiver is able to determine which codeword is being retransmitted and to determine the corresponding time-frequency resource allocation for the retransmitted codeword.

A method and user equipment for simultaneous transmission of a first set of information bits and a second set of information bits by a user equipment, either separately encoded utilizing transmit power or rate matching to increase successful decoding of a set of information bits, or jointly encoding using a priori knowledge or bit positioning to increase successful decoding. Also, the use of joint coding where a first set of information bits is encoded first and then encoded with a second set of information bits, and modulation symbol mapping are provided.

Method and apparatus for managing data in a memory. In accordance with some embodiments, a first data object and an associated first ECC data set are generated and stored in a non-volatile (NV) main memory responsive to a first set of data blocks having a selected logical address. A second data object and an associated second ECC data set are generated responsive to receipt of a second set of data blocks having the selected logical address. The second data object and the second ECC data set are subsequently stored in the in the NV main memory responsive to a mismatch between the first ECC data set and the second ECC data set.

Embodiments of the present invention relate to an apparatus, method, and/or sequence for a distributed ECC that may be used in a storage system. In another embodiment of the invention, an apparatus for handling distributed error correction code (ECC) operations, includes: a plurality of ECC engines configured to perform ECC operations in parallel on multiple data parts; the plurality of ECC engines distributed in parallel to receive some of the multiple data parts that are read from storage media devices and to receive some of the other multiple data parts that are to be written to the storage media devices; and the plurality of ECC engines configured to use respective ECC bytes corresponding to respective ones of the multiple data parts.

Within a radio communication network infrastructure transmitting data organized into a sequence of symbols to a receiving device over a plurality of radio links, data to be transmitted is encoded according to an error correction coding scheme in order to produce a set of systematic symbols and a set of corresponding redundancy symbols; the systematic symbols and a first subset of the corresponding redundancy symbols are transmitted, over a first radio link among said plurality of radio links, in broadcast mode, and a second subset of the corresponding redundancy symbols, distinct from the first one, is transmitted over a second radio link among said plurality of radio links.

According to one embodiment, a memory controller includes: a first flash encoding unit that performs flash encoding on user data according to a first scheme to generate user data flash codes; an encoding unit that performs an error correction encoding process on the user data flash codes to generate parities; a second flash encoding unit that performs flash encoding on the parities according to a second scheme to generate parity flash codes; and a memory I/F that writes the user data flash codes and the parity flash codes to the nonvolatile memory.

A logical operations functional block for an execution unit of a processor includes a first input data link for a first operand and a second input data link for a second operand. The execution unit includes a register connected to an error correction code detection unit. The logical operations functional block includes a look-up table configured to receive an error correction code syndrome from the error correction code detection unit. The logical operations functional block also includes a multiplexer configured to receive an output signal from the look-up table at a first input and the first operand at a second input, wherein an output of the multiplexer is coupled to the first input data link of a logical functional unit.

Embodiments of apparatus and methods for error detection and correction are described. A codeword may have a data portion and associated check bits. In embodiments, one or more error detection modules may be configured to detect a plurality of error types in the codeword. One or more error correction modules coupled with the one or more error detection modules may be further configured to correct errors of the plurality of error types once they are detected by the one or more error detection modules. Other embodiments may be described and/or claimed.

A nonvolatile memory is configured with blocks as deletion units, each block having several pages that are configured as write units. A controller for the nonvolatile memory includes an error correcting circuit, which detects and corrects an error in data read out of a page in one of the blocks of the nonvolatile memory, the page being referenced by a logical address. The controller also determines an error occurrence when the error cannot be corrected. An error block table is provided to store the logical address where the error occurred, and a physical address corresponding to the logical address.

Data is compressed using content addressable memory without disruption despite error using a plurality of content addressable memories to detect sequentially repeating data elements of the data. Compression information is generated for each sequence of repeating data elements that repeat for at least a compression threshold without any one of the plurality of content addressable memories generating an indication of an error for a matching content addressable memory entry. Individual data elements are output for each of the data elements that do not repeat for the compression threshold. Compression information is generated for each sequence of repeating data elements that repeat for at least the compression threshold and then generating a currently searched data element that matches the repeating data elements when any one of the plurality of content addressable memories generates an indication of an error for a content addressable memory entry that matches the currently searched data element.

A method of operating a memory controller to control a memory device includes reading a read vector from the memory device and correcting one or more errors in the read vector, where a power consumed at the correcting is varied according to the number of errors in the read vector.

A method includes determining a read threshold voltage corresponding to a group of storage elements in a non-volatile memory that includes a three-dimensional (3D) memory of a data storage device. The method also includes determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage. The method includes comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event.

A memory device includes a memory chip that stores data, and an external controller that controls the memory chip. The memory chip includes multiple memory cells configured to store data of two or more bits; and an internal controller that executes a program operation for page data including a lower and an upper page program operation, and executes a read operation for page data including a lower and an upper page read operation. The external controller includes an error correction unit that performs error correction encoding on data to be programmed into the memory cell array and performs error correction decoding on data. The internal controller outputs the read page data from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation.

Methods and systems for in-place updating original content stored in a non-volatile storage device and for yielding updated content. Some of the described embodiments illustrate the possibilities for reduction in storage operations, storage blocks, and/or update package size. Some of the described embodiments include the writing of error recovery result(s) such as XOR result(s) which enable the recovery of data in case of an interruption of the update process. In some of the described embodiments, there is re-usage of a protection buffer containing content which is required in the update process.

Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for decoding codewords using a side channel. In various embodiments, a memory controller may be configured to determine that m of n die of non-volatile memory (“NVM”) have failed iterative decoding. In various embodiments, the memory controller may be further configured to generate a side channel from n-m non-failed die and the m failed die other than a first failed die. In various embodiments, the memory controller may be further configured to reconstruct, using iterative decoding, a codeword stored on the first failed die of the m failed die based on the generated side channel and on soft input to an attempt to iteratively decode data stored on the first failed die. In various embodiments, the iterative decoding may include low-density parity-check decoding. Other embodiments may be described and/or claimed.

A packet transmission/reception apparatus and method is provided. The packet transmission method of the present invention includes acquiring a source payload including partial source symbols from a source block, generating a source packet including the source payload and an identifier (ID) of the source payload, generating a repair packet including a repair payload corresponding to the source payload and an ID of the repair payload, generating a Forward Error Correction (FEC) packet block including the source and repair packets, and transmitting the FEC packet block. The source payload ID includes a source payload sequence number incrementing by 1 per source packet. The packet transmission/reception method of the present invention is advantageous in improving error correction capability and network resource utilization efficiency.

A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism.

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate coding in a data processing system.

The present invention discloses a method and apparatus for processing and error correction of a GFP-T superblock, where the 64 bytes of payload data of a first superblock are buffered in the first page of a two-page buffer. The flag byte is buffered in a separate buffer, and a CRC operation is performed in a separate logic element. The result of the CRC operation is checked against a single syndrome table which may indicate single- or multi-bit errors. As the payload data of the first superblock is processed and read out of the first page of the two-page buffer, the payload data of a second superblock is written into the second page of the two-page buffer to be processed and corrected.

A method for decoding and checking a tail-biting convolutional code is provided. The method fully utilizes structural features of the tail-biting convolutional code to re-sort Log-Likelihood Ratio (LLR) values input into a decoder, and by reconstructing a derivative generator polynomial of a convolutional code, allows the decoder to output in serial according to a normal ordering of information bits during backtracking, that is, a first bit of an information sequence is first decoded successfully. Thus, CRC checking may be activated as soon as possible, so that part of the backtracking process and the CRC checking may be performed in parallel, thereby achieving the objective of reducing a processing time delay in decoding and checking the tail-biting convolutional code.