A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.

This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation effect(s) in a circuit simulation, a simulated defect signal level is produced. More specifically, the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and a simulated input signal level of a simulated input signal. As such, the charge degradation effect(s) are simulated externally with respect to the in silico active semiconductor component. In this manner, the in silico active semiconductor component does not need to be reprogrammed in order to simulate charge degradation effects.

A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x−1 switch circuits to connect x−1 data circuits to through silicon vias 1 to x−1 in the group of n adjacent through silicon vias, activating n-x switch circuits to connect n-x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.

A relationship between distance from a back bias control section which outputs a control signal for controlling a back bias of a transistor and an amount of noise in the control signal outputted from the back bias control section is found. An increase of jitter corresponding to the amount of the noise in a clock transmitted on a clock path connected to a circuit section (IP macro) is found on the basis of the relationship between the distance from the back bias control section and the amount of the noise. The circuit section and the clock path are placed on the basis of the increase of the jitter and an allowable jitter value for the circuit section.

A method includes providing a design of a semiconductor device such as a stacked CMOS device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based on at least one predetermined criterion. Each respective one of the at least one first type of circuit element is to be assigned to a respective designated one of the plurality of tiers. The method further includes dividing the remainder of the plurality of circuit elements into at least two groups of circuit elements based on circuit density, and assigning the at least one first type of circuit element and the at least two groups of circuit elements to respectively different ones of the plurality of tiers of the semiconductor device.

A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.

A method for designing a transformer in an integrated circuit includes receiving one or more desired characteristics of the transformer from user input and iteratively determining a design solution for the transformer through one or more simulations and modifications using a rule-set. The method combines the one or more desired characteristics with other preset characteristics of the transformer or the integrated circuit. A first model of the transformer is defined with typical load impedances and simulated having the combined characteristics to determine performance. Results of the simulation are processed to calculate performance with the load impedances specified by the user. The results are further processed to obtain a mathematical model that includes tuning capacitors. The first and subsequent models are modified by drawing on a rule-set of expert knowledge relating to general dependency of at least one design criterion, such as a physical, geometrical or performance characteristic, with another design criterion.

Aspects of the invention relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern may be constructed for a via-type feature group that comprises two or more via-type features in a layout design. A backbone structure may then be determined for the guiding pattern. Based on the backbone structure and a self-assembly model, simulated locations of the two or more via-type features are computed. The simulated locations are compared with targeted locations. If the simulated locations do not match the targeted locations based on a predetermined criterion, the simulated locations adjusted to derive modified locations. Using the modified locations, the above operations may be repeated until the simulated locations match the targeted location based on a predetermined criterion or for a predetermined number of times.

An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

In a method for fracturing or mask data preparation or mask process correction for charged particle beam lithography, a plurality of shots are determined that will form a pattern on a surface, where shots are determined so as to reduce sensitivity of the resulting pattern to changes in beam blur (βf). In some embodiments, the sensitivity to changes in βf is reduced by varying the charged particle surface dosage for a portion of the pattern. Methods for forming patterns on a surface, and for manufacturing an integrated circuit are also disclosed, in which pattern sensitivity to changes in βf is reduced.

A via disposition information acquiring unit acquires via disposition information indicating a disposition of the plurality of first vias (212). A second conductor information acquiring unit acquires second conductor information indicating disposition positions of a plurality of second conductors (232) repeatedly disposed in the second conductor layer (230). A via extracting unit extracts an extraction via with respect to each of the plurality of second conductors (232). The extraction via is each of the first vias (212) overlapping the second conductor (232). A via selecting unit selects a selection via with respect to each of the plurality of second conductors (232). The selection via is each of first vias (212) selected in a predetermined number from the extraction vias. An opening introducing unit introduces a first opening (234) to each of the plurality of second conductors (232). The first opening (234) overlaps the extraction via not selected by the via selecting unit in plan view.

A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.

A method for mask data preparation or mask process correction is disclosed in which a set of charged particle beam shots is determined which is capable of forming a pattern on a surface, wherein critical dimension uniformity (CDU) of the pattern is optimized. In some embodiments the CDU is optimized by varying at least two factors. In other embodiments, model-based techniques are used. In yet other embodiments, the surface is a reticle to be used in an optical lithographic process to form a pattern on a wafer, and CDU on the wafer is optimized.

Methods for the design of microwave filters comprises comprising preferably the steps of inputting a first set of filter requirements, inputting a selection of circuit element types, inputting a selection of lossless circuit response variables, calculating normalized circuit element values based on the input parameters, and generate a first circuit, insert parasitic effects to the normalized circuit element values of the first circuit, and output at least the first circuit including the post-parasitic effect circuit values. Additional optional steps include: requirements to a normalized design space, performing an equivalent circuit transformation, unmapping the circuit to a real design space, performing a survey, and element removal optimization. Computer implement software, systems, and microwave filters designed in accordance with the method are included.

A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least partly on the generated signal behaviour description, and performing gate-level simulation using the generated gate-level stimuli to generate gate-level activity data for the IC design. In one embodiment, generating the signal behaviour description includes performing Register Transfer Level (RTL) simulation of the IC design, and generating the gate-level netlist includes performing RTL synthesis. The RTL simulation and RTL synthesis are performed on RTL data for the IC design.

A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.

A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits reference a top-level circuit or subcircuits (by name or by specific instance), and the simulator automatically binds vunit contents appropriately during circuit hierarchy expansion. Vunits may be re-used for other design cells, and may be easily processed by text-based design tools. Vunits may be provided via vunit_include statements in a control netlist file, command line arguments, or by directly placing a vunit block into a netlist. Vunits may also contain instance statements to monitor or process signals, such as those needed by assertions.

The present disclosure relates a method of performing a design rule checking (DRC) procedure on a multi-tiered integrated chip. In some embodiments, the method is performed by defining layer databases for a plurality of tiers within a multi-tiered integrated chip. The layer databases respectively identify design layers within an associated tier. A DRC (design rule checking) deck is then generated, which defines one or more individual design layer definitions as a function of a plurality of layer databases, so that the one or more individual design layer definitions are defined for a plurality of tiers. One or more design rules for the one or more individual design layer definitions are defined within the DRC deck. Since the individual design layer definitions are defined as functions of the plurality of layer databases, the design rules apply to the plurality of tiers.

A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of horizontal interconnects and gap channels. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. The highest crosstalk may comprise far-end crosstalk or near-end crosstalk and may be calculated for a range of frequencies or for a plurality of frequencies. The crosstalk may be calculated by modeling the interconnects as transmission lines.

Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment.

A method and system for optical proximity correction (OPC) is disclosed in which a set of shaped beam shots is determined which, when used in a shaped beam charged particle beam writer, will form a pattern on a reticle, where some of the shots overlap, where the pattern on the reticle is an OPC-corrected version of an input pattern, and where the sensitivity of the pattern on the reticle to manufacturing variation is reduced. A method for fracturing or mask data preparation is also disclosed.

A circuit-design support method includes obtaining information for a circuit having a logic circuit in which signal lines are connected to input terminals, signals of the signal lines being output via the logic circuit; obtaining information concerning a control circuit that has a first flip-flop for scanning and that can control a value of a given signal line by a value set by the first flip-flop; selecting, based on the circuit information, a second flip-flop at an output destination of a signal from the logic circuit, among second flip-flops of the circuit; and generating, based on the control circuit information, information indicating a serial connection of the control circuit between an output source of the signal of the given signal line and the given signal line and a connection of a data input terminal of the first flip-flop and an output terminal of the selected second flip-flop.

A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective assertions for each of the identified clock signals and identifying potential glitchy logic in respective clock paths for each of the identified clock signals. Finally, the technique includes inserting, at the potential glitchy logic, glitches in each of the respective clock paths of the original RTL file to provide a modified RTL file and executing an RTL simulation using the modified RTL file and the respective assertions.

Methods and systems are described for placing arithmetic operators on a programmable integrated circuit device (e.g., a PLD). Placement of arithmetic operators of a data flow graph in one of multiple regions (e.g., a region of DSP circuitry blocks or a region of logic fabric circuitry) on the programmable integrated circuitry device may be determined (e.g., randomly). A score related to the performance of the graph (e.g., a score related to data flow graph routing delays or area consumed by the data flow graph) may be determined and this process may be repeated after one of the arithmetic operators of the data flow graph is moved. The placement of arithmetic operators that corresponds to the best value for the score related to the performance of the data flow graph may be stored. Accordingly, more arithmetic operators may be included on a programmable integrated device than in conventional devices.

A layout-legalizing system modifies a portion of a circuit layout that is selected by a user to generate a modified portion that satisfies a set of technology constraints and a set of design constraints. The system receives as input the set of technology constraints which a semiconductor manufacturing foundry requires the circuit layout to satisfy for manufacturability purposes. The system also receives a set of design constraints from the user which restricts how objects in the portion of the circuit layout can be modified to satisfy the set of technology constraints. The system can further receive a selection input from the user which identifies the portion of the circuit layout which is to be legalized. The system then modifies the identified portion of the circuit layout to obtain a modified portion which satisfies the set of design constraints and at least a subset of the set of technology constraints.

Disclosed are methods, systems, and articles of manufactures for implementing physical designs by using multiple force models to iteratively morph a layout decomposition. In addition to attractive force model(s) or repulsive force model(s), the physical implementation also uses a containment force model for grouping multiple design blocks or for confining a node of a cell within the boundary of a container. Another aspect is directed at deriving a first force model at the first hierarchical level from a second force model at the second hierarchical level by directly modifying the second model based at least in part on characteristic(s) of the first hierarchical level and of the second hierarchical level. In a design with multiple hierarchies, a cell-based force model is also used to ensure child nodes of a parent cell stay within a close proximity of the parent node of the parent cell.

Aspects of the invention relate to techniques of defect injection for transistor-level fault simulation. A circuit element in a circuit netlist of a circuit is first selected for defect injection. Next, a defect is determined based on whether the selected circuit element is a design-intent circuit element or a parasitic circuit element. After the defect is determined, the defect is injected into the circuit netlist and then the circuit is simulated.

The present invention is directed to provide a resist remover composition for semiconductor substrate which enables to remove a resist simply and easily in the photolithography process in the semiconductor field, and a method for removing a resist comprising that the composition is used. The present invention relates to a resist remover composition for semiconductor substrate, comprising [I] a carbon radical generating agent, [II] an acid, [III] a reducing agent, and [IV] an organic solvent, and having pH of lower than 7, and a method for removing a resist, comprising that the composition is used.

The present invention is a solid rinse aid composition and methods of making and using the same. Applicants have surprisingly found that the crystal modifier sodium xylene sulfonate (short chain alkyl benzene or alkyl naphthalene sulfonates) at higher percentage can act as a solidification agent. The solid rinse aid composition generally includes an short chain alkyl benzene or alkyl naphthalene sulfonates solidification agent and an effective amount of a surfactant which can include a sheeting agent component, defoamer component and/or association disruption agent. The solid rinse aid composition may be phosphate-free, aminocarboxylate-free, and GRAS if desired.

Resist stripping agents useful for fabricating circuits and/or forming electrodes on semiconductor devices for semiconductor integrated circuits and/or liquid crystals with reduced metal and metal alloy etch rates (particularly copper etch rates and TiW etch rates), are provided with methods for their use. The preferred stripping agents contain low concentrations of resorcinol or a resorcinol derivative, with or without an added copper salt, and with or without an added amine to improve solubility of the copper salt. Further provided are integrated circuit devices and electronic interconnect structures prepared according to these methods.

The invention relates to compositions and methods of treatment employing compositions comprising polyelectrolyte complexes. The compositions include a water-soluble first polyelectrolyte bearing a net cationic charge or capable of developing a net cationic charge and a water-soluble second polyelectrolyte bearing a net anionic charge or capable of developing a net anionic charge. The total polyelectrolyte concentration of the first solution is at least 110 millimolar. The composition is free of coacervates, precipitates, latex particles, synthetic block copolymers, silicone copolymers, cross-linked poly(acrylic) and cross-linked water-soluble polyelectrolyte. The composition may be a concentrate, to be diluted prior to use to treat a surface.

Surfactants (e.g., fluorosurfactants) for stabilizing aqueous or hydrocarbon droplets in a fluorophilic continuous phase are presented. In some embodiments, fluorosurfactants include a fluorophilic tail soluble in a fluorophilic (e.g., fluorocarbon) continuous phase, and a headgroup soluble in either an aqueous phase or a lipophilic (e.g., hydrocarbon) phase. The combination of a fluorophilic tail and a headgroup may be chosen so as to create a surfactant with a suitable geometry for forming stabilized reverse emulsion droplets having a disperse aqueous or lipophilic phase in a continuous, fluorophilic phase. In some embodiments, the headgroup is preferably non-ionic and can prevent or limit the adsorption of molecules at the interface between the surfactant and the discontinuous phase. This configuration can allow the droplet to serve, for example, as a reaction site for certain chemical and/or biological reactions. In another embodiment, aqueous droplets are stabilized in a fluorocarbon phase at least in part by the electrostatic attraction of two oppositely charged or polar components, one of which is at least partially soluble in the dispersed phase, the other at least partially soluble in the continuous phase. One component may provide collodial stability of the emulsion, and the other may prevent the adsorption of biomolecules at the interface between a component and the discontinous phase. Advantageously, surfactants and surfactant combinations of the invention may provide sufficient stabilization against coalescence of droplets, without interfering with processes that can be carried out inside the droplets.

A cleansing composition for cosmetic or household use may include an ampholytic polymer; a crosslinked cationic polymer; a surfactant component selected from the group consisting of anionic surfactants, amphoteric surfactants, cationic surfactants, nonionic surfactants, and zwitterionic surfactants; and an aqueous and/or organic carrier.

A new general purpose foaming agent having application as drilling fluid foaming agents or as any foaming agent needed an a wide variety of applications is disclosed, where the agent includes at least one anionic surfactant, at least one cationic surfactant, and mixtures thereof and one or more zwitterionic compounds. A method for using the foaming agent in capillary coiled tubing application is also disclosed. The foaming agents can also include additive to augment the properties of the foaming agent for a given application.

A method for softening laundry employs a softening composition, which includes at least one thickener containing a cationic polymer obtained by polymerization: of a cationic monomer;of a monomer with a hydrophobic nature, of formula (I): wherein R1=H or CH3 R2=alkyl chain having at least 16 carbon atomsX═O, m≧5, y=z=0, orX═NH, m≧z≧5, y=0, orX═NH, m≧y≧5, z=0, of a nonionic monomer.

Disclosed are topical skin compositions and corresponding methods of their use that include an extract from Artabotrys hexapetalus, an extract from Sassafras tzumu, and an extract from Prunus salicina.

An elongated segmented soap bar is segmented longitudinally into a plurality of soap bodies separate and discrete from one another. Adjacent soap bodies are movable with respect to one another between at least two different configurations including at least an arc configuration with the plurality of soap bodies disposed in an arc. At least one coupler couples the plurality of soap bodies together to allow the adjacent soap bodies to move with respect to one another between the at least two different configurations.

A process for preparing a particle defoamer. The particle defoamer of 55%-75% of a carrier, 15%-35% of a silicone emulsion, 3%-10% of a texturing agent and 2%-10% of a solvent, based on the total weight of the particle defoamer; the process for preparing the particle defoamer is: (1)first adding a carrier A1 into a mixer, and then adding thereto a silicone emulsion B1, and stirring uniformly; (2)adding a carrier component A2 to the mixture obtained in (1), and stirring uniformly; (3)adding a silicone emulsion B2 to the mixture obtained in (2), and, after uniformly stirring, adding the solvent thereto and stirring uniformly; and (4)pelleting and drying by baking the mixture obtained in(3), so as to produce the product.

The invention relates to a non-corrosive degreasing concentrate and ready to use formulation. In particular, non-corrosive compositions capable of removing polymerized grease as effectively as some alkali metal hydroxide (i.e. caustic) based degreasers without requiring the use of personal protective equipment are disclosed.

Gemini surfactants of bis-N-alkyl polyether, bis-N-alkenyl polyether, bis-N-cycloalkyl polyether, bis-N-aryl polyether bis-beta or alpha-amino acids or their salts, are produced for use as multifunctional corrosion inhibitors, which protect and prevent corrosion of ferrous metals exposed to acidic, basic and neutral liquids when transporting or storing crude oil and liquid fuels. The surfactants are also used to inhibit corrosion of equipment and pipes used in cooling systems in petroleum and petrochemical equipment. The Gemini surfactants have the structural formula:

The invention describes a stable liquid washing agent or liquid cleaning agent having a yield point and very good dispersing properties. The agents contain anionic and nonionic surfactants as well as inorganic salt and cosurfactant. The invention also relates to the use of the liquid washing agent or liquid cleaning agent, and to a method for manufacturing it.

Compositions and methods for improved cleaning using neutral cleaners are disclosed. In particular, neutral pH cleaning compositions according to the invention employ a synergistic combination of water insoluble surfactants and an anionic hydrotropes capable of forming a stable, low-foaming solution. The neutral cleaning solutions provide significant benefits over water insoluble microemulsions traditionally used for neutral cleaning compositions and provide at least equivalent cleaning efficacy as non-neutral cleaning compositions.

This invention relates to extend the benefits of using hypochlorite compounds such as sodium hypochlorite to clean and disinfect articles while reducing or eliminating the side effects of treating an article with a strong oxidant material. The invention relates to a single step process involving mixing of precursor compositions of a suitable hypohalite or hypohalous acid with a solution of a reducing agent. Optionally a buffer may be present in either or both precursor compositions, such that at time of use such active hypohalous acid concentration in the resulting aqueous mixture remains at a sufficient activity level to effect one or more desired benefits against a target substrate for a desired period of time. The oxidant is substantially consumed by reaction with the reducing agent after the time needed for achieving the desired benefit has passed.

A non-aqueous liquid cleaning composition for applicators used for applying non-aqueous hair removal compositions to the skin. The composition includes a solubilizing oil effective for solubilizing the non-aqueous hair removal composition, e.g., mineral oil, and an effective antibacterial amount of an antibacterial agent, e.g., triclosan. The composition may also include fragrances and additional bacteriocides, e.g., phenoxyethanol. When the applicator is contacted with the heated cleaning composition any hair removal composition and bacteria on the applicator are removed therefrom and the applicator is ready for reuse. It is preferred to use surgical stainless steel applicators. Also provided are methods of using these compositions and kits containing, among other items, such compositions and applicators.

The present invention is directed to provide a semiconductor surface treating agent; composition which is capable of stripping an anti-reflection coating layer, a resist layer, and a cured resist layer in the production process of a semiconductor device and the like easily and in a short time, as well as a method for treating a semiconductor surface, comprising that the composition is used. The present invention relates to a semiconductor surface treating agent; composition, comprising [I] a compound generating a fluorine ion in water, [II] a carbon radical generating agent; , [III] water, [IV] an organic solvent, and [V] at least one kind of compound selected from a group consisting of hydroxylamine and a hydroxylamine derivative represented by the general formula [1], as well as a method for treating the semiconductor surface, comprising that the composition is used: (wherein R1 represents a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups; R2 represents a hydrogen atom, a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups).

Compositions and methods for treating biofilm formation and growth on a substrate are provided. The composition comprises 1 ppb to 1,000 ppm of at least one D-amino acid and 1 ppm to 60,000 ppm of at least one biocide. The method comprises contacting the substrate with 1 ppb to 1,000 ppm of at least one D-amino acid and 1 ppm to 60,000 ppm of at least one biocide. The compositions and methods are effective for preventing, reducing or eliminating biofilm formation or biofilm growth or both, as well as eradicating established, recalcitrant biofilms, particularly biofilms comprising sulfate reducing bacteria that are known to cause microbiologically influenced corrosion, biofouling, or both.

A mixture of surfactants from alkylene oxide adducts with different degrees of alkoxylation is used in a urea solution to be added to an exhaust stream for reduction of nitrous gases.

Provided is a method of manufacturing a superconducting accelerator cavity in which a plurality of half cells having opening portions (equator portions and iris portions) at both ends thereof in an axial direction are placed one after another in the axial direction, contact portions where the corresponding opening portions come into contact with each other are joined by welding, and thus, a superconducting accelerator cavity is manufactured, the half cells to be joined are arranged so that the axial direction thereof extends in a vertical direction; and concave portions that are concave towards an outer side are also formed at inner circumferential surfaces located below the contact portions of the half cells positioned at a bottom; and the contact portions are joined from outside by penetration welding.

An apparatus and method for moving a wire along its own axis against a high resistance to its motion causing a substantial uniaxial compression stress in the wire without allowing it to buckle. The apparatus consists of a wire gripping and moving drive wheel and guide rollers for transporting the moving wire away from the drive wheel. Wire is pressed into a peripheral groove in a relatively large diameter, rotating drive wheel by a set of small diameter rollers arranged along part of the periphery causing the wire to be gripped by the groove.

The present disclosure relates to a superconducting rotating electrical machine and a manufacturing method for a high temperature superconducting film thereof. The superconducting rotating electrical machine includes a stator, and a rotor rotatable with respect to the stator, the rotor having a rotary shaft and a rotor winding. Here, the rotor winding includes tubes disposed on a circumference of the rotary shaft and each forming a passage for a cooling fluid therein, superconducting wires accommodated within the tubes, and a cooling fluid flowing through the inside of the tubes. This configuration may allow for direct heat exchange between the superconducting wires and a refrigerant, resulting in improvement of heat exchange efficiencies of the superconducting wires.