Method and system are provided for managing components of a storage operating environment having a plurality of virtual machines that can access a storage device managed by a storage system. The virtual machines are executed by a host platform that also executes a processor-executable host services module that interfaces with at least a processor-executable plug-in module for providing information regarding the virtual machines and assists in storage related services, for example, replicating the virtual machines.

A processing device comprises a processor coupled to a memory and implements an obligation management system for information technology infrastructure, with the obligation management system being configured to process a plurality of obligations on behalf of a relying party to verify implementation of corresponding controls in information technology infrastructure of a claimant. A given one of the obligations has an associated obligation fulfiller that is inserted or otherwise deployed as a component within the information technology infrastructure of the claimant and is configured to provide evidence of the implementation of one or more of the controls responsive to an obligation assertion so as to establish an associated trust aspect of the claimant. The information technology infrastructure may comprise distributed virtual infrastructure of a cloud service provider. The claimant may comprise the cloud service provider and the relying party may comprise a tenant of the cloud service provider.

Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.

An electronic device for using pause to manage resources is described. The electronic device includes a processor and instructions stored in memory. The electronic device monitors a pause duration and determines whether to perform a resource management operation based on the pause duration. The electronic device performs the resource management operation based on the pause duration.

The technology of the present application provides a networked computer system with at least one workstation and at least one shared resource such as a database. Access to the database by the workstation is managed by a database management system. An access engine reviews job requests for access to the database and allows job requests access to the resource based protocols stored by the system.

A video player instance may be prioritized and decoding and rendering resources may be assigned to the video player instance accordingly. A video player instance may request use of a resource combination. Based on a determined priority a resource combination may be assigned to the video player instance. A resource combination may be reassigned to another video player instance upon detection that the previously assigned resource combination is no longer actively in use.

According to an embodiment, based on task border information, and first-type dependency relationship information containing N number of nodes corresponding to data accesses to one set of data, containing edges representing dependency relationship between the nodes, and having at least one node with an access reliability flag indicating reliability/unreliability of corresponding data access; task border edges, of edges extending over task borders, are identified that have an unreliable access node linked to at least one end, and presentation information containing unreliable access nodes is generated. According to dependency existence information input corresponding to the set of data, conversion information indicating absence of data access to the unreliable access nodes is output. According to the conversion information, the first-type dependency relationship information is converted into second-type dependency relationship information containing M number of nodes (0≦M≦N) corresponding to data accesses to the set of data and containing edges representing inter-node dependency relationship.

Disclosed is an information processing device and a task switching method that can reduce the time required for switching of tasks in a plurality of coprocessors. The information processing device (30) includes a processor core (301); coprocessors (311 to 31n) including operation units (321 to 32n) that perform operation in response to a request from the processor core (301) and operation storage units (331 to 22n) that store the contents of operation of the operation units (321 to 32n), save storage units (351 to 35n) that store the saved contents of operation, a task switching control unit (302) that outputs a save/restore request signal when switching a task on which operation is performed by the coprocessors (311 to 31n), and save/restore units (341 to 34n) that perform at least one of saving of the contents of operation in the operation storage units (331 to 33n) to the save storage units (351 to 35n) and restoration of the contents of operation in the save storage units (351 to 35 n) to the operation storage units (331 to 33n) in response to the save/restore request signal.

Policy enforcement in an environment that includes virtualized systems is disclosed. Virtual machine information associated with a first virtual machine instance executing on a host machine is received. The information can be received from a variety of sources, including an agent, a log server, and a management infrastructure associated with the host machine. A policy is applied based at least in part on the received virtual machine information.

Methods and apparatus are provided for evaluating potential resource capacity in a system where there is elasticity and competition between a plurality of containers. A dynamic potential capacity is determined for at least one container in a plurality of containers competing for a total capacity of a larger container. A current utilization by each of the plurality of competing containers is obtained, and an equilibrium capacity is determined for each of the competing containers. The equilibrium capacity indicates a capacity that the corresponding container is entitled to. The dynamic potential capacity is determined based on the total capacity, a comparison of one or more of the current utilizations to one or more of the corresponding equilibrium capacities and a relative resource weight of each of the plurality of competing containers. The dynamic potential capacity is optionally recalculated when the set of plurality of containers is changed or after the assignment of each work element.

1,4 fullerene deriatives useful for solar cells are provided, where their structures allow for straightforward functionalizations to tune their properties in terms of solubility and LUMO energy levels.

A liquid crystal compound having a high stability to heat, light and so forth, a high clearing point, a low minimum temperature of a liquid crystal phase, a small viscosity, a suitable optical anisotropy, a large dielectric anisotropy, a suitable elastic constant and an excellent solubility in other liquid crystal compounds, a liquid crystal composition containing the compound, and a liquid crystal display device including the composition. The compound is represented by formula (1): wherein, for example, R1 is fluorine or alkyl having 1 to 10 carbons; ring A1 and ring A2 are 1,4-phenylene, or 1,4-phenylene in which at least one of hydrogen is replaced by fluorine; Z1, Z2 and Z3 are a single bond; L1 and L2 are hydrogen or fluorine; X1 is fluorine or —CF3; and m is 1, and n is 0.

To provide a compound, when the compound has both a high clearing point and a low crystallization temperature, having a wide temperature range of a liquid crystal phase and also an excellent solubility in other liquid crystal compounds, and further having general physical properties necessary for the compound, namely, stability to heat, light and so forth, a suitable optical anisotropy and a suitable dielectric anisotropy. A compound is represented by formula (1): wherein, for example, Ra and Rb are alkyl having 1 to 10 carbons; A1, A2, A3 and A4 are 1,4-phenylene; Z1, Z2, Z3 and Z4 are a single bond or alkylene having 1 to 4 carbons; and m, n, q and r are independently 0, 1, or 2, and a sum of m, n, q and r is 1, 2, 3 or 4.

An optically active bisbenzyl compound or a racemic bisbenzyl compound represented by formula (2) that has axial chirality: where: R1 represents a halogen, or an optionally substituted: linear, branched, or cyclic C1-8 alkyl, C2-8 alkenyl, C2-8 alkynyl, C6-14 aryl, C3-8 heteroaryl, linear, branched, or cyclic C1-8 alkoxy, or C7-16 aralkyl;R21 each independently represents hydrogen, halogen, nitro, or an optionally substituted: linear, branched, or cyclic C1-8 alkyl, C2-8 alkenyl, C2-8 alkynyl, C6-14 aryl, linear, branched, or cyclic C1-8 alkoxy, or a C7-16 aralkyl;R3 represents hydrogen, or an optionally substituted: C6-14 aryl, a C3-8 heteroaryl, or a C7-16 aralkyl; andY2 represents a halogen, or an optionally substituted: C1-8 alkylsulfonyloxy, C6-14 arylsulfonyloxy, or C7-16 aralkylsulfonyloxy.

A novel organic compound suitable for emitting green light and an organic light-emitting device including the organic compound are provided. The organic compound is represented by general formula (1). In general formula (1), R1 to R18 are each independently selected from a hydrogen atom, a halogen atom, a substituted or unsubstituted alkyl group, a substituted or unsubstituted alkoxy group, a substituted amino group, a substituted or unsubstituted aryl group, and a substituted or unsubstituted heterocyclic group.

The invention is to provide a new liquid crystal compound having a high clearing point, a good compatibility with other compounds, a small viscosity, and a high stability to heat, light and so forth; compound (1) is provided: R1CF2nR2 (1) wherein, for example, R1 is alkyl having 4 to 10 carbons or —(CH2)2—CH═CH2, R2 is alkyl having 2 to 10 carbons, n is 8, and R1 and R2 are not allowed to be straight-chain alkyl having an identical number of carbons.

The invention relates to a process for the preparation of formula (I) which process comprises pyrolyzing a compound of formula (II) wherein X is chloro or bromo, and to compounds which may be used as intermediates for the manufacture of the compound of formula I and to the preparation of said intermediates.

A process for making a fluorinated olefin having the step of dehydrochlorinating a hydrochlorofluorocarbon having at least one hydrogen atom and at least one chlorine atom on adjacent carbon atoms, preferably carried out in the presence of a catalyst selected from the group consisting of (i) one or more metal halides, (ii) one or more halogenated metal oxides, (iii) one or more zero-valent metals/metal alloys, (iv) a combination of two or more of the foregoing.

A solvent that reversibly converts from a hydrophobic liquid form to hydrophilic liquid form upon contact with water and a selected trigger, e.g., contact with CO2, is described. The hydrophilic liquid form is readily converted back to the hydrophobic liquid form and water. The hydrophobic liquid is an amidine or amine. The hydrophilic liquid form comprises an amidinium salt or an ammonium salt.

A composition and method demulsify a produced emulsion from anionic surfactants and polymer (SP) and alkali, surfactants, and polymer (ASP). The produced emulsion is demulsified into oil and water. In one embodiment, the composition includes a surfactant. The surfactant comprises a cationic surfactant, an amphoteric surfactant, or any combinations thereof.

The invention relates to the use of polymers, containing between 1 and 100 mol % of structural units of the formula (1), wherein R1 means hydrogen or C1-C6 alkyl, A means C2-C4 alkylene groups, and B means C2-C4 alkylene groups, with the stipulation that A is different from B, and x and y mean an integer from 1 to 100 independent of each other, in amounts of 0.01 to 2 wt % relative to the water phase, as gas hydrate inhibitors.

The invention provides for the use of copolymers comprising 1 to 99 mol % of structural units of the formula (1) in which R1 is hydrogen or C1-C6-alkyl, A is C2-C4-alkylene groups and B is C2-C4-alkylene groups, with the proviso that A is different than B, and x, y are each independently an integer of 1-100, and 1 to 99 mol % of structural units of the formula (3) in which R6 is hydrogen or C1-C6-alkyl, D is C2-C4-alkylene groups and z is an integer of 1-50, in amounts of 0.01 to 2% by weight, based on the water phase, as gas hydrate inhibitors.

A heat transfer fluid emulsion includes a heat transfer fluid, and liquid droplets dispersed within the heat transfer fluid, where the liquid droplets are substantially immiscible with respect to the heat transfer fluid and have dimensions that are no greater than about 100 nanometers. In addition, the thermal conductivity of the heat transfer fluid emulsion is greater than the thermal conductivity of the heat transfer fluid.

This invention provides a method related to the preparation of derivatives of poly(ethylene glycol), wherein the method comprises increasing the pH of an aqueous composition comprising a poly(ethylene glycol) bearing a —O—(CH2)n—CO2R3 functional group to result in an aqueous composition comprising a poly(ethylene glycol) bearing a —O—(CH2)n—CO2H functional group, wherein R3 is alkyl and (n) in each instance is 1-6.

The invention relates to polymers that can be obtained by polymerizing the monomers (A), (B), and (D), and optionally (C), where (A) is a monomer of formula (I), wherein A stands for C2 to C4 alkylene, B stands for a C2 to C4 alkylene different from A, R stands for hydrogen or methyl, m stands for a number from 1 to 500, n stands for a number from 1 to 500, (B) is an ethylenically unsaturated monomer that contains at least one carboxylic acid function, (C) is optionally a further ethylenically unsaturated monomer different from (A) and (B), (D) is a monomer of formula (II), wherein D stands for C2 to C4 alkylene, E stands for a C2 to C4 alkylene group different from D, F stands for a C2 to C4 alkylene group different from E, R stands for hydrogen or methyl, o stands for a number from 1 to 500, p stands for a number from 1 to 500, q stands for a number from 1 to 500, and wherein the weight fraction of the monomers is 35 to 99% for the macromonomer (A), 0.5 to 45% for the monomer (B), 0 to 20% for the monomer (C), and 1 to 20% for the monomer (D), and to the use of said polymers as defoamers for inorganic solid suspensions.

Oil-water dispersions and emulsions derived from petroleum industry operations are demulsified and clarified using anionic polymers. Formation of such oil-water dispersion and emulsions is inhibited and mitigated using the anionic polymers. The anionic polymers comprise: A) 2-80% by weight of at least one C3-C8 α,β-ethylenically unsaturated carboxylic acid monomer; B) 15-80% by weight of at least one nonionic, copolymerizable α,β-ethylenically unsaturated monomer; C) 1-50% by weight of one or more of the following monomers: C1) at least one nonionic vinyl surfactant ester; or C2) at least one nonionic, copolymerizable α,β-ethylenically unsaturated monomer having longer polymer chains than monomer B), or C3) at least one nonionic urethane monomer; and, optionally, D) 0-5% by weight of at least one crosslinker.

An object of the present invention is to provide a method for producing a conductive material that allows a low electric resistance to be generated, and that is obtained by using an inexpensive and stable conductive material composition containing no adhesive. The conductive material can be provided by a producing method that includes the step of sintering a first conductive material composition that contains silver particles having an average particle diameter (median diameter) of 0.1 μm to 15 μm, and a metal oxide, so as to obtain a conductive material. The conductive material can be provided also by a method that includes the step of sintering a second conductive material composition that contains silver particles having an average particle diameter (median diameter) of 0.1 μm to 15 μm in an atmosphere of oxygen or ozone, or ambient atmosphere, at a temperature in a range of 150° C. to 320° C., so as to obtain a conductive material.

A manufacturing method of a glass substrate for a magnetic disk is provided whereby nano pits and/or nano scratches cannot be easily produced in polishing a principal face of a glass substrate using a slurry containing zirconium oxide as an abrasive. The manufacturing method of a glass substrate for a magnetic disk includes, for instance, a polishing step of polishing a principal face of a glass substrate using a slurry containing, as an abrasive, zirconium oxide abrasive grains having monoclinic crystalline structures (M) and tetragonal crystalline structures (T).

A method of making cerium-containing metal oxide nanoparticles in non-polar solvent eliminates the need for solvent shifting steps. The direct synthesis method involves: (a) forming a reaction mixture of a source of cerous ion and a carboxylic acid, and optionally, a hydrocarbon solvent; and optionally further comprises a non-cerous metal ion; (b) heating the reaction mixture to oxidize cerous ion to ceric ion; and (c) recovering a nanoparticle of either cerium oxide or a mixed metal oxide comprising cerium. The cerium-containing oxide nanoparticles thus obtained have cubic fluorite crystal structure and a geometric diameter in the range of about 1 nanometer to about 20 nanometers. Dispersions of cerium-containing oxide nanoparticles prepared by this method can be used as a component of a fuel or lubricant additive.

An aqueous delivery system is described including at least one surfactant and at least one water insoluble wetting agent. Further described are low surface energy substrates, such as microporous polytetrafluoroethylene, coated with such an aqueous solution so as to impart a change in at least one surface characteristic compared to the surface characteristics of the uncoated low surface energy substrate.

A vector data access unit includes data access ordering circuitry, for issuing data access requests indicated by elements of earlier and a later vector instructions, one being a write instruction. An element indicating the next data access for each of the instructions is determined. The next data accesses for the earlier and the later instructions may be reordered. The next data access of the earlier instruction is selected if the position of the earlier instruction's next data element is less than or equal to the position of the later instruction's next data element minus a predetermined value. The next data access of the later instruction may be selected if the position of the earlier instruction's next data element is higher than the position of the later instruction's next data element minus a predetermined value. Thus data accesses from earlier and later instructions are partially interleaved.

A statue management section of a control section is provided with a corresponding real number storage section that stores a real number converted from a logical number by a configuration number converting section. When the corresponding real number storage section has stored configuration information with a real number of the next transition state, the state management section directly supplies the real number to the configuration information storage section in the next or later processing cycle.

Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.

A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.

A data processing system and method are disclosed. The system comprises an instruction-fetch stage where an instruction is fetched and a specific instruction is input into decode stage; a decode stage where said specific instruction indicates that contents of a register in a register file are used as an index, and then, the register file pointed to by said index is accessed based on said index; an execution stage where an access result of said decode stage is received, and computations are implemented according to the access result of the decode stage.

A system and method for controlling restarting of instruction fetching using speculative address computations in a processor are provided. The system includes a predicted target queue to hold branch prediction logic (BPL) generated target address values. The system also includes target selection logic including a recycle queue. The target selection logic selects a saved branch target value between a previously speculatively calculated branch target value from the recycle queue and an address value from the predicted target queue. The system further includes a compare block to identify a wrong target in response to a mismatch between the saved branch target value and a current calculated branch target, where instruction fetching is restarted in response to the wrong target.

A technique for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced. The disclosure reduces the cycle delay of the slave processor in accessing the dual-port RAM and the register, thereby effectively reducing the dynamic power consumption of the chip, improving the processing capability of the slave processor and enhancing the effective performance of the slave processor.

A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored.

A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread and the trailing thread preferably being assigned to two different cores. At this time, the leading thread and the trailing thread are simultaneously executed, performing a buffering operation on a thread local area without performing a write operation on a shared memory. When the respective execution results of the two threads match each other, the content buffered to the thread local area is committed and written to the shared memory. When the respective execution results of the two threads do not match each other, the leading thread and the trailing thread are rolled back to a preceding commit point and re-executed.

A hypervisor and one or more guest operating systems resident in a data processing system and hosted by the hypervisor are configured to selectively enable or disable branch prediction logic through separate hypervisor-mode and guest-mode instructions. By doing so, different branch prediction strategies may be employed for different operating systems and user applications hosted thereby to provide finer grained optimization of the branch prediction logic for different operating scenarios.

A method for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.

A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.

An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.

An array of a plurality of processing elements (PEs) are in a data packet-switched network interconnecting the PEs and memory to enable any of the PEs to access the memory. The network connects the PEs and their local memories to a common controller. The common controller may include a shared load/store (SLS) unit and an array control unit. A shared read may be addressed to an external device via the common controller. The SLS unit can continue activity as if a normal shared read operation has taken place, except that the transactions that have been sent externally may take more cycles to complete than the local shared reads. Hence, a number of transaction-enabled flags may not have been deactivated even though there is no more bus activity. The SLS unit can use this state to indicate to the array control unit that a thread switch may now take place.

Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

In accordance with embodiments, there are provided mechanisms and methods for controlling a process using a process map. These mechanisms and methods for controlling a process using a process map can enable process operations to execute in order without necessarily having knowledge of one another. The ability to provide the process map can avoid a requirement that the operations themselves be programmed to follow a particular sequence, as can further improve the ease by which the sequence of operations may be changed.

A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing apparatus also includes another execution unit which performs computation on two operand inputs, one of which is selectable between read data from a register and an immediate value, and the other of which is an immediate value. A control unit determines, based on a received instruction specifying a computation on two operands, whether each of the two operands specifies read data from a register or an immediate value. Depending on the determination result, the control unit causes one of the execution units to execute the computation specified by the received instruction.

A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.