An automatic lock affixed to a cargo container for interconnecting two stacked containers, and for automatically locking and unlocking without reliance upon the overcoming of a friction force to release the device.

A box stop device includes a base member and a raised member attached to the base member. The base member has a top surface and a bottom surface. The top surface may be flat. The bottom surface may be adapted to attach to a desired surface. The raised member may be attached to the base member and may extend approximately vertically from the top surface. The raised member may include a first side and a second side. The first side and the second side may be attached together at an angle of approximately 90 degrees.

A protective cap for a trailing edge of a rotor blade of a wind turbine for use during transportation, handling, or maintenance of the rotor blade is disclosed. The protective cap includes a body having a first leg, a second leg, and a cap member. The cap member connects the first and second legs. Further, the cap member may be configured to cover at least a portion of a trailing edge of the rotor blade and may be configured to provide a gap between an inner surface of the protective cap and the trailing edge. In addition, the first and second legs may resiliently engage the rotor blade.

An apparatus and method for providing a removable anchor for use in tying down a load, or for securing a winch cable for use in recovering a disabled vehicle or other load. The anchor may be removably attached to the deck/bed of a trailer or vehicle (e.g., a car carrier or wrecker/tow truck), using one or more slots or stake pockets located on a cargo surface of the deck. The removable anchor may include: a projection member shaped and sized to fit into a slot on the cargo surface, or to protrude through a stake pocket; a crown attached to, or integrally forming a part of, the projection member, and configured to receive and anchor one or more tie down connectors; and a key attached to, or integrally forming a part of, the projection member. The key can be passed into the slot and manipulated between removable and locked positions. Alternatively, the key may be used to removably secure the anchor to the stake pocket.

A module in the form of a pallet or a closed container includes a grouping together of the electrical devices in an avionics bay, in which the electrical devices are interconnected and attached so as to facilitate the mounting and thus limit the time it takes to mount the electrical devices in the avionics bay.

A fastening system includes an energy absorbing or impact indicator and at least one or more of the following: (1) a fastening base for mounting in an emergency vehicle, (2) a patient support engageable with a base, (3) a patient securement mechanism for securing a patient on a patient support, (4) a patient securement mechanism for securing a patient to a vehicle, (5) a patient support securement mechanism operable to secure a patient support in an emergency vehicle, or (6) a patient support securement mechanism operable to secure a patient support to a base, wherein the energy absorbing or impact indicator is located (1) at the patient securement mechanism, or (2) at the patient support securement mechanism, or wherein the energy absorbing or impact indicator is between (1) the base and the vehicle, (2) the patient support and the base, (3) the patient securement mechanism and the patient support, (4) the patient support and the emergency vehicle, (5) the patient and the emergency vehicle, or (6) the patient securement mechanism and the emergency vehicle, wherein the energy absorbing device or impact indicator has at least an energy absorbing state and a rigid state or indicates a level of impact at or between any of the respective component or components.

A cargo rack for transferring loads between a marine vessel and an offshore marine platform provides a frame having a front, a rear, and upper and lower end portions. The lower end of the frame has a perimeter beam base, a raised floor and a pair of open-ended parallel fork tine tubes that communicate with the perimeter beam at the front and rear of the frame. The frame includes a plurality of fixed side walls extending upwardly from the perimeter beam. A plurality of gates are movably mounted on the frame, each gate being movable between open and closed positions, the gates enabling a forklift to place loads on the floor. The frame has vertically extending positioning beams that segment the floor into a plurality of load-holding positions. Each load holding position has positioning beams that laterally hold a load module in position on the floor.

An apparatus for selectively securing a boat to a trailer may include a hull contact structure for abutting against the boat hull, and a releasable gripping structure positioned adjacent the hull contact structure to engage the boat's securing loop and selectively lock onto the loop to hold the boat to the trailer.

An apparatus and method for applying an underlayment layer to trucking cargo are provided. The underlayment layer may be formed into a roll with a rod disposed therethrough. The roll may be supported by a frame. The roll can be configured to move vertically with respect to the ground. A trailer carrying trucking cargo can be stationed beneath the frame. The underlayment layer may unwound and dispensed from the roll. In order to drape the trucking cargo with the underlayment layer, the roll may be moved horizontally over the frame in addition to or alternatively to having the trucking cargo driven horizontally with respect to the roll.

The combination of: a) a storage unit associated with an over-the-road vehicle, the storage unit having an internal wall surface bounding a storage space and including spaced and facing first and second wall surfaces and a floor surface; and b) a cargo support system. The cargo support system has first and second vertically extending tracks operatively mounted on each to the first and second wall surface and at least a first elongate beam having spaced first and second ends attached respectively to the first and second tracks in an operative position spaced above the floor surface. At least one of the tracks is maintained operatively mounted to the first wall surface through the use of an adhesive.

An edge protector for insertion between a load to be lifted and a lifting member which facilitates the lifting of the load, preventing damage to either the load or the lifting member. The edge protector has a pair of flanges which extend from a radiused or curved center portion. Each flange has an inner surface and an outer surface. A portion of each respective outer surface of each flange is spaced from and is essentially parallel to the inner surface of the respective flange.

An apparatus relates generally to a clock generator is disclosed. The clock generator is coupled to receive an input clock signal and further coupled to provide an output clock signal. An address and control register is coupled to receive an address signal and the output clock signal. An access generator is coupled to receive the output clock signal. The clock generator includes: an input node coupled to receive the input clock signal; at least one pulse generator coupled to the input node to receive the input clock signal and further coupled to provide a clock control signal; and a control gate coupled to the input node to receive the input signal and further coupled to the at least one pulse generator to receive the clock control signal. The clock control signal is provided in a non-toggling state for a high-frequency mode and in a toggling state for a low-frequency mode.

An anti-disassembling device for an electronic product includes a case, a linear movement device, a circular movement device and an optical encoder. At least one retractable transmission member is connected to the case. The circular movement device is located in the case and has an encoding disk, which has multiple slots defined therethrough and teeth are defined in the periphery thereof. The at least one retractable transmission member is engaged with the teeth to rotate the encoding disk. The optical encoder has a lighting module which emits light beams through the slots of the encoding disk and a photosensitive module receives the light beams and sends a signal to the storage unit of the electronic product. The retractable device rotates when the electronic product is disassembled.

A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

A bridge output circuit includes an output terminal, a high side transistor, a low side transistor, a high side driver for controlling a gate voltage of the high side transistor, a low side driver for controlling a gate voltage of the low side transistor, and a controller for controlling the high side and low side drivers. The low side driver includes a first current source, a second current source, and a first assist circuit. The controller is configured to control the turning-on and turning-off states of the first current source, the second current source and the first assist circuit.

An active termination circuit for a differential receiver includes a first receiver element configured to receive a first component of a differential signal, a second receiver element configured to receive a second component of a differential signal, a common mode measurement element configured to receive the differential signal and generate a transmit common mode signal (Vcm) representing an average value of the differential signal, and a receiver (RX) common mode signal node. The termination circuit also comprises an active element configured to receive the transmit common mode signal (Vcm) and provide an output to the receiver common mode signal node, the output configured to drive the value of the signal at the receiver common mode signal node to the value of the transmit common mode signal (Vcm), and a capacitive element coupled to the receiver common mode signal node in parallel with the active element.

A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.

Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

A device for passive equalization and slew-rate control of a signal includes a first branch and a second branch. The first branch includes a first driver coupled in series with an equalization capacitor. The second branch includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch. The first branch may be configurable to enable either passive equalization or slew-rate control of the signal based on a mode control signal.

A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.

Apparatus and methods are provided for an extraction circuit. In one configuration, an apparatus includes: an edge extraction circuit for receiving a first clock signal and outputting a second clock signal, wherein a duty cycle of the second clock is substantially smaller than a duty cycle of the first clock; a transistor for receiving the second clock signal and outputting a current signal; a transmission line for receiving the current signal on a first end and transmitting the current signal to a second end; a termination circuit for receiving the current signal at the second end and converting the current signal into a voltage signal; and an edge detection circuit for outputting a third clock by detecting an edge of the voltage signal. In one embodiment, the edge detection circuit comprises an inverter. In another embodiment, the edge detection circuit comprises a comparator.

A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.

A multi-chip package may include first and second integrated circuit dies that are each partitioned into multiple logic regions. The logic regions of the first and second dies may be coupled via interconnects. Each integrated circuit die may include at least one spare logic region. Multiple logic groups may be formed with each logic group including logic regions from the first and second integrated circuit dies and the interconnects that couple those logic regions. The logic groups may be evaluated to identify defective logic groups. In response to identifying a defective logic group, the defective logic group may be repaired by configuring the first and second integrated circuit dies to stop using the defective logic group and to use a spare logic group. The spare logic group may include spare logic regions of the first and second dies that are coupled by spare logic region interconnects.

An intelligent current drive is disclosed that couples an active current source to a bus line to increase the rate of pull-up and decouples the active current source from the bus line prior to reaching the desired pull-up voltage.

A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

An isolator circuit capable of two-way electrical disconnection and a semiconductor device including the isolator circuit are provided. A data holding portion is provided in an isolator circuit without the need for additional provision of a data holding portion outside the isolator circuit, and data which is to be input to a logic circuit that is in an off state at this moment is stored in the data holding portion. The data holding portion may be formed using a transistor with small off-state current and a buffer. The buffer can include an inverter circuit and a clocked inverter circuit.

Disclosed herein is a device that includes first and second buffer circuits connected to a data terminal and a first control circuit controlling the first and second buffer circuits. The first control circuit receives n pairs of first and second internal data signals complementary to each other from 2n input signal lines and outputs a pair of third and fourth internal data signals complementary to each other to first and second output signal lines, where n is a natural number more than one. The first and second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.

A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M1) pin coupled to a contact bar extending from a first cell of the plurality of cells, and a second metal layer (M2) wire coupled to the contact bar, wherein the contact bar extends across at least one power rail. By extending the contact bar into an open area between the plurality of cells to couple the M1 pin and the M2 wire, routing efficiency and chip scaling are improved.

The present invention relates to a method for downloading a binary configuration file in a programmable circuit implemented in a device. The device comprises at least one central processing unit, a plurality of connectors, and a programmable circuit enabling all or a part of the signals received by said connectors to be processed and transmitted to at least one other circuit of the device. The device analyzes the signals present on the connectors in order to define what other devices are connected and whether the connections are operational. Then, a configuration file is selected from among a set of configuration files according to the operational connections and is downloaded from a memory of the device into the programmable circuit. The invention also relates to a device having a component programmed according to the method previously described.

A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value.

A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

A circuit for a single differential-inductor oscillator with common-mode resonance may include a tank circuit formed by coupling a first inductor with a pair of first capacitors; a cross-coupled transistor pair coupled to the tank circuit; and one or more second capacitors coupled to the tank circuit and the cross-coupled transistors. The single differential-inductor oscillator may be configured such that a common mode (CM) resonance frequency (FCM) associated with the single differential-inductor oscillator is at twice a differential resonance frequency (FD) associated with the single differential-inductor oscillator.

The present disclosure relates to nanoresonator oscillators or NEMS (nanoelectromechanical system) oscillators. A circuit for measuring the oscillation frequency of a resonator is provided, comprising a first phase-locked feedback loop locking the frequency of a controlled oscillator at the resonant frequency of the resonator, this first loop comprising a first phase comparator. Furthermore, a second feedback loop is provided which searches for and stores the loop phase shift introduced by the resonator and its amplification circuit when they are locked at resonance by the first loop. The first and the second loops operate during a calibration phase. A third self-oscillation loop is set up during an operation phase. It directly links the output of the controllable phase shifter to the input of the resonator. The phase shifter receives the phase-shift control stored by the second loop.

A resonator element includes a substrate including a first principal surface and a second principal surface respectively forming an obverse surface and a reverse surface of the substrate, and vibrating in a thickness-shear vibration mode, a first excitation electrode disposed on the first principal surface, and a second excitation electrode disposed on the second principal surface, and being larger than the first excitation electrode in a plan view, the first excitation electrode is disposed so as to fit into an outer edge of the second excitation electrode in the plan view, and the energy trap confficient M fulfills 15.5≦M≦36.7.

A resonator element includes a substrate vibrating in a thickness-shear vibration mode, a first excitation electrode disposed on one principal surface of the substrate, and has a shape obtained by cutting out four corners of a quadrangle, and a second excitation electrode disposed on the other principal surface of the substrate, and a ratio (S2/S1) between the area S1 of the quadrangle and the area S2 of the first excitation electrode fulfills 87.7%≦(S2/S1)

A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.

A self-feedback random generator comprises a digital-to-analog converter, a digital oscillator, a frequency-modulating unit and a first D-type flip-flop. The digital-to-analog converter receives a digital random-code signal and the digital random-code signal is converted to corresponding analog random signal. The frequency-modulating unit modulates frequency of first digital oscillating signal so as to increase random of frequency of first digital oscillating signal according to voltage value of the analog random signal, and accordingly outputs a second digital oscillating signal. The first D-type flip-flop receives the second digital oscillating signal and a clock signal, and reads the second digital oscillating signal through utilizing the clock signal so as to outputs the digital random-code signal, wherein frequency of the clock signal is smaller than frequency of the first digital oscillating signal, and random of frequency of the second digital oscillating signal corresponds to random of the digital random-code signal.

There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer (100), a pulse signal proportional to a fractional phase error occurring between a reference signal and an output signal of a fractional divider (112) for feeding back an output of a VCO (115) of an output stage to a preceding stage is generated using an error signal from an accumulator (120). Through the use of the pulse signal, pulse widths of a UP signal and a DN signal output from a phase detector (140) are controlled so as to reduce a fractional phase error occurring between the UP signal and the DN signal. Thus, the fractional spurious caused by periodically switching the frequency division number of the fractional divider (112) is suppressed.

A digitally controlled oscillator has a high-order ΔΣ modulator configured to be of at least an order higher than a first order and configured to input a digital control signal and output a pseudorandom digital output signal, a first-order ΔΣ modulator configured to input the pseudorandom digital output signal and generate a control pulse signal including a pulse width corresponding to the pseudorandom digital output signal, a low pass filter configured to pass a low frequency component of the control pulse signal, and an oscillator configured to generate a high-frequency output signal whose frequency is controlled based on the control pulse signal outputted by the low pass filter so as to be a frequency corresponding to the digital control signal.

An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.

The invention concerns an oscillator generating a wave composed of a frequency of on the order of terahertz from a beat of two optical waves generated by a dual-frequency optical source. The oscillator includes a modulator the transfer function of which is non-linear for generating harmonics with a frequency of less than one terahertz for each of the optical waves generated by the dual-frequency optical source, an optical detector able to detect at least one harmonic for each of the optical waves generated by the dual-frequency optical source and transforming the harmonics detected into an electrical signal, a phase comparator for comparing the electrical signal with a reference electrical signal, and a module for controlling at least one element of the dual-frequency optical source with a signal obtained from the signal resulting from the comparison.

A digitally-controlled oscillator includes a base frequency generator having an odd number of base inverters connected end-to-end to generate an output signal that oscillates at a predetermined frequency and a frequency-adjusting unit connected to the base frequency generator. The frequency-adjusting unit includes a first string of switchable inverters connected in series with each other, the switchable inverters having sizes that decrease from an input end of the first string to the output end of the first string.

Embodiments provide a multi-phase voltage controlled oscillator (VCO) that produces a plurality of output signals having a common frequency and different phases. In one embodiment, the VCO may include a passive conductive structure having a first ring and a plurality of taps spaced around the first ring. The VCO may further include a capacitive load coupled to the passive conductive structure, one or more feedback structures coupled between a pair of opposing taps of the plurality of taps, and one or more current injection devices coupled between a pair of adjacent taps of the plurality of taps.

The present invention discloses an Oven Controlled Crystal Oscillator and a manufacturing method thereof. The Oven Controlled Crystal Oscillator comprises a thermostatic bath, a heating device, a PCB and a signal generating element, where the signal generating element is used for generating a signal of a certain frequency, the heating device, the PCB and the signal generating element are mounted in the thermostatic bath, the signal generating element is mounted in a groove formed on one side of the PCB, while the heating device is mounted against the other side of the PCB that is opposite to the groove. The signal generating element may be a passive crystal resonator or an active crystal oscillator. The Oven Controlled Crystal Oscillator according to the invention is advantageous for a small volume and a high temperature control precision.

An oscillator outputs a control signal to suppress an influence caused by temperature characteristic of f1 based on a differential signal corresponding to difference between an oscillation output f1 of a first oscillator circuit and an oscillation output f2 of a second oscillator circuit treated as a temperature detection value. A switching unit switches between a first state and a second state. The first state is a state where a first connecting end and a second connecting end are connected to a storage unit for access from an external computer to the storage unit. The second state is a state where the first connecting end and the second connecting end are connected to a first signal path and a second signal path such that the respective f1 and f2 are retrieved from the first connecting end and the second connecting end to an external frequency measuring unit.

An atomic oscillator includes: a gas cell which includes two window portions having a light transmissive property and in which metal atoms are sealed; a light emitting portion that emits excitation light to excite the metal atoms in the gas cell; a light detecting portion that detects the excitation light transmitted through the gas cell; a heater that generates heat; and a connection member that thermally connects the heater and each window portion of the gas cell to each other.

An oscillator configured to oscillate an electromagnetic wave, including: a negative resistance device; a microstrip resonator configured to determine an oscillation frequency of an electromagnetic wave excited by the negative resistance device; a resistance device and a capacitance device, which form a low-impedance circuit configured to suppress parasitic oscillation; and a strip conductor configured to connect the capacitance device of the low-impedance circuit and the microstrip resonator to each other, in which an inductance L of the strip conductor and a capacitance C of the microstrip resonator produce a resonance frequency of ½π√LC, and ¼ of an equivalent wavelength of the resonance frequency is larger than a distance between the negative resistance device and the resistance device of the low-impedance circuit via the strip conductor, is provided.