A modulator generates a baseband digital signal from an information-bearing digital signal. The baseband signal has time-varying phase and amplitude defined by a sequence of complex data words, each having an in-phase (I) component and a quadrature (Q) component. A noise-shaping modulator generates a noise-shaped digital signal from the baseband digital signal such that quantization noise in the noise-shaping modulator is attenuated by a spectral null of its noise transfer function. The spectral null is selected by a noise-shaping parameter corresponding to a selected one of a plurality of output frequencies. A signal converter generates an analog signal conveying the information of the information-bearing digital signal on an analog carrier signal having the selected output frequency.

A signal generator for a transmitter or a receiver for transmitting or receiving RF-signals according to a given communication protocol includes an oscillator and a mismatch compensator. The oscillator is configured to provide a signal generator output signal having a signal generator output frequency and comprises a fine tuning circuit for providing a fine adjustment of the signal generator output frequency based on a fine tuning signal and a coarse tuning circuit for providing a course adjustment of the signal generator output frequency based on a coarse tuning signal. The mismatch compensator is configured to receive the signal generator output signal and compensate a frequency mismatch between a desired signal generator output frequency and the signal generator output frequency generated by the oscillator by providing the fine tuning signal for changing the state of the fine tuning circuit of the oscillator and by providing the coarse tuning signal for changing a state of the coarse tuning circuit of the oscillator. The mismatch compensator provides the coarse tuning signal during a guard period defined in the given communication protocol, during which no RF-signals are transmitted by the transmitter or no RF-signals are to be received by the receiver, such that the state of the coarse tuning circuit is changed within the guard period.

A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one resistance-capacitance (RC) detection result, wherein the digital compensation filter includes an RC compensation module; and tuning the digital compensation filter by inputting the RC detection result into the RC compensation module. For example, the RC detection result may correspond to a detected value representing a product of a resistance value and a capacitance value. In another example, the at least one RC detection result may be obtained by performing RC detection on at least a portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein. An associated digital compensation filter and an associated calibration circuit are also provided.

A new coded continuous phase modulation (CPM) scheme is proposed to enhance physical layer performance of the current DVB-RCS standard for a satellite communication system. The proposed CPM scheme uses a phase pulse design and combination of modulation parameters to shape the power spectrum of CPM signal in order to improve resilience to adjacent channel interference (ACI). Additionally, it uses a low complexity binary convolutional codes and S-random bit interleaving. Phase response using the proposed CPM scheme is a weighted average of the conventional rectangular and raised-cosine responses and provides optimum response to minimize frame error rate for a given data rate.

Techniques and mechanisms for configuring logic to implement a signal modulation. In an embodiment, the logic includes a finite impulse response (FIR) module comprising circuitry. The selection circuitry may be operable to concurrently receive signals from latch circuitry of the FIR module and, based on the signals, to select an input group of the selection circuitry and to output a voltage identifier. In another embodiment, configuration logic is operable to set an operational mode which determines a total number of concurrent input signals, received by the FIR module, which the FIR module will use to select an input group for generating an output representing a voltage level.

A circuit includes a switched modulator stage combining an information signal with a square wave carrier to produce a first modulated signal; and a second modulation stage forming additional steps in the first modulated signal to produce a second modulated signal.

A rail-to-rail comparator including a first comparison unit connected to a first terminal and configured to compare differential input signals to differential reference voltages; a second comparison unit connected to a second terminal and configured to compare the differential input signals to the differential reference voltages; and an output unit configured to be driven in response to a clock signal and to generate a complementary output signal according to comparison results of the first and second comparison units.

An example PWM includes a driver and a two-way oscillator. The oscillator includes, a first frequency adjust current source, a second frequency adjust current source, a capacitor, a switching reference and a comparator. The capacitor integrates a frequency adjust current by charging with the first frequency adjust current source. The capacitor subsequently integrates a second frequency adjust current by discharging with the second frequency adjust current source. The switching reference outputs a first reference voltage and a second reference voltage responsive to an oscillator signal. The comparator compares the output of the switching reference with a voltage on the capacitor. The first and second frequency adjust current sources vary the first and second frequency adjust currents to vary the frequency of the PWM signal to spread energy of switching harmonics over a frequency band and to reduce EMI.

Methods and apparatus for translating duty cycle information in duty-cycle-modulated signals to higher frequencies or higher data rates. An exemplary duty cycle translator includes a duty cycle evaluator, a high-speed digital counter, and a comparator. The duty cycle evaluator generates a first digital number representing a duty cycle of a low-frequency input duty-cycle-modulated (DCM) signal. The comparator compares the first digital number to a second digital number generated by the high-speed digital counter, and generates, based on the comparison, an output DCM signal having a higher frequency or data rate than the frequency or data rate of the low-frequency input DCM signal but a duty cycle that is substantially the same as the duty cycle of the low-frequency input DCM signal.

A communications transmitter includes a baseband processor configured to generate amplitude, angle, in-phase and quadrature baseband signals and a combination modulator that is configurable to modulate in the polar domain and, alternatively, in the quadrature domain. The combination modulator includes a quadrature modulator and a separate and distinct angle modulator that is configured to serve as a local oscillator for the quadrature modulator. In one embodiment of the invention the combination modulator is configured to modulate in the quadrature domain when the transmitter is operating according to a first communications condition (e.g., first transmit power level or first modulation scheme) and is configured to modulate in the polar domain when the transmitter is operating according to a second communications condition (e.g., second transmit power level or second modulation scheme).

A device for mixing multiple (N) pulse density modulated (PDM) bit streams of a bit rate, the device comprises an input logic, an error accumulation circuit, an error correction circuit and an adder of more than N bits; wherein the device is arranged to output an output PDM bit stream that represents a mixture of the multiple input PDM bit streams; wherein the output PDM bit stream comprises a plurality of output PDM bits, wherein a certain output PDM bit of a plurality of output PDM bits that form the output PDM bit stream is generated during a certain clock cycle; wherein the input logic is arranged to select, during each fraction of the certain clock cycle, a current bit of a selected PDM bit stream, wherein different PDM bit streams are selected during different fragments of the certain clock cycle; wherein the error accumulation circuit is arranged to store intermediate values during a first fraction till a penultimate fraction of the certain clock signal and to store a last value during a last fraction of the certain clock signal.

Provided is a method for transmitting data in a communication or broadcasting system using a linear block code by generating a codeword by encoding input information data bits, interleaving the codeword; outputting modulation signal-constituting bits by bit-mapping the interleaved codeword using a bit-mapping table predetermined depending on a modulation scheme and a coding rate, outputting a modulation signal by modulating the modulation signal-constituting bits and transmitting the modulation signal via a transmit antenna.

A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word.

Embodiments of digital high-speed bi-phase modulator and method for bi-phase modulation are generally described herein. In some embodiments, the digital high-speed bi-phase modulator comprises a high-speed digital divider, a high-speed digital multiplexer, and matched signal paths provided between the divider and the multiplexer. The high-speed digital divider is configured to receive a carrier signal and generate complementary output signals. The high-speed digital multiplexer is configured to switch between the complementary output signals and generate a bi-phase modulated output at a carrier frequency (fc) modulated with a bi-phase code. The bi-phase code may be provided to control inputs of the multiplexer.

A radio frequency generator includes a power control module, a frequency control module and a pulse generating module. The power control module is configured to generate a power signal indicating power levels for target states of a power amplifier. The frequency control module is configured to generate a frequency signal indicating frequencies for the target states of the power amplifier. The pulse generating module is configured to (i) supply an output signal to the power amplifier, (ii) recall at least one of a latest power level or a latest frequency for one of the target states of the power amplifier, and (iii) adjust a current power level and a current frequency of the output signal from a first state to a second state based on the power signal, the frequency signal, and at least one of the latest power level and the latest frequency of the power amplifier.

Provided is a method of generating a driving signal for driving a dual mode supply modulator for a power amplifier. The method includes obtaining an envelope of a complex baseband signal to be transmitted, comparing the envelope of the complex signal with a preset threshold value, when a current envelope of the complex signal is the preset threshold value or greater or when there is a result having the preset threshold value or greater in previous N comparisons, outputting a digital board output signal configured with a first logic level through a digital-to-analog converter; and when the current envelope of the complex signal is smaller than the preset threshold value and when there is no result having the preset threshold value or greater in the previous N comparisons, outputting a digital board output signal configured with a second logic level through the digital-to-analog converter.

An apparatus for coding a signal by means of amplitude shift keying comprises a class E amplifier including a switching transistor, to whose gate is supplied a voltage having an operating frequency for operating the class E amplifier. For achieving an amplitude shift keying in the output signal of the class E amplifier, a circuit for switching the operating frequency of the voltage supplied to the gate of the switching transistor, or the resonance frequency of the class E amplifier, between a first value and a second value is provided and in order to switch a deviation degree between the operating frequency and the resonance frequency between a first value and a second value.

In an embodiment, a method of producing a multi-level RF signal includes producing plurality of pulse-width modulated signals based on an input signal. The method further includes driving a corresponding plurality of parallel amplifiers with the plurality of pulse-width modulated signals by setting a parallel amplifier to have a first output impedance when a corresponding pulse-width modulated signal is in an active state and setting the parallel amplifier to have a second output impedance when the corresponding pulse-width is in an inactive state. The method also includes phase shifting the outputs of the plurality of parallel amplifiers, wherein phase shifting transforms the second output impedance into a third impedance that is higher than the second output impedance, and combining the phase shifted outputs.

A transmission device for transmitting a signal in a wireless communication system is provided. The transmission device includes: a serial-to-parallel converter configured to convert an input serial bit stream into a parallel bit stream having three bits; and a phase rotation symbol mapper configured to map the parallel bit stream to a symbol having phase rotation characteristics, wherein when the parallel bit stream includes first to third bits, the phase rotation symbol mapper maps the second and third bits to a complex variable and sequentially maps a real number part and an imaginary number part of the complex variable to the front part and the rear part of a symbol in this order or to the rear part and the front part of the symbol in this order.

According to some embodiments, a method and apparatus are provided to vary a clock signal frequency for a first time period between a lower limit of a range of problematic frequencies and a frequency lower than the lower limit, and vary the clock signal frequency for a second period of time between an upper limit of the range of problematic frequencies and a frequency greater than the upper limit.

A modulation apparatus for a class D switching amplifier is capable of reducing power consumption of an Electro-Migration Interface (EMI) of an output end and a gate driver end in a zero input signal. The modulation apparatus for a class D switching amplifier includes a control unit for detecting and outputting a control signal which is a common signal component of a first modulation signal modulated by using a first input signal and a second modulation signal modulated by using a second input signal; and is characterized by feedback of a first output signal, a second output signal and a common output signal outputted by using the first modulation signal, the second modulation signal and the control signal through an input of the modulation apparatus.

In a method of transmitting a data stream from a transmitter in a multiple-input-multiple-output (MIMO) wireless communication system, where the transmitter comprises a plurality of transmit antennas, a discrete Fourier transform (DFT) is applied to the data stream to generate a plurality of symbol sequences; symbols of a first symbol sequence from the plurality of symbol sequences are paired with symbols of a second symbol sequence from the plurality of symbol sequences to generate a plurality of symbol pairs, wherein the pairing results in an orphan symbol; a space-time block code (STBC) is applied to the symbol pairs to generate a plurality of sets of STBC symbols, each set of STBC symbols being associated with a corresponding one of the plurality of antennas; a cyclic delay diversity (CDD) operation is applied to the orphan symbol to generate a plurality of CDD symbols, each CDD symbol being associated with a corresponding one of the plurality of antennas; and each one of the antennas transmits the corresponding set of STBC symbols and the corresponding CDD symbol.

In various embodiments, systems and methods for generating high-precision pulse-width modulation include a delay-locked loop comprising multiple delay units having time-variable delays, control logic for selecting a subset S of the multiple delay units to thereby generate a time-invariant shift amount having a precision finer than that of a system clock and circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform.

An ultra-wide band frequency modulator is disclosed. The frequency modulator includes a direct modulation phase lock loop that receives a small component. The frequency modulator also includes a delay module that produces a plurality of delay lines. The frequency modulator further includes an edge selector that receives a large component and the plurality of delay lines.

The present invention relates to a digital modulation method and a corresponding modulator. The modulator comprises a transcoder (110) followed by a FIFO register (120) and a 2-PSK modulator (130). The transcoder codes a binary word of fixed size into a code word of variable size using a transcoding table. The transcoding table codes at least one first binary word, leading to a first number of phase transitions at the output of the modulator, into a second word of size greater than that of the first word, leading to, at the output of the modulator, a second number of phase transitions less than the first number of phase transitions.

The present invention provides a digitally controlled, current starved, pulse width modulator (PWM). In the PWM of the present invention, the amount of current from the voltage source to the ring oscillator is controlled by the proposed header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, where the duty cycle can vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations.

Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

A memristor-based emulator including a memristor circuit for use in digital modulation that includes a first current feedback operational amplifier (CFOA) having multiple terminals in communication with a capacitor Cd and in further communication with a resistor Ri. A second CFOA having multiple terminals is in communication with the first CFOA and is adapted to be in further communication with a voltage vM to provide an input current iM for integration by a capacitor Ci. A nonlinear resistor is in communication with the second CFOA. A third CFOA having multiple terminals is in communication with the nonlinear resistor and is in further communication with the first CFOA and a resistor Rd. The third CFOA and the resistor Rd act as an inverting amplifier associated with the nonlinear resistor to increase a current gain to increase a difference between ON and OFF values of a resistance of a realized memristor.

A method for phase modulation of a carrier signal from a transmitter to a contactless transponder in which data is coded as consecutive symbols, each corresponding to a predefined number of carrier cycles, and in which a symbol time is at least two cycles of the carrier signal includes, at the transmitter, spreading a phase jump of a symbol in relation to a preceding symbol over a first part of the symbol time. The establishment of the phase jump is completed in the first part of the symbol time. The periods of the cycles are constant during a second part of the symbol time.

A modulator which has a first terminal to receive a carrier signal, a second terminal to receive a first control signal to control a frequency band of the carrier signal and a third terminal to receive a second control signal to control a modulation depth of the carrier signal.

This disclosure relates to methods and systems to reduce high voltage breakdown jitters in liquid dielectric switches. In particular, dielectric liquids have been produced that contain a suspension of nanoparticles and a surfactant to reduce the breakdown jitter. In one embodiment, the suspended nanoparticles are Barium Strontium Titanate (BST) nanoparticles.

An electromagnetic actuator comprising a core moving between a latched position and an open position, a permanent magnet, a coil designed to generate a first magnetic control flux to move the core from an open position to a latched position, and a second magnetic control flux designed to facilitate movement of the moving core from the latched position to the open position. The permanent magnet is positioned on the moving core so as to be at least partly outside the fixed magnetic circuit in which the first magnetic control flux flows in the open position, and to be at least partly inside the fixed magnetic circuit used for flow of a magnetic polarization flux of the magnet in the latched position.

A driver for a switch in a GIS (Gas Insulation Switchgear) includes a motor, a shaft connected with a moving contact of the switch, a gear connected with one terminal of the shaft and configured to transfer power of the motor to cause the shaft to reciprocate the moving contact through the shaft, a cam spline combined with the shaft and spaced apart from the gear, and a micro-switch connected with the cam spline and configured to control an operation of the motor.

Disclosed are a power transmission device for a vacuum interrupter, and a vacuum breaker having the same. The device includes: a driving link coupled to an adjuster; a driven link coupled to a movable electrode of a vacuum interrupter; connection links configured to connect the driving link and the driven link with each other, and coupled to the driving link and the driven link such that an interval between the driving link and the driven link is varied; cams coupled to the connection links in a perpendicular direction; and cam guides having guide recesses for slidably coupling the cams, and configured to guide the interval between the driving link and the driven link to be changed.

A method of manufacturing a power contactor from an existing contactor having a magnetic amplifier that comprises a blowout coil and a ferromagnetic core, and an arc chute for extinguishing an arc generated by opening the existing contactor under a current load is disclosed. The method includes removing a bolt assembly from the existing contactor and at least one side plate from the existing contactor. The method also includes removing the ferromagnetic core from the existing contactor.

The invention relates to a tap changer for the interruption-free switchover between winding taps of a tap-changing transformer. Furthermore, the present invention relates to a novel vacuum interrupter which is particularly suitable for such a tap changer. The tap changer according to the invention is based on the general concept of combining in each case one main contact (V1) and one mechanical switching means (U1), connected in series therewith, of a first load branch and an additional resistive contact (V3) of a second load branch in only a single vacuum interrupter (1) with a common housing (5). The vacuum interrupter (1) according to the invention is furthermore based on the general inventive concept of replacing the functionalities of two required vacuum interrupters in accordance with the prior art and an additional mechanical switching means with a single vacuum interrupter (1) according to the invention by virtue of combining the design of a vacuum interrupter (1) with a plurality of moveable contact systems (I, II, III), which are arranged in separate vacuum interrupter chambers (2, 3, 4) which are sealed with respect to one another.

An electric switch for application to high- and very high-voltage circuit breakers and switches comprising a flexible toroidal helical spring (8) placed in a groove of a control rod (1) carrying a movable resistance-insertion contact (2), and springs (4) placed about the movable resistance-insertion contact to cause the springs to be compressed until a certain value is reached, at which value the movable resistance-insertion contact causes the flexible toroidal helical spring (8) to deform under pressure enabling the movable resistance-insertion contact (2) to be withdrawn. Among other uses, the switch is suitable for use in a resistance-inserting device that does not need additional mechanical moving parts. For application to high- and very high-voltage circuit breakers and switches.

A circuit interrupter includes, a first contact and a second contact, the second contact being moveable relative to the first contact, a drive assembly structured to move the second contact relative to the first contact, and an erosion monitoring device including a linear transducer coupled to a portion of the drive assembly. The liner transducer is structured to generate an output signal representative of an amount of linear displacement of the portion of the drive assembly, wherein the erosion monitoring device is structured to monitor a degree of erosion of at least one of the first contact and the second contact based on the output signal.

An arc chamber for a circuit breaker has first and second mounting bodies. The mounting bodies are disposed at the ends of an electrically insulating insulation section of the arc chamber. The insulation section is formed of at least two shell-shaped partial sections. The partial sections are curved concavely relative to a longitudinal axis of the arc chamber. A gap is formed between the edges of the bodies of the partial sections.

Provided is a sector gear including: a drive gear having a drive part that forms a part of a circle and has a plurality of teeth and a non-drive part that forms a remaining part of the circle and provides a non-contact angle of at least approximately 90 degrees; first and second movers forming a disconnector and a grounded breaking switch, respectively; and first and second driven gears engaged with the drive gear and respectively engaged with the first and second movers and configured to make the first mover or the second mover operate in conjunction with the drive part of the drive gear according to a direction of rotation of the drive gear, wherein an intermediate angle between the first and second movers is between approximately 90-135 degrees. The present invention can reduce the size of the gas-insulated switchgear having the sector gear.

A circuit breaker including a pair of separable contacts and an arc chamber is provided. The separable contacts include a fixed contact having an upper surface. The arc chamber includes magnetic members disposed on either side of the separable contacts. The magnetic members have a lower surface below the fixed contact upper surface.

A flexible shunt for a vacuum circuit breaker can have a reduced straight length and improved flexibility even with an increased thickness within a predetermined accommodation space of a main circuit part. The flexible shunt comprises a pair of conductive plates, each including a clamp connecting portion configured as a flat conductive member, the clamp connecting portion being connected the clamp, a terminal side connecting portion configured as a flat conductive member, the terminal side connecting portion being connected to the terminal side, and a flexible curved portion configured to connect the clamp connecting portion to the terminal side connecting portion, the flexible curved portion being formed to be projected outwardly.

Circuit breakers include an arc chamber and an arc chute comprising a plurality of arc plates in the arc chamber. The circuit breakers also include a line conductor assembly with at least one arc runner attached to a line conductor in the arc chamber. The arc runner can extend below but adjacent to a bottom arc plate to thereby guide a respective arc into the arc chute.

An arc extinguishing apparatus for a ring main unit includes: a housing; a plurality of fixed contactor assemblies fixed to be protruded toward the center in the housing and formed by inserting a permanent magnet for arc extinguishing by a magnetic force between a pair of main circuit fixed contacts; a plurality of earthing fixed contactors fixed to be protruded toward the center in the housing and installed to be spaced apart from the fixed contactor assemblies at a predetermined angle; a 3-phases common rotational shaft installed to be rotatable at the center of the housing; and a rotatable movable contactor assembly having a plurality of puffer guide plate sections having openings with a narrow opening width to accelerate the velocity of flow of insulating gas to extinguish arc by blowing it, and rotatable to a circuit closing position, an earthing position, and a circuit opening position.

An electrode assembly for a vacuum interrupter is configured such that supporting members can support most of a contact electrode plate and a supporting electrode plate in an axial direction with coil conductors interposed therebetween. Accordingly, an impact generated between electrode assemblies upon a closing operation of the vacuum interrupter may be evenly distributed onto the supporting members, which may result in preventing each of the electrode plates and the coil conductors from being deformed. Also, the supporting members are inserted into the electrode plates and the coil conductors, thereby effectively preventing a current from flowing via the supporting members. In addition, the supporting member may be wide and large so as to simplify an assembly operation and reduce an assembly time.

A removable faceplate for a portable electronic device is provided. The faceplate permits a user to change the physical appearance of a surface of the device while retaining access to the mechanisms for controlling the function of the device. Preferably, the removable faceplate and electronic device are configured with a means for association and dissociation that can be activated without the use of a tool and the means is not visible when the faceplate is attached. Additionally, an improved packaging system is provided to enable a vendor or manufacturer to package faceplates with the devices that they will cover and to allow substitution of faceplates in the packaging without disturbing the packaging of the electronic device itself. Further, there is a method for distribution of the packaging system.

An apparatus is provided for dispensing a roll of sheet material in severable portions therefrom. The apparatus comprises a housing having a rim portion longitudinally offset from a base portion by a sidewall portion extending therebetween. The base and sidewall portions define a compartment for holding the roll of sheet material, and the sidewall portion includes a longitudinally extended dispensing slot formed therethrough communicating with the compartment. The sidewall portion forms about the dispensing slot at least one tapered edge. A lid is detachably coupled to the rim portion of the housing to enclose the compartment, and includes a bottom surface portion. A pivot structure is formed on at least one of the base and bottom surface portions to pivotally engage an axial end of the roll of sheet material for angular displacement thereon.

The present invention provides an assembly for the preparation of a medical device having a porous coating comprising hydrogen peroxide. Particularly interesting medical devices are catheters (such as urinary catheters), endoscopes, laryngoscopes, tubes for feeding, tubes for drainage, guide wires, condoms, urisheaths, barrier coatings e.g. for gloves, stents and other implants, extra corporeal blood conduits, membranes e.g. for dialysis, blood filters, devices for circulatory assistance, dressings for wound care, and ostomy bags. The coating is in particular a hydrophilic coating formed from cross-linked polyvinylpyrrolidone. In one embodiment, the assembly holds a dry catheter element in one compartment of a package and an aqueous hydrogen peroxide solution in another compartment. The solution may also comprise stabilizers, e.g. chelators, and osmolality increasing agents. The catheter for insertion in the urethra is useful for the treatment, alleviation or prophylaxis of microbial infections such as urinary tract infections (UTI).

A housing shell for electrical measuring, controlling and communication devices, in particular the lower housing part of a cellphone, has very great flexural and torsional rigidity in spite of an extremely small wall thickness if it is formed as a part created by a forming operation from the planar blank of a thermoplastically impregnated long-fibered multi-layered mat. Fine-membered functional elements of likewise thermoplastic material are then molded onto the housing shell in an injection mold.

A multi-standard flash-memory-card carrier is about the same size as a thick credit card and fits into a wallet. The multi-standard flash-memory-card carrier has bays that accept flash-memory cards. Larger bays on one side receive SD cards and a Memory Stick Duo card, while micro bays on another side of the carrier receive microSD cards and Memory Stick Micro cards. A carrier spine sandwiched between top and bottom covers has openings forming the bays. Spring-clip tabs on spring-clip fingers fit into notches on the side of the flash-memory cards to secure the flash-memory cards into the multi-standard flash-memory-card carrier to prevent loss. The spring-clip fingers are movable parts of the carrier spine that are deformed during insertion of the flash-memory cards. Both micro and standard flash-memory cards can be carried in the same multi-standard flash-memory-card carrier that can be placed in plastic sleeves for credit cards in a person's wallet.