A method and a device for pressing a book block over the rounded back of a book block having a longitudinal axis extending in the center and along the back. The book block is clamped between two clamping jaws of a clamping device, in a region adjacent to the back of the book block, parallel to the longitudinal axis of the back. A pressing device presses a pressing member against the back, wherein the pressing member is placed approximately in the center of the back onto the book block back. At least a section of the pressing member is then moved across the back. Once the pressing member, which is oriented parallel to the longitudinal axis of the back, is placed onto the back it then moves along at least one continuously preselected movement path over the back.

A drill bit assembly has a bit head and a pin body. The bit head comprises a cutting end, an opposite connecting end with an engagement section, and a feature facing the connecting end. The pin body comprises a tubular body with an axial bore therethrough, a connecting end with an engagement section and a feature facing the connecting end. The drill bit assembly is manufactured by positioning the pin body connecting end with the bit head connecting end such that the pin body and bit head engagement sections overlap with a gap therebetween, and the pin body and bit head features are aligned; injecting a thermoplastic or other connecting material in liquid form between the bit head and pin body engagement sections and into the gap; and solidifying the thermoplastic or other connecting material such that the bit head and pin body are mechanically coupled together at their connecting ends and their features are securely aligned.

A fastener apparatus is disclosed that features projecting locking members that extend and retract when a central drive shaft is rotated. The exterior of the connector has a body that is partially threaded to receive a nut so that two structures (e.g. flanges, panels, plates, beams, etc.) can be pulled together by tightening the bolt when the locking members are in the extended position. In one embodiment, the shaft can be an eyebolt.

The blind rivet for fastening together a plurality of mounted components with mounting holes comprises a rivet body having a sleeve, a flange and a through hole; a mandrel having a slender stem and a head; and a washer. The head of the mandrel is adjacent to the sleeve-side end portion of the rivet body, the stem of the mandrel extends through the rivet body from the flange-side end portion, and the washer is mounted near the flange on the outer periphery of the sleeve of the rivet body. A portion of the outer peripheral surface of the sleeve adjacent to the flange is swaged to form a recessed portion so that the diameter in the other position is enlarged. The washer is pushed onto the enlarged-diameter portion and secured. The mounted components are fastened together between the enlarged end portion of the sleeve and the washer.

An assembly comprising at least two non-metal components which are fixed to each other using at least one fixing system. The fixing system includes a fixing device with a fixing element which is provided with a head and a rod, and a crimping ring which is in contact with one of the components. A protection device is a part of the fixing system which delimits a cavity for confining gas around a portion of the device comprising the crimping ring. In order to improve the repeatability of the operation for positioning the protection device, a guiding device is provided which includes an assembly element on the portion of the fixing device, and an element for guiding the protection device.

A generator stator core through-bolt tensioning device that automatically tightens the nut on the through-bolts that hold together and compress laminate plates of the stator core in a high voltage generator. A controller receives a signal from a measuring device, such as a fiber Bragg grating that measures the strain on the bolt, and based on that signal determines whether the nut needs to be tightened. If the controller determines that tightening is necessary, it will cause the tensioning device to automatically tighten the nut while the generator is in service, and use the measuring device to provide feedback of the tensioning of the through-bolt to know when to stop the device from tightening the nut.

A threaded metal sleeve includes a core and a thread provided on the outside of the core, with the thread profile having a flank angle within the range from 25° to 35°. The pitch (h) of the thread is 0.1-fold to 0.4-fold of the outer diameter of the threaded sleeve, and the thread depth of the thread is 0.02-fold to 0.2-fold of the outer diameter of the threaded sleeve.

Safety apparatuses for objects having at least one nut are disclosed. Contemplated apparatuses comprise a base, one or more nut caps, and one or more electronic sensors configured to acquire data related to a corresponding nut, wheel or tire. In some embodiments, a physical nut rotation indicator that can readily be observed by an operator is included, and a retention wall disposed on the base can operate in conjunction with the physical nut rotation indicator to block a rotation of a nut. Apparatuses are preferably configured to remain stable in harsher environments.

A vibration-isolating screw is disclosed. The vibration-isolating screw includes a screw head and a screw tail portion. The screw head includes a first screw body, a first magnetic element, a second screw body, a second magnetic element, a third screw body and a third magnetic element. The first magnetic element and the second magnetic element are mounted on the first screw body and the second screw body, respectively. The third screw body is mounted between the first screw body and the second screw body. The third magnetic element comprises a first end and a second end and is mounted on the third screw body. The first end and the first magnetic element are adjacent and mutual repulsion. The second end and the second magnetic element are adjacent and mutual repulsion. The screw tail portion is connected with the second screw body.

A method and apparatus for an insulating cover for fasteners. In one advantageous embodiment, an apparatus comprises a washer and a cover. The washer is capable of receiving a fastener. The cover is capable of being secured to the insulating washer, wherein an insulating volume is created with the cover secured to the washer.

A system and method for positioning a tool. The system includes a base member configured to contact a first decking member and a second decking member; at least one base guide including a first end and an opposing second end, the first end coupled to the base member, the at least one base guide configured to position the base member relative to the first decking member and the second decking member; and an adjustable section coupled to the base member, the adjustable section configured to allow adjustment of at least one of a position and an angle of the tool relative to the base member. The system further includes a fastener configured to secure the first and/or second decking members to a joist.

In a mobile terminal having a security function, both convenience and security protection are realized so as to prevent a user from feeling bothersome. A mobile phone has an operation control unit which sets the operation of various functions of the mobile terminal to be unusable at any timing. When a used state determination unit determines that the mobile phone is not in an abnormal state and not left, the operation control unit controls operation of the various functions to maintain usable states.

A method and an anchor for supporting items on a substrate such as drywall. The anchor comprises a structure configured to carry the anchoring element in a minimal cross section configuration through an insertion hole and to effect a first expansion. The anchor further comprises an adjustable cap member configured to be moved to fixedly position the anchoring element to the non-accessible side of the substrate. The anchoring element comprises a base channel member, a top channel member, and a connector-pivoting element configured to pivotally connect the top channel member to the base channel member. The top channel member is configured to be nested with the base channel member in the minimal cross section configuration and to be pivotally rotatable via the connector pivoting element in the plane parallel to the non-accessible side of the wall, with the pivotal rotation of the top channel member providing the second expansion.

In a driving circuit, one output circuit has a scanning signal line, a first transistor which controls electrical connection between the scanning signal line and a clock signal line which has a gate connected to a first node, the first node which is at an active potential in a first time period including a time period during which the active potential is output to the scanning signal line, a second transistor which electrically connects the first node and an inactive signal line which has a potential to open the transistor in a second time period other than the first time period, and the second transistor has a gate connected to a second node, wherein the second node has two kinds of timings to be charged for retaining the active potential.

A shift register and driving method thereof, a gate driving apparatus and a display apparatus, the shift register comprises a pulling-up unit(21), a precharging and resetting unit(22), an output signal terminal at present stage(OUTPUT), a pulling-down unit(23), an input terminal connected to an output signal terminal of a shift register at previous stage(OUTF), an input terminal connected to an output signal terminal of a shift register at next stage(OUTL), and a scan control signal input terminal(INPUT), wherein: the precharging and resetting unit(22) precharges a gate of a first thin film transistor(T1) included in the pulling-up unit(21) and resets its potential; the pulling-down unit(23) pulls down a potential at the gate of the first thin film transistor(T1) and the output signal at present stage after the precharging and resetting unit(22) resets the potential at the gate of the first thin film transistor(T1), so that the pulling-up unit(21) is turned off and the output signal at present stage is at a low level. The present shift register realizes a bidirectional gate driving scan from up to down or from down to up by a conversion control for high-low levels of input signals.

A display panel drive circuit includes a shift register constructed of unit circuits connected in stages. The unit circuits generate signal line selection signals, respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. In at least one embodiment, each of the unit circuits receive (i) clock signals generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal. The clear signal is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register until a subsequent vertical scanning period starts. This configuration achieves a display panel drive circuit which prevents display disorder or holds down increase in load given to a power source, each of which occurs in a case where anomalousness is included in the sync signal.

A scan driving apparatus includes a plurality of sequentially arranged scan driving blocks, each including: a first node configured to receive a first clock signal; a second node configured to receive an input signal according to a second clock signal input; a first transistor having a gate electrode coupled to the first node, a first electrode configured to receive a power source voltage, and a second electrode coupled to an output terminal; and a second transistor having a gate electrode coupled to the second node, a first electrode for receiving a third clock signal, and a second electrode coupled to the output terminal. Each scan driving block is configured to receive the first, second, and third clock signals as a corresponding three clock signals among four clock signals sequentially shifted by a first period, and to output the third clock signal by being synchronized with the input signal.

A stage circuit and a scan driver using the same that is capable of concurrently (e.g., simultaneously) or progressively supplying a scan signal to a plurality of scan lines. The stage circuit includes a progressive driver and a concurrent driver.

Methods, systems and devices are provided for displaying monitored activity data in substantial real-time on a screen of a computing device. One example method includes capturing motion data associated with activity of a user via an activity tracking device. The motion data is quantified into a plurality of metrics associated with the activity of the user. The method includes connecting the activity tracking device with a computing device over a wireless data connection, and sending motion data from the activity tracking device to the computing device for display of one or more of the plurality of metrics on a graphical user interface of the computing device. At least one of the plurality of metrics displayed on the graphical user interface is shown to change in substantial real-time based on the motion data.

A shift register, comprising a plurality of shift register sub-units connected in cascade, each of the plurality of shift register sub-units comprising first to third TFTs, an eleventh TFT, a first capacitor and a first reset control module for controlling the second TFT to be turned on or off. Besides the shift register sub-unit at a first stage, for each of the shift register sub-units at other stages, the second TFT gate control terminal thereof is connected to the third TFT gate control terminal of the shift register sub-unit at a previous stage. Accordingly, a gate driving circuit comprising the shift register and a display comprising the gate driving circuit are provided. Compared with the prior art, reliability of the shift register is highly improved and area occupied by the shift register is smaller.

A shift register includes a plurality of stages of unit circuits each including a flip-flop. Each of the unit circuits generates, by obtaining a sync signal in accordance with an output from the flip-flop, an output signal. The flip-flop includes a first switch and a second switch and a latch circuit for latching a signal supplied thereto and outputting the signal as the output from the flip-flop. A first shift direction signal is supplied to the latch circuit via the first switch, and the second shift direction signal is supplied to the latch circuit via the second switch. In each unit circuit other than those of the first and last stages, an output signal from a previous stage is supplied to a control terminal of the first switch, and an output signal from a subsequent stage is supplied to a control terminal of the second switch.

A shift register of a gate driving circuit includes a pull-up unit for pulling up a first output signal and a first gate signal to a high voltage level according to a driving voltage and a high-frequency clock signal, a start-up unit for transmitting a second gate signal, an energy-store unit for providing the driving voltage to the pull-up unit according to the second gate signal, a first discharging unit for pulling down the driving voltage to a first voltage level according to a first control signal, a first leakage-preventing unit for turning off the first discharging unit when the first gate signal reaches the high voltage level, a first pull-down unit for respectively pulling down the first output and first gate signals to the first and a second voltage levels according to the first control signal, and a first control unit for generating the first control signal.

Methods, devices and system are provided. One method includes capturing activity data associated with activity of a user via a device. The activity data is captured over time, and the activity data is quantifiable by a plurality of metrics. The method includes storing the activity data in storage of the device and, from time to time, connecting the device with a computing device over a wireless communication link. The method defines using a first transfer rate for transferring activity data captured and stored over a period of time. The first transfer rate is used following startup of an activity tracking application on the computing device The method also defines using a second transfer rate for transferring activity data from the device to the computing device for display of the activity data in substantial-real time on the computing device.

A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhance operation speed and reduced power consumption.

The present invention provides a shift register unit, a shift register circuit, an array substrate and a display device, and relates to the area of display manufacturing. The time of the bias working on the de-noising transistor can be reduced without affecting the circuit stability, so that the operational lifespan of the device can be extended. A shift register comprises: a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a de-noising control model. The present invention is used for manufacturing displays.

A shift register includes cascade-connected stages, each of which includes a data latch and an output stage. In at least one embodiment, the latch has a single data input which, in use, receives a date signal from a preceding or succeeding stage. The output stage includes a first switch, which passes a clock signal to the stage output when the output stage is activated by the latch. The output stage also comprises a second switch, which passes the lower supply voltage to the stage output when the output stage is inactive.

A display device including various portions, circuits and other arrangements for outputting various pulses and triggers, for controlling forward shift and backward shift operations.

A display device includes a first-stage output circuit adapted to perform output to a first-stage output signal line as an endmost output signal line out of a plurality of output signal lines disposed in parallel to each other, and the first-stage output circuit includes a start signal line to which a start signal for applying a conducting potential sequentially to the plurality of output signal lines is applied, a first clock signal line to which a first clock signal is applied, a second clock signal line to which a second clock signal is applied, a first transistor having a source to which the first-stage output signal line is connected, and a drain to which the first clock signal line is connected, and a second transistor having a gate to which the start signal line is connected.

A shift register circuit includes a first shift register string and a second shift register string. The first shift register string is configured to receive a first start signal and output a first-stage control signal. The second shift register string, electrically connected to the first shift register string, is configured to receive the first-stage control signal and a second start signal and output the first pulse of a first-stage scan signal according to the first-stage control signal and the second start signal and consequently output the second pulse of the first-stage scan signal according to the second start signal; wherein the first and second pulses are configured to have different pulse widths. A driving method of a shift register circuit is also provided.

A reset circuit for Gate Driver on Array, an array substrate and a display is used for increasing reliability and long-term stability of a GOA circuit and thus improving performance of the GOA circuit. The GOA reset circuit includes a first electronic switch circuit (301) connected to an input terminal of a GOA unit of the Gate Driver on Array (INPUT); and a second electronic switch circuit connected to an output terminal of the GOA unit (OUTPUT), wherein the first electronic switch circuit (301) is connected to a low level signal terminal and is switched on to connect the low level signal terminal to a reset terminal of the GOA unit (RESET) when the input terminal of the GOA unit (INPUT) is at a high level; and the second electronic switch circuit (302) is connected to a high level signal terminal and is switched on to connect the high level signal terminal to the reset terminal of the GOA unit (RESET) when the output terminal of the GOA unit (OUTPUT) is at a high level.

To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.

A stage constituent circuit of a display device drive circuit includes a first-node to a third-node, a thin-film transistor that changes a potential of a scanning signal toward a VDD potential when a potential of the first-node is in a HIGH level, a thin-film transistor that changes a potential of a different stage control signal toward a potential of a clock when a potential of the second-node is in the HIGH level, a capacitor between the first-node and the second-node, and a capacitor between the second-node and the third-node. The potential of the first-node is raised on the basis of a different stage control signal output from the stage constituent circuit in the different stage, and then the potential of the second-node and a potential of the third-node are sequentially raised. Herein, an amplitude of the clock is set to be smaller than an amplitude of the scanning signal.

A semiconductor device that includes transistors having the same polarity consumes less power and can prevent a decrease in amplitude of a potential output. The semiconductor device includes a first wiring having a first potential, a second wiring having a second potential, a third wiring having a third potential, a first transistor and a second transistor having the same polarity, and a plurality of third transistors for selecting supply of the first potential to gates of the first transistor and the second transistor or supply of the third potential to the gates of the first transistor and the second transistor and for selecting whether to supply one potential to drain terminals of the first transistor and the second transistor. A source terminal of the first transistor is connected to the second wiring, and a source terminal of the second transistor is connected to the third wiring.

An active level shift (ALS) driver circuit and a liquid crystal display apparatus including the ALS driver circuit are disclosed. The ALS driver circuit includes an input unit configured to apply a first polarity voltage to a first node and to apply a second polarity voltage to a second node, a level compensation unit configured to adjust the voltages of the first node and the second node, and an output unit configured to alternately output a first power voltage and a second power voltage according to the adjusted voltages of the first and second nodes.

A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.

An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flying-adder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (fs) and the destination frequency (fd). Methods of generating a divided clock signal involving the open loop clock divider circuit are also disclosed.

A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phase-shifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal.

A flip-flop includes: a first, second, third, and fourth transistors; input terminals; and first and second output terminals, the first and second transistors constituting a first CMOS circuit such that gate terminals are connected and drain terminals are connected, the third and fourth transistors constituting a second CMOS circuit such that gate terminals are connected and drain terminals are connected, the first output terminal connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, at least one input transistor included in the group of the first through fourth transistors, a source terminal of the input transistor being connected to one of the input terminals. This can provide a further compact flip-flop.

An output thin film transistor threshold voltage offset compensation circuit, a GOA circuit, and a display. The circuit includes: a first capacitor, comprising a first electrode and a second electrode, the first electrode being connected to the gate of an output thin film transistor and receiving a charge signal, the second electrode being connected to the drain of the output thin film transistor, the first capacitor being used for, under the action of the charge signal, making the first electrode and the second electrode have a same voltage, so that a voltage difference between the drain and the source of the output thin film transistor is equal to a threshold voltage thereof; a first switch unit, connected to the drain and the source of the output thin film transistor, and opening under the action of a first clock signal, so that a voltage difference between the gate and the source of the output thin film transistor is equal to the threshold voltage thereof.

One of the most important RF building blocks today is the frequency synthesizer, or more particularly the programmable frequency divider (divider). Such dividers preferably would support unlimited range with continuous division without incorrect divisions or loss of PLL lock. The inventors present multi-modulus dividers (MMDs) providing extended division range against the prior art and without incorrect divisions as the division ratio is switched back and forth across the boundary between two different ranges. Accordingly, the inventors present MMD frequency dividers without the drawbacks within the prior art.

The present invention relates to a liquid crystal display (LCD) device. More particularly, the present invention relates to an LCD device including a thin film transistor (TFT) compensation circuit in an LCD device which implements a driving circuit by using an oxide TFT, the LCD device capable of compensating for degraded characteristics of a TFT due to threshold voltage shift. As the compensation circuit including a dummy TFT is formed on a non-active area of the LC panel, the degree of threshold voltage shift of the DT due to a DC voltage can be sensed. Based on the sensed result, a threshold voltage of a second TFT can be compensated. This can reduce lowering of a device characteristic.

A stage circuit including an output unit for supplying first or second power source to an output terminal is disclosed. The stage circuit may comprise a bidirectional driver for respectively supplying signals supplied to first and second input terminals, a first driver, and a second driver. The second driver controls the output unit to output the second power source to the output terminal without any voltage loss, corresponding to a second clock signal.

A shift register unit comprises: a first transistor, a pulling-up close unit, a pulling-up start unit, a first pulling-up unit, a second pulling-up unit, a trigger unit, and an output unit. A shift register circuit, an array substrate and a display device are also provided. The shift register unit, the shift register circuit, the array substrate and the display device can reduce drift of a gate threshold voltage of a gate line driving transistor and improve operation stability of devices.

The present invention divides a wire supplying a scan start signal to a gate driver into two wires, so as to avoid overlapping a clock signal line. In this way the clock signal is not delayed by interference, and a gate driving margin may continue uninterrupted, thereby uniformly outputting a gate-on voltage. In particular, if the clock signal line is connected to all stages in the gate driver and the clock signal line overlaps the scan start signal line, unsightly horizontal bands appear on the image and the parallel gate lines generate a very large parasitic capacitance. In contrast, the gate drivers in the present disclosure comprise clock signal lines which do not overlap the scan start signal lines. As benefits, interference resulting in horizontal banding is minimized and the power consumption may be reduced by about 10%.

A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit.

An LCD and a bidirectional shift register device thereof are provided. The bidirectional shift register device of the invention is disposed on the substrate of the panel and includes multi-stages shift registers in series connection. Each stage shift register includes a pre-charging unit, a pull-up unit and a pull-down unit, in which the pre-charging unit receives a first preset clock signal and the output from a (i−1)th stage shift register or a (i+1)th stage shift register so as to thereby output a charging signal. The pull-up unit receives the charging signal and a second preset clock signal so as to thereby output a scan signal. The pull-down unit receives the second preset clock signal, a third preset clock signal and the output from the (i+2)th stage shift register or the (i−2)th stage shift register so as to decide whether or not pulling down the scan signal to a reference level.

A system for optimizing storage in an enclosed transport trailer (6), having transverse bearing beams (2) for supporting a load such as loaded pallets (12, 13) at a mid height of the trailer such that two storage levels are available. The beams have a wheel (10) at each end that runs in a horizontal track (11) attached to each side wall of the trailer, the track enclosing the wheels to prevent them from disengaging from the track. Adjacent beams can be attached together at variable spacings using a spacer bar (15) to suit a particular pallet or load size. The track has a junction adjacent the open end (20) of the trailer that leads up to another track (18) immediately below the roof line where the beams can be moved to an out of the way storage position (19) when not required.