1 Estonian Kroon = 3.8591 Dominican Peso

1 Estonian Kroon = 0.4824 Danish Krone

1 Estonian Kroon = 1.7622 Czech Republic Koruna

1 Estonian Kroon = 39.8906 Costa Rican Colon

1 Estonian Kroon = 273.2001 Colombian Peso

1 Estonian Kroon = 0.496 Chinese Yuan Renminbi

1 Estonian Kroon = 57.9006 Chilean Peso

1 Estonian Kroon = 0.0681 Swiss Franc

1 Estonian Kroon = 0.0983 Canadian Dollar

1 Estonian Kroon = 0.8515 Botswana Pula

1 Estonian Kroon = 0.4019 Brazilian Real

1 Estonian Kroon = 0.4835 Bolivian Boliviano

1 Estonian Kroon = 0.0991 Brunei Dollar

1 Estonian Kroon = 0.0265 Bahraini Dinar

1 Estonian Kroon = 0.1266 Bulgarian Lev

1 Estonian Kroon = 5.9593 Bangladeshi Taka

1 Estonian Kroon = 0.1073 Australian Dollar

1 Estonian Kroon = 4.6607 Argentine Peso

1 Estonian Kroon = 0.1259 Netherlands Antillean Guilder

1 Estonian Kroon = 0.2575 United Arab Emirates Dirham

1 Danish Krone = 8.2586 Macedonian Denar

1 Danish Krone = 2.0728 Estonian Kroon

1 Fiji Dollar = 25.2223 Macedonian Denar

1 Fiji Dollar = 6.3303 Estonian Kroon

1 New Zealand Dollar = 34.8802 Macedonian Denar

1 New Zealand Dollar = 8.7543 Estonian Kroon

1 Croatian Kuna = 8.19 Macedonian Denar

1 Croatian Kuna = 2.0555 Estonian Kroon

1 Peruvian Nuevo Sol = 16.7185 Macedonian Denar

1 Peruvian Nuevo Sol = 4.196 Estonian Kroon

1 Dominican Peso = 1.0325 Macedonian Denar

1 Dominican Peso = 0.2591 Estonian Kroon

1 Papua New Guinean Kina = 16.5657 Macedonian Denar

1 Papua New Guinean Kina = 4.1577 Estonian Kroon

1 Brunei Dollar = 40.2097 Macedonian Denar

1 Brunei Dollar = 10.0919 Estonian Kroon

EDA investor and former executive Jim Hogan is optimistic about automotive electronics, but he has some concerns as well. At the recent Design Automation Conference (DAC 2015), he delivered a speech titled “The Looming Quality, Reliability, and Safety Crisis in Automotive Electronics...Why is it and what can we do to avoid it?"

Hogan gave the keynote speech for IP Talks!, a series of over 30 half-hour presentations located at the ChipEstimate.com booth. Presenters included ARM, Cadence, eSilicon, Kilopass, Sidense, SilabTech, Sonics, Synopsys, True Circuits, and TSMC. Held in an informal setting, the talks addressed the challenges faced by SoC design teams and showed how the latest developments in semiconductor IP can contribute to design success.

Jim Hogan delivers keynote speech at DAC 2015 IP Talks!

Hogan talked about several phases of automotive electronics. These include assisted driving to avoid collisions, controlled automation of isolated tasks such as parallel parking, and, finally, fully autonomous vehicles, which Hogan expects to see in 15 to 20 years. The top immediate priorities for automotive electronics designers, he said, will be government regulation, fuel economy, advanced safety, and infotainment.

More Code than a Boeing 777

According to Hogan, today’s automobiles use 50-100 microcontrollers per car, resulting in a worldwide automotive semiconductor market of around $40 billion. The global market for advanced automotive electronics is expected to reach $240 billion by 2020. Software is growing faster in the automotive market than it is in smartphones. Hogan quoted a Ford vice president who observed that there are more lines of code in a Ford Fusion car than a Boeing 777 airplane.

One unique challenge for automotive electronics designers is long-term reliability. This is because a typical U.S. car stays on the road for 15 years, Hogan said. Americans are holding onto new vehicles for a record 71.4 months.

Another challenge is regulatory compliance. Aeronautics is highly regulated from manufacturing to air traffic control, and the same will probably be true of automated cars. Hogan speculated that the Department of Transportation will be the regulatory authority for autonomous cars. Today, automotive electronics providers must comply with the ISO26262 automotive functional safety specification.

So where do we go from here? “We’ve got to change our mindset,” Hogan said. “We’ve got to focus on safety and reliability and demand a different kind of engineering discipline.” You can watch Hogan’s entire presentation by clicking on the video icon below, or clicking here. You can also watch other IP Talks! videos from DAC 2015 here.

https://youtu.be/qL4kAEu-PNw

Richard Goering

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DAC 2015: See the Latest in Semiconductor IP at “IP Talks!”

Automotive Functional Safety Drives New Chapter in IC Verification

Hi Folks, A question that I've often received from designers, "Is there a method to determine the amount of memory required before I submit a job? I use distributed processing and need to provide an estimate before submitting jobs." The answer...(read more)

ST Microelectronics reported their success with IEEE 1801 / UPF low-power simulation using Incisive Enterprise Simulator at CDNLive India in November 2013. We were able to meet with Mohit Jain just after his presentation and recorded this video that explains the key points in his paper.

With eight years of experience and pioneering technology in native low-power simulation, Mohit was able to apply Incisive Enterprise Simulator to a low-power demonstrator in preparation for use with a production set-top box chip.  Mohit was impressed with the ease in which he was able to reuse his existing IEEE 1801 / UPF code successfully, including the power format files and the macro models coded in his Liberty files. Mohit also discusses how he used the power-aware Cadence SimVision debugger.

The Cadence low-power verification solution for IEEE 1801 / UPF also incorporates the patent-pending Power Supply Network visualization in the SimVision debugger.  You can learn more about that in the Incisive low-power verification Rapid Adoption Kit for IEEE 1801 / UPF here in Cadence Online Support.

Just another happy Cadence low-power verification user!

Regards,

 Adam "The Jouler" Sherer 

hi everyone, 

i'm trying to create a netlist for aging simulation. i would like to simulate how power, Gain and PAE (efficiency) are inlfuenced after 3 hours

i would be grateful if someone can correct my syntax in the netlist since i'm trying to make a sweep HB  simulation where the input power is the parameter.

i did it without any error for the sp (S parameters)  simulation.

you can see the images for both sp and hb simulation netlists. (from left to right: sp aging netlist; hb aging netlist)

i will be grateful if someone can provide me some syntax advices.

thanks,

best regards

Hi, I am in the middle of a design and had no problem going back and forth between schematics and layout. Now I am getting the error message below. I am using Cadence 17.2.

ERROR: Layout database has probably been reverted to an earlier version than that, which was used in the latest flow or the schematic database was synchronized with another board.

The basecopy file generated by the last back-to-front flow not found.

ERROR: Layout database has probably been reverted to an earlier version than that, which was used in the latest flow or the schematic database was synchronized with another board.

The basecopy file generated by the last back-to-front flow not found.

Error: CMFBC-1: The schematic and the layout constraints were not synchronized as the changes done since the last sync up could not be reconciled. Syncing the current version of the schematic or layout databases with a previous version would result in this issue. The  constraint difference report is displayed.

Continuing with "changes-only" processing may result in incorrect constraint updates.

Thanks for your input

Claudia

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Bro is a powerful network analysis framework that is much different from the typical IDS you may know. While focusing on network security monitoring, Bro provides a comprehensive platform for more general network traffic analysis as well. Well grounded in more than 15 years of research, Bro has successfully bridged the traditional gap between academia and operations since its inception. Today, it is relied upon operationally in particular by many scientific environments for securing their cyber-infrastructure. Bro's user community includes major universities, research labs, supercomputing centers, and open-science communities.