In a multiprocessor system, in general, a processor assigned with a larger amount of tasks is apt to perform a larger amount of communication with other processors assigned with tasks, than a processor assigned with a smaller amount of tasks. Thus in order for each processor to be able to perform the routing process efficiently, tasks are assigned such that, when there are a first processor and a second processor, the number of processors each assigned with one or more tasks and directly connected with the second processor being smaller than the number of processors each assigned with one or more tasks and directly connected with the first processor, the amount of tasks assigned to the first processor is equal to or larger than the amount of tasks assigned to the second processor.

A method for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.

A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.

An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.

A data processing device includes processing circuitry 20 for executing a first memory access instruction to a first address of a memory device 40 and a second memory access instruction to a second address of the memory device 40, the first address being different from the second address. The data processing device also includes prefetching circuitry 30 for prefetching data from the memory device 40 based on a stride length 70 and instruction analysis circuitry 50 for determining a difference between the first address and the second address. Stride refining circuitry 60 is also provided to refine the stride length based on factors of the stride length and factors of the difference calculated by the instruction analysis circuitry 50.

A multiprocessor system includes a first microprocessor and a second microprocessor. A first signaling pathway is configured to send message transmission coordination signals from the first microprocessor to the second microprocessor. The first signaling pathway may be coupled to at least two flag registers associated with the second microprocessor. A second signaling pathway is configured to send message transmission coordination signals from the second microprocessor to the first microprocessor. The second signaling pathway may be coupled to at least two flag registers associated with the first microprocessor. The first signaling pathway is independent of the second signaling pathway.

Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

In accordance with embodiments, there are provided mechanisms and methods for controlling a process using a process map. These mechanisms and methods for controlling a process using a process map can enable process operations to execute in order without necessarily having knowledge of one another. The ability to provide the process map can avoid a requirement that the operations themselves be programmed to follow a particular sequence, as can further improve the ease by which the sequence of operations may be changed.

A data processing system arranged for receiving over a network, according to a data transfer protocol, data directed to any of a plurality of destination identities, the data processing system comprising: data storage for storing data received over the network; and a first processing arrangement for performing processing in accordance with the data transfer protocol on received data in the data storage, for making the received data available to respective destination identities; and a response former arranged for: receiving a message requesting a response indicating the availability of received data to each of a group of destination identities; and forming such a response; wherein the system is arranged to, in dependence on receiving the said message.

A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.

A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing apparatus also includes another execution unit which performs computation on two operand inputs, one of which is selectable between read data from a register and an immediate value, and the other of which is an immediate value. A control unit determines, based on a received instruction specifying a computation on two operands, whether each of the two operands specifies read data from a register or an immediate value. Depending on the determination result, the control unit causes one of the execution units to execute the computation specified by the received instruction.

A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.

A processor receives an instruction operation (OP) code from a verification system. The instruction OP code includes instruction bits and forced event bits. The processor identifies a forced event based upon the forced event bits, which is unrelated to an instruction that corresponds to the instruction bits. In turn, the processor executes the forced event.

In an example embodiment, there is described herein an apparatus comprising an interface for communicating with a plurality of digital signal processors and logic operable to send and receive data via the interface. The logic is configured to determine a first set of digital signal processors to be maintained in a ready state, a second set of digital signal processors to be maintained in a first energy saving state, and a third set of digital signal processors to be maintained in a second energy saving state.

A method is disclosed which may include analyzing communication requests in a business process between a client and a server offering a service application to be tested. The method may further include identifying a call to a web service in the analyzed communication. The method may also include determining a location of a Web Service Description Language (WSDL) file relating to the web service on a remote server and downloading the WSDL file from the determined location. A computer readable medium having stored thereon instructions for performing the method and a computer system are also disclosed.

A method of applying formal verification methodologies to event processing applications is provided herein. The method includes the following stages: representing an event processing application as an event processing network, being a graph with event processing agents as nodes; generating a finite state machine based on the event processing network, wherein the finite state machine is an over-approximation of the event processing application; expressing stateful rules and policies that are associated with the event processing application using temporal logic, to yield a temporal representation of the event processing application; combining the temporal representation and the finite state machine into a model; generating a statement associated with a user-selected verification-related property of the event processing application, wherein the statement is generated using the temporal representation; and applying the statement to the model, to yield an indication for: (i) a correctness of the statement or (ii) a counter example, respectively.

Methods, devices, and systems for management of a cloud computing environment for use by a software application. The cloud computing environment may be an N-tier environment. Multiple cloud providers may be used to provide the cloud computing environment.

An aspect of the present invention identifies differences between source codes (e.g. of different versions of a software), when each source code is organized using incorporated files. In one embodiment, in response to receiving identifiers of a first and second source codes (each source code being organized as a corresponding set of code files), listings of the instructions in the first and second source codes are constructed. Each listing is constructed, for example, by replacing each incorporate statement in the source code with instructions stored in a corresponding one of code files. The differences between the first and second source codes are then found by comparing the constructed listings of instructions.

An information processing system, computer readable storage medium, and method for automatically generating human readable and meaningful documentation for one or more source code files. A processor of the information processing system receives one or more source code files containing source code artifacts (SCA) and infers semantics therefrom based on predefined rules. The processor, based on the inferred semantics, extracts documentation from another source code file. The extracted documentation and the inferred semantics are used to generate new human readable and meaningful documentation for the SCA, such new documentation being previously missing from the SCA. The generated new documentation is included with the SCA in one or more source code files.

A system and method may generate unit tests for source code concurrently with API documentation. The system may receive a source code file including several comments sections. Each comments section may include a description of a source code unit such as a class, method, member variable, etc. The description may also correspond to input and output parameters the source code unit. The system and method may parsing the source code file to determine a source code function type corresponding to the unit description and copy the unit description to a unit test stub corresponding to the function type. A developer or another module may then complete the unit test stub to transform each stub into a complete unit test corresponding to the source code unit. Additionally, the system and method may execute the unit test and generate a test result indication for each unit test.

A method is provided for providing consistent logical code across specific programming languages. The method incorporates preprocessor macros in a source computer program code to generate a program control flow. The preprocessor macros can be used to describe program control flow in the source programming language for execution in the source computer program code. The preprocessor macros can also be used to generate control flow objects representing the control flow, which converts the source computer program code into a general language representation. The general language representation when executed is used to output computer programming code in specific programming languages representing the same logical code as that of the source computer program code.

The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.

In one embodiment of the invention, a method is disclosed for modifying a pre-existing application program for multi-processing and/or distributed parallel processing. The method includes searching an application program for a computational loop; analyzing the computational loop to determine independence of the computational transactions of the computational loop; and replacing the computational loop with master code and slave code to provide master-slave execution of the computational loop in response to analyzing the computational loop to determine independence of the computational transactions of the computational loop. Multiple instances of the modified application program are executed to provide multi-processing and/or distributed parallel processing.

In one embodiment, an optimization hint may be included in a business process flow. An executable process may be generated from the business process flow where the optimization hint is included in the executable process. While executing the executable process, the runtime engine encounters an optimization hint and determines an optimization to perform. The optimization hint may be related to an aspect of a business process being orchestrated by the business process flow. The optimization is then performed while executing the executable process. For example, the runtime engine may start pre-processing the branch while the condition is being evaluated. If the condition evaluates such that the pre-processed branch should be executed, then the runtime engine has already started processing of that branch. The processing is thus optimized in that the runtime engine is not sitting idle while waiting for the condition to be evaluated.

This invention relates to a method, computer readable medium, and apparatus for identifying one or more problematic loops in an application. This invention provides a Directed Acyclic Graph or DAG representation of structure of one or more loops in the application by performing a static and a dynamic analysis of the application source code and depicts the loop information as LoopID, loop weight, total loop iteration, average loop iteration, total loop iteration time, average loop iteration time and embedded vector size. This aids a programmer to concentrate on problematic loops in the application and analyze them further for potential parallelism.

Transferring files to a baseboard management controller (‘BMC’) in a computing system, including: receiving, by the BMC, a request to initiate an update of the computing system; identifying, by the BMC, an area in memory within the computing system for storing an update file; and transmitting, by the BMC, a request to register the BMC as a virtual memory device.

Transferring files to a baseboard management controller (‘BMC’) in a computing system, including: receiving, by the BMC, a request to initiate an update of the computing system; identifying, by the BMC, an area in memory within the computing system for storing an update file; and transmitting, by the BMC, a request to register the BMC as a virtual memory device.

A binary library overload instruction is received at an embedded computing device that executes a write-protected firmware build. The binary library overload instruction specifies a write-protected binary library of the write-protected firmware build to be overloaded by execution of an alternative binary library instead of the write-protected binary library of the write-protected firmware build. The alternative binary library is configured within a random access memory (RAM) storage area to execute instead of the write-protected binary library as specified in the received binary library overload instruction. The write-protected firmware build is executed using the alternative binary library instead of the write-protected binary library specified in the binary library overload instruction.

Embodiments provide various techniques for dynamic adjustment of a number of threads for execution in any domain based on domain utilizations. In a multiprocessor system, the utilization for each domain is monitored. If a utilization of any of these domains changes, then the number of threads for each of the domains determined for execution may also be adjusted to adapt to the change.

Methods and systems to identify and reproduce concurrency bugs in multi-threaded programs are disclosed. An example method disclosed herein includes defining a data type. The data type includes a first predicate associated with a first thread of a multi-threaded program that is associated with a first condition, a second predicate that is associated with a second thread of the multi-threaded program, the second predicate being associated with a second condition, and an expression that defines a relationship between the first predicate and the second predicate. The relationship, when satisfied, causes the concurrency bug to be detected. A concurrency bug detector conforming to the data type is used to detect the concurrency bug in the multi-threaded program.

The present invention relates to a process for producing perfume-containing microcapsules having both an aqueous inner phase and an oily inner phase, which can be used in home or personal care products, as well as to the process for producing these microcapsules and the consumer products containing them.

A microcapsule comprising A) a core containing a hydrophobic liquid or wax, B) a polymeric shell comprising a) a polymer formed from a monomer mixture containing: i) 1 to 95% by weight of a hydrophobic mono functional ethylenically unsaturated monomer, ii) 5 to 99% by weight of a polyfunctional ethylenically unsaturated monomer, and iii) 0 to 60% by weight of other mono functional monomer, and b) a further hydrophobic polymer which is insoluble in the hydrophobic liquid or wax. The invention includes a process for the manufacture of particles and the use of particles in articles, such as fabrics, and coating compositions, especially for textiles.

The invention relates to a method of use of certain derivatives of formula (I) in the form of any one of its stereoisomers or a mixture thereof, and wherein R1 represents a hydrogen atom, a C1-4 alkyl or alkenyl group, or a (CHR)2OH group, each R being a hydrogen atom or a methyl group; R2 represents a hydrogen atom or a methyl, ethyl or n-propyl group; and R3 represents a hydrogen atom or a methyl group, as perfuming ingredients. The present invention concerns also certain compounds and compositions or articles containing such compounds.

A perfuming composition capable of prolonging the release of a perfuming component into the surrounding environment when applied on a body surface. The composition includes isocetyl alcohol as a fragrance evaporation modulator in the presence of high amounts of ethanol. Also, consumer articles containing such compositions and methods for the perfuming of a body surface and for increasing the long-lastingness of a perfuming component using these compositions.

An individual alkamide and/or a mixture having two or more different alkamides, is disclosed for changing, masking or reducing the unpleasant flavor impression of an unpleasant-tasting substance or mixture of substances. The alkamide can be trans-pellitorine; cis-pellitorine; 2Z,4Z- or 2Z,4E-decadienoic acid-N-isobutylamide; 2E,4E-decadienoic acid-N-([2S]-2-methylbutyl)amide; 2E,4E-decadienoic acid-N-([2R]-2-methylbutylamide); 2E,4Z-decadienoic acid-N-(2-methylbutyl)amide; achilleamide; sarmentine; 2E- or 3E-decenoic acid-N-isobutylamide; 3E-nonenoic acid-N-isobutylamide; spilanthol; homospilanthol; 2E,6Z,8E-decatrienoic acid-N-([2R]-2-methylbutyl)amide; 2E- or 2Z-decen-4-oic acid-N-isobutylamide; α-sanshool; α-hydroxysanshool; γ-hydroxysanshool; γ-hydroxysanshool; γ-hydroxyisosanshool; γ-dehydrosanshool; γ-sanshool; bungeanool; isobungeanool; dihydrobungeanool; or tetrahydrobungeanool, or combinations thereof.

Absorbent articles provided with an odor control system. The odor control system includes at least two classes of odor control materials, wherein one class acts on malodors or a malodorous substance in the absorbent article and a second class acts on nose receptors. The classes of odor control materials may be selected to provide a synergistic effect in terms of malodor reduction.

The use is described (i)(a) of a single alcohol of formula (1) or(i)(b) of a mixture comprising or consisting of two or more different alcohols of formula (1), wherein in each case one of the two radicals Ra or Rb represents hydrogen and in each case the other radical Ra or Rb represents an acyl radical having 2 to 6 C atoms,for reducing an odororas an auxiliary for reducing an odor.

A perfume tester or perfume includes a granule containing a friable peripheral portion incorporating fragrant compounds, which disintegrates as a perfumed powder when the granule is applied onto the skin. A method for making the perfume tester or perfume is by granulation, and the granule can be used in particular for perfume testing.

Certain surfactants suitable for use alone to dissolve a water-insoluble component in compositions is described for providing VOC-free compressed gas aerosol compositions. The compositions include water-insoluble component(s), a surfactant and water. The water-insoluble component(s) can be active agent(s), such as fragrance(s) and/or an insecticide(s). The surfactant is present as a single surfactant which, in the absence of a solvent, dissolves or disperses the water-insoluble component(s) and provides a homogenous blend in water which provides a stable compressed gas emulsion. The surfactant is an anionic surfactant or a nonionic surfactant, in particular nonionic alkylpolyglycosides; nonionic cocoglucoside; nonionic alkylene oxide extended chain alkylpolyglycosides; anionic sodium lauryl ether sulfate (SLES), nonionic C13-C15 oxoalcohol ethoxylate with 8 ethylene oxides (EO), nonionic C12-C14 secondary alcohol ethoxylate with 7EO or 12EO, polyethylene glycol (PEG) hydrogenated castor oil wherein the PEG is PEG-60 or PEG-40, polyglyceryl-10 laurate and polyglyceryl-6 caprylate.

The present invention primarily concerns certain 4-alkyl pyridines of the following formula (I), wherein R is C8-C12 alkyl, odiferous substance mixtures and aromatic substance mixtures containing these 4-alkyl pyridines, the respective uses thereof as an odiferous or aromatic substance (mixture) and corresponding perfumed products.

The present invention relates to some perfuming ingredients which are esters of formula (I) wherein R1 and R2 represent each a hydrogen atom or a methyl or ethyl group; and R3 represents a C5-C8 group of formula satured or unsatured linear, branched or cyclic group.

Apparatus and method for assessing odors, comprises an electronic nose, to be applied to an odor and to output a structure identifying the odor; a neural network which maps an extracted structure to a first location on a pre-learned axis of odor pleasantness; and an output for outputting an assessment of an applied odor based on said first location. The assessment may be a prediction of how pleasant a user will consider the odor.

(3S,5R)-3,8-dimethyl-5-(prop-1-en-2-yl)-octahydroazulen-1-ols, their use as flavor or fragrance ingredient, and a process of their production by oxidation in the presence of laccase.

Encapsulates, compositions, packaged products and displays comprising such encapsulates, and processes for making and using such encapsulates, compositions, packaged products and displays. Such compositions have improved deposition and retention properties that may impart improved benefit characteristics to a composition and/or situs.

The present invention relates to a process for preparing cyclic compounds having at least eight carbon atoms and at least one keto group, to the cyclic compounds obtained by this process and to the use thereof, in particular as fragrance or for providing a fragrance.

The present invention relates to compounds of formula (I) in the form of any one of its stereoisomers or a mixture thereof, and wherein R1 represents a substituent of the benzene ring and is a bromine atom or a linear, branched or cyclic C1-8 alkyl, alkenyl, alkoxy or alkenyloxy group; R2 represents a C1-3 alkyl group; and R3 represents a hydrogen atom or a methyl or ethyl group; and their use as perfuming ingredients, for instance to impart odor notes of the watery/ozone type.

A fragrance mixture, preferably perfume oil, is described, comprising the constituents (a) (cyclopent-2-enyl ethyl acetate) and additionally (b) one or a plurality of fragrances, preferably with a floral odor note, from the group consisting of alcohols and aldehydes with a molecular weight of 210 g/mol or less and/or (c) one or a plurality of fragrances from the group consisting of ketones, ethers and esters with a molecular weight in the range from 190 g/mol through 250 g/mol.

1-(3/4-isobutyl-1/6-methylcyclohex-3-enyl)methanols and derivatives thereof having appreciable floral and hesperidic odor notes, their use as fragrance ingredient and perfumed products comprising them.