When analyzing multiple sessions simultaneously Verisium Manager crashed and reported below error messages:

# A fatal error has been detected by the Java Runtime Environment:
#
#  SIGSEGV (0xb) at pc=0x00007efc52861b74, pid=14182, tid=18380
#
# JRE version: OpenJDK Runtime Environment Temurin-17.0.3+7 (17.0.3+7) (build 17.0.3+7)
# Java VM: OpenJDK 64-Bit Server VM Temurin-17.0.3+7 (17.0.3+7, mixed mode, sharing, tiered, compressed oops, compressed class ptrs, g1 gc, linux-amd64)
# Problematic frame:
# C  [libucis.so+0x238b74]

......

For more details please refer to the attached log file "hs_err_pid21143.log".

Two approaches were tried to solve this problem but neither has worked.
Method.1:

Setting larger heap size of Java process by "-memlimit" options.For example "vmanager -memlimit 8G".

Method.2:

Enlarging stack memory size limit of the Coverage engine by setting "IMC_NATIVE_STACKSIZE" environment variable to a larger value. For example "setenv IMC_NATIVE_STACKSIZE 1024000"

According to "hs_err_pid*.log" it is almost certain that the memory overflow triggered Java's CrashOnOutOfMemoryError and caused Verisium Manager to crash. There are some arguments about memory management of Java like "Xms, Xmx, ThreadStackSize, Xss5048k etc" and maybe this problem can be fixed by setting these arguments during analysis. However, how exactly does Verisium Manager specify these arguments during analysis? I tried to set them by the form of setting environment variables before analysis but it didn't work in analysis and their values didn't change.

Is there something wrong with my operation or is there a better solution?

Thank you very much.

I'm working on the code coverage. Doing a metrics analysis by default we see overall average grade and overall covered. But when i do a block analysis on an instance i see overall covered grade, code covered grade, block covered grade, statement covered grade, expression covered grade, toggle covered grade.

As I dont know the difference I started to read the IMC user guide and came to know there are 3 things we come across while doing a code coverage local, covered, average

From my understanding

local - child instances metrics doesnt reach the parent level. For example, we have an instance Q and its sub instances like Q.a, Q.b. Block Local grade of Q can be 100% even when its instances Q.a and Q.b a block local grades isnt at 100%.

In the attached image there is formula 

The key difference between average and covered is the weights.

Average : Mathematically taking the above scenario where Q.a, and Q.b has 10 blocks each. Q.a has covered 8 blocks and q.b has covered 2 blocks. Now if we take the normal average it should be total covered/ totatl number = 8+2/10+10 yielding 50%. But when we add weights saying Q.a is 70% and Q.b is 30% the new number would be (8*0.7+2*0.3) / (10*0.7+10*0.3) resulting 62%. Because of the weights we see 12% bump.

Covered: there is no role of weights.

Among these 3 metrics i've changed my default view to this in the image to get more realistic picture when i do analyze metrics. Do you guys agree with the approach?

I'm currently work in coverage analysis. In my design certain register bits remain unused, which could potentially lower toggle coverage. Specifically, I'd like to know how to disable coverage for specific unused register bits within a 32-bit register. For instance, I want to deactivate coverage for bit 17 and bit 20 in a 32-bit register to optimize toggle coverage. Could you please provide guidance on how to accomplish this?

Hello,

I have a question about toggle coverage.

In my case, there are many unused registers or wires that are affecting the toggle coverage score negatively.

Is it possible to automatically exclude registers or wires that are not used from toggle coverage?

My RTL code is as follows, Is it possible to automatically disable tb.top1.b and tb.top1.c without using an exclude file?

module top1;

  reg a;

  reg b;

  reg [31:0] c;

  initial

  begin

  #1 a=1'b0;

  #1 a=1'b1;

  #1 a=1'b0;

  end

endmodule

module tb;

  top1 top1();

endmodule

Hi, I'm using the xcelium simulator to simulate a testbench, in which I first stimulate my design to do something (part "A") and then do a direct follow-up test on the design (part "B").

I need two things from this testbench: the results of the test (part "B", passed/failed) and coverage information, but the coverage information should only include part A and explicitly not part B.

I could do the following: run the testbench with part A and B, get the "passed/failed" result of the test and then follow up another simulator run with another testbench, that only includes part A and get the coverage information from that simulation run.

Is there a way to force xcelium to give me the coverage information of only a part of the simulation? Ideally, I would like to write the verilog code of my testbench to look something like this:

• do A
• dump coverage information
• do B

But maybe there is another way to tell xcelium to consider only part of the testbench for the coverage information. I did have a look at the manual, but was not able to find something useful for this problem. Any ideas?

Hi, 

I am running a regression in order to collect the coverage. However I have an issue. I am setting a signal to 0 when reset is de-asserted  then this signal takes a fixed value when the reset is asserted. 

if(!rst_n) 
init_val= 'b0;

else 

init_val= 31'h34013FF7

the issue is that I got 0%  coverage for the init_value since we only have a rising edge and the signal is not toggling during the simulation. is there an option to collect coverage when there is a rising edge or a falling edge? 

I am running simulation in gui mode using Indago and every time there is UVM_ERROR occur simulation stops. I have to resume it manually. is there any way to disable this feature. 

I have been using the rank feature to identify tests that are redundant in our environment, but then I realized I'd also like to be able to see exactly what coverage goes into increasing the delta_cov value for a given test. If I had a test in my rank report that contributed 0.5% of the delta_cov, how could I got about seeing exactly where that 0.5% was coming from? It seems like that might be part of the correlate function, but I couldn't mange to find a way to see what specific coverage was being contributed for a given test.

In a nutshell, tags allows you to navigate through program code distributed over multiple files effectively. e.g if you see a function call or a struct in e-code and want to "jump" to the definition (which may be in a different file) then you just hit CTRL+] in Vim! Pressing CTRL+t will take you back where you came from. Check out http://vim.wikia.com/wiki/Browsing_programs_with_tags#Using_tags if you want to learn more about how to use tags with Vim.

This utility can generate tags file for your e files. It can either walk through e import order, a directory recursively or all directories on SPECMAN_PATH recursively! The tags file will have tags for struct, unit, types, events, defines, fields, variables, etc.

For help and some examples, just run ctags4e -help.

Attached is the latest revision of the venerable Specman-Matlab package (Lead Application Engineer Jangook Lee is the latest to have refreshed it for a customer in Asia to support 64 bit mode.  Look for a guest blog post from him on this package shortly.)

There is a README file inside the package that gives a detailed overview, shows how to run a demo and/or validate it’s installed correctly, and explains the general test flow.  The test file included in the package called "test_get_cmp_mdim.e" shows all the capabilities of the package, including:

* Using Specman to initialize and tear down the Matlab engine in batch mode

* Issuing Matlab commands from e-code, using the Specman command prompt to load .m files, initializing variables, and other operational tasks.

* Transfering data to and from the Matlab engine to Specman / an e language test bench

* Comparing data of previously retrieved Matlab arrays

* Accessing Matlab arrays from e-code without converting them to e list data structure

* Convert Matlab arrays into e-lists

Happy coding!

Team Specman

The silkscreen layer plays a crucial role in the assembly, repair, and testing of a PCB. You can add a variety of information to this layer, such as the location of the components, polarity, component orientation, on-off switches, LEDs, and testpoint...(read more)

A constraint is a user-defined property, or a rule, applied to a physical object, such as a net, pin, or via in a design. There are a number of constraints that can be applied to an object based on its type and behavior. For example, you can define t...(read more)

Hi,
My Virtuoso and Spectre Version: ICADVM20.1-64b.NYISR30.2
I plot an eye diagram using a built in function. I want to see the data-dependent jitter. I want to measure the eye diagram edges at zero crossing (width of that diamond part) shown in the pic by vertical and horizontal markers. I can put a marker and read the numbers there and get what I want. But now I want to run Monte Carlo and I can't do this for all samples. I wish I could write an expression for this. Unfortunately, I see that the function "cross" is not working on the eye diagram. Basically, when I send the eye diagram data to a table, I see that it actually is just the prbs data and not the eye diagram data. Is there a hack that can help me achieve my goal which is: having an expression to measure the edges of the eye diagram at zero crossing?
There is a script that Andrew wrote (https://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin%3AViewSolution%3BsolutionNumber%3D11395772). This is a good script but it puts all edges on top of each other. I want to distinguish the two edges. In the attached pic (two-period eye diagram) you can see what I mean by the two edges (diamond shapes). I want to measure each of the two and take the maximum. Having all the edges on top of each other won't give me what I want. All edges together will lso include DCD. I purely want to measure DDJ. DCD is measured separately. I have very little experience with writing scripts and could not modify Andrew's script.
Your help is much appreciated. Thank you.

Che(read more)

Hi

I have fixed a SPACING RULE (SP1) for a CLASS_DIFF_PAIR whereas for via associated to the net (DP_VIA), the DISTANCE > 60mils respect to ANY other vias (PTH, BB, TEST vias)

Now my problem is that this rules should NOT be applied for GND VIAS (STICHING VIA) which must be placed at a distance < 40mils respect to DP_VIA

How to create an exemption to the SPACING RULE (SP1)?

I am using OrCAD PCB Designer Standard version 17.4-2019. I want to force update the Package_Height_Max property on the place bound top shape. The footprint library that we've created has that property set in the dra file, but I'd like to override that from capture so I can be certain that the height is correct.

This is coming from a place where we have created a very large footprint library over that past ++ years. Everyone who creates a new footprint is supposed to make sure that we add Package_Height_Max to the footprint, but of course footprints get reused for various parts, not all of which will have the same package height. What I want to do is export a list of package heights from our part database and then import the package heights into Capture and override the package height in the footprint.

I have found a post here  Using Height Property from Orcad Capture which says its not possible, but it also says its from 15 years ago, so maybe things have changed?

Loading new netlist into 23.1 Apparently it does not like many of the specified footprints or padstacks. I have to open the footprint in 231., save the pad stack then save the footprint. This is very time consuming and frustrating to say the least.

I also get the following message

WARNING(SPMHNI-194): Symbol 'SMD_SOD123_ANODE_PIN1' used by RefDes D30 for device 'DIODE_0_SMD_SOD123_ANODE_PIN1_1N4148W-7-F' not found.

The symbol either does not exist in the library path (PSMPATH) or is an old symbol from a previous release.  

Set the correct library path if not set or use dbdo

     The current version of software is unable to open design smd_sod123_anode_pin1.

The design was last saved using version 16.5 and must be updated using DB Doctor. [help]


Going to DB Doctor does nothing, no option to update a footprint?

Tom

Power efficiency is a critical factor in the fast-evolving world of semiconductor design.

The IEEE 1801 standard, also known as UPF (Unified Power Format), was developed by the IEEE to address the intricate challenges associated with power management in contemporary semiconductor designs. This standard offers a uniform framework for defining power domains, power states, and power intent, ensuring consistency across diverse tools and phases of the design process. By utilizing UPF, you can precisely model and regulate power consumption, a critical aspect for battery-operated devices, high-performance computing, and energy-efficient designs.

The key concepts of IEEE 1801 are:

1. Power domains
2. Power states
3. Power gating and isolation
4. Power switches
5. Level shifters, isolation, and retention cells
6. Macro model

Based on these building blocks, you write the power intent of the design.

The power intent for the design includes identifying/implementing low-power strategies that provide a clear description of the power architecture of a design.

The power definitions can effectively manage power consumption and ensure the chip meets its power and performance requirements.

You can start by creating the Power Supply Network, which defines how power is supplied to the design's various power domains and logic cells.

What's the next step to build the file? How do you understand the various concepts related to IEEE 1801? How do you complete the rest of the power intent file?

Relax!

Gear up to attend the training class created just for you to dive deep into the entire format and explore this exciting power specification method/format with hands-on labs in one day!

Training

Fundamentals of IEEE 1801 Low-Power Specification Format Training

This course is a complete tutorial for understanding the fundamentals of IEEE 1801 low-power specification format concepts. You learn about IEEE 1801 power supply networks, ground ports and nets, creating and connecting supply ports/nets, power domain, power switch, power states, defining isolation and level shifter strategies, hierarchical IEEE 1801, and various versions of the IEEE 1801. You also explore how power intent information can be used for a design across various flow stages, such as functional verification, synthesis, logic equivalency checking, place-and-route, test, timing signoff, power integrity, and so forth, using Cadence^® tools.

Labs

We ensure that your learning journey is smooth with hands-on labs covering various design scenarios.

Lab Videos

Now, the exciting part is that to help you further, we have created engaging videos of the training labs. You can refer to the lab module's instructions in demo format at https://support.cadence.com.

Lab Demo: Checking Power Supply Network in IEEE 1801 format and Running IEEE 1801 Quality Checks using Conformal Low Power

Lab Demo: Checking Power Intent for The Macro Connections in IEEE 1801 Format And Running IEEE 1801 Quality Checks using Conformal Low Power 

Online Class

Here is the course link.

Get ready for the most thrilling experience with Accelerated Learning!

The more you know, the faster you go!

Grab the cycle  or hike it, based on your existing knowledge.

Take the quiz and increase your learning pace!!

What's Next?

Grab your Badge after finishing the training and flaunt the expertise you have built up. 😊

Ready to take a tour of this power specification world? Let's help you enroll in this course.

We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information. If you want to ensure you are always the first to know about anything new in training, you can use the SUBSCRIBE button on the landing page to sign up for our regular training newsletters.

Related Short Training Bytes/Videos

Enhance the learning experience with short videos:

Genus Synthesis Solution: Video Library

 Joules RTL Power Solution: Video Library

Related Training

 Low-Power Synthesis Flow with Genus Synthesis Solution

Genus Low-Power Synthesis Flow with IEEE 1801

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In an era of abundant and constantly evolving information, the challenge is not just accessing knowledge but understanding and applying it effectively. AI is a transformative technology that is reshaping how we learn, work, and grow. In this blog, we’ll explore how AI accelerates our knowledge acquisition and understand how it can relate to the process of learning, which connects with our daily lives.

The role of AI is to accelerate knowledge by personalizing learning experiences, providing instant access to information, and offering data-driven insights. AI empowers us to learn more efficiently and effectively in many ways. I won't go into much detail, as we are already busy searching for the meaning of AI and what it can do; however, I want to share one inspiring fact about AI. It can analyze vast amounts of data in seconds, making sense of complex information and providing instantaneous actionable insights or concise answers. I understand that humans are looking to speed up things, which can help us understand technology better and perform our tasks faster.

The main reason AI is in focus is because of its ability to perform tasks faster than ever. We aim to enhance the performance of all our products, including the everyday household electronic items we use. Similarly, are we striving to accelerate the learning process? I am committed to assisting you, and one such method is concise, short (minute-long) videos.

In today's fast-paced world, where attention spans are shorter than ever, the rise of social media platforms has made it easier for anyone to create and share short videos. This is where minute videos come in. These bite-sized clips offer a quick and engaging way to deliver information to the audience with a significant impact. Understanding the definitions of technical terms in VLSI Design can often be accomplished in just a minute.

Below are the definitions of the essential stages in the RTL2GDSII Flow. For further reference, these definitions are also accessible on YouTube.

Want to Learn More?

The Cadence RTL-to-GDSII Flow training is available as both "Blended" and "Live" Please reach out to Cadence Training for further information.

And don't forget to obtain your Digital Badge after completing the training!

• You can check out a free Online Version of the training above, which is available 24/7 for all customers with a Cadence Learning ans Support Portal
• You will also have access to our Training Byte Library then which is full of hundres of troubleshooting videos, like the following: What is Digital Implementation?
• You can find more instructions how to get the best out of the Portal in this blog.
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Binge on Chip Design Concepts this Weekend!

In the era of Artificial Intelligence, front-end designers need a magical key to empower them with technology that enables fully optimized RTL for implementation handoff and provides RTL designers with capabilities to accurately assist in the implementation convergence process.

The magic lies with Cadence Joules RTL Design Studio, an expert system that leverages generative AI for RTL design exploration, triages possible causes of violations, and additional insights that empower designers to understand how to address issues in their RTL, leading to smarter and more efficient chip design.

This unlocks the immense debugging and design analysis capabilities from a single, unified cockpit, enabling fully optimized RTL design prior to implementation handoff for the front-end designers and addresses all aspects of physical design by adding visibility into power, performance, area, and congestion (PPAC)

One critical component is the clock tree, which distributes the clock signal to all sequential elements, such as flip-flops and latches. Designers need the right techniques in the beginning stage to optimize the clock tree structure, ensuring that their designs meet the required timing specifications, reduce power consumption, maintain signal integrity, and increase reliability.

 This incredible feature is part of the Joules RTL Design Studio.

How do you efficiently explore the clock tree structure to optimize the results using Joules RTL Design Studio?

Joules Studio allows viewing a simplified version of the clock structure. This feature is primarily designed to help display clock frequency scaling through clock dividers. You can customize colors, symbols, and design elements using an input file. Additionally, you can cross-probe the custom clock tree structure to other widgets and the main schematic view in Joules Studio.

Moreover, with the clock tree preference features of the ideal clock tree wizard in Joules Studio GUI, you can highlight clock path, generate clocks and master clock, set case analysis, fold and unfold instances, undo and redo, set sense and disable timing, color preference, etc.

You can binge on these features through the channel videos posted on the support portal, which covers the Joules RTL Design Studio GUI Clock Tree Structure and Features of Ideal Clock Tree Wizard.

You can refer to the videos on Cadence Online Support (Cadence login required).

​Video Links:
Viewing Custom Clock Tree Structure in Joules RTL Design Studio (Video) 

Exploring Clock Tree Preference Widget of Ideal Clock Tree Wizard in Joules RTL Design Studio (Video) 

Want to learn more?

Explore the one-stop solution Joules RTL Design Studio Product Page on Cadence Online Support (Cadence login required).

Related Resources 

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Understanding Prototype Design Flow in Joules RTL Design Studio (Video)

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Understanding Analyze Timing By Hierarchy In Joules RTL Design Studio (Video)

Related Courses:

• Joules Power Calculator

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