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NFL Power Rankings: 1-32 poll, plus post-draft winners for every team

Ben Roethlisberger and Chandler Jones got some support in the NFL draft, while Alvin Kamara's importance was cemented even more.




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AMBA Adaptive Traffic Profiles: Addressing The Challenge

Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components and calculation power to accommodate new performance-hungry applications such as machine learning and autonomous driving.  With increased number of SoC components, such as CPUs, GPUs, accelerators and I/O devices, comes increased demand to correctly model interoperability of various components. Traditional simulation of complex systems requires accurate models of all components comprising the system and normally results in very long simulation times. A better way is to create a set of typical traffic profiles which describe behavior of system’s masters and slaves. Such profiles should be abstract to be applied to various protocols and interfaces and be portable to be applied throughout different SoC design and verification cycles.

To address the challenges outlined above, Arm has recently announced availability of the AMBA® Adaptive Traffic Profiles (AMBA ATP) specification which lays foundation of a new synthetic traffic framework. The AMBA ATP specification includes detailed information of various transaction types and timing characteristics of those transactions. The traffic profiles defined in the specification are abstract in nature and thus could be used to generate stimuli for various standard AMBA protocols and in various environments such as RTL-based simulation, FPGA prototyping and final SoC verification. The traffic profiles outlined in the specification include a set of parameters to define timing relationships between transactions as well as timing relationships within individual transactions. Even though the traffic profile represents the behavior of a single agent it could be applied either in a concurrent manner (e.g. write and read traffic profiles running in parallel) or in a sequential manner (e.g. when one traffic completes before the next one start). Moreover, when simulating a reasonably complex system, it is possible to coordinate traffic profiles generated by multiple components. While providing abstract definition of traffic profiles, the AMBA ATP specification focuses on the use of traffic profiles with an AMBA AXI interface, outlining signaling, timing relationships between different transaction phases and between different transactions. The same application principles could be used to map the abstract traffic profiles to other AMBA protocols such as AMBA5 CHI protocol.  

To facilitate adoption of the AMBA Adaptive Traffic Profiles, Cadence has recently announced availability of SystemVerilog UVM ATP Sequence Layer which automatically implements mapping of an abstract ATP traffic to AMBA protocol specific traffic, generated by Cadence AMBA Verification IP. The ATP layer is implemented as a SystemVerilog UVM virtual sequence with the sequence item including all ATP transaction parameters as defined in the specification.

Using the provided sequence infrastructure, users can write tests to define and coordinate traffic profiles for various components in the system. The ATP Layer automatically converts the abstract traffic profile into AMBA protocol-specific traffic, e.g., AMBA5 CHI protocol traffic.

 A sample code below, shows an example of a read profile translated by Cadence ACE Verification IP in ACE protocol traffic.

   `uvm_do_with(ace_atp_vseq,                                            

                       {ace_atp_vseq.agentId == agent_id;                                // ATP agent id

                        ace_atp_vseq.atpDirection == ATP_READ;                    // direction of bursts issued by virtual sequence

                        ace_atp_vseq.startAddress == start_address;                // start of address range being accessed

                        ace_atp_vseq.endAddress == end_address;                  // end of address range being accessed

                        ace_atp_vseq.atpDomain == atp_domain;                      // domain to use for transactions

                        ace_atp_vseq.addressPattern == ATP_SEQUENTIAL;  // address pattern

                        ace_atp_vseq.transactionSize == 64;                             // number of bytes in each burst

                        ace_atp_vseq.dataSize == 4;                                          // number of bytes in each transfer

                        ace_atp_vseq.rate == 150.0/(50.0);                                // requestedBandwidth / clkFrequency

                        ace_atp_vseq.start == ATP_EMPTY;                              // start condition of the ATP FIFO

                        ace_atp_vseq.full == 128;                                               // full level of the ATP FIFO

                        ace_atp_vseq.numOfTransactions == 500;                    // number of bursts issued by this sequence

                        ace_atp_vseq.ARTV == 2;                                              // sub-transaction delay

                        ace_atp_vseq.RBR == 3;                                                // sub-transaction delay

                       });

In addition to the ATP Layer for Cadence Simulation-Based AMBA Verification IP, Cadence supports the ATP functionality in Acceleration-Based AMBA Verification IP. For detailed information about ATP support in Cadence Simulation-Based and Acceleration-Based Verification IP, visit ip.cadence.com.




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7 Habits of Highly Successful S-Parameters: How to Simulate Those Pesky S-Parameters in a Time Domain Simulator

Hello Spectre Users, Simulating S-parameters in a time domain (transient, periodic steady state) simulator has been and continues to be a challenge for many analog and RF designers. I'm often asked: What is required in order to achieve accurate...(read more)




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Link to: 7 Habits of Highly Successful S-Parameters: How to Simulate Those Pesky S-Parameters in a Time Domain Simulator

Hi All, If you were unable to attend IMS 2017 in June 2017, the IMS MicroApp “7 Habits of Highly Successful S-Parameters” is on our Cadence website. On Cadence Online Support , the in-depth AppNote is here: 20466646 . Best regards, Tawna...(read more)




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Triple Beat Analysis: What, Why & How?

The Triple Beat analysis is similar to Rapid IP2/IP3 analysis except that it uses three tones instead of two. It is used in cases where two closely-spaced small-signal inputs from a transmitter leak in to the receiver along with an intended small-signal RF input signal. (read more)




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Celebrating Five Years of Performance-Optimized Arm-Based SoCs: Now including AMBA5

It’s been quite a long 5-year journey building and deploying Performance Analysis, Verification, and Debug capabilities for Arm-based SoCs. We worked with some of the smartest engineers on the planet. First with the engineers at Arm, with whom we...(read more)




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BoardSurfers: Allegro In-Design Impedance Analysis: Screen your Routed Design Quickly

Have you ever manufactured a printed circuit board (PCB) without analyzing all the routed signal traces? Most designers will say “yes, all the time.” Trace widths and spacing are set by constraints,...

[[ Click on the title to access the full blog on the Cadence Community site. ]]




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IC Packagers: Shape Connectivity in the Allegro Data Model

Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain...

[[ Click on the title to access the full blog on the Cadence Community site. ]]




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Library Characterization Tidbits: Recharacterize What Matters - Save Time!

Recently, I read an article about how failure is the stepping stone to success in life. It instantly struck a chord and a thought came zinging from nowhere about what happens to the failed arcs of a...

[[ Click on the title to access the full blog on the Cadence Community site. ]]




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Start Your Engines: AMSD Flex – Your Instant Access to Latest Spectre Features!

Cadence ® Spectre ® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines, and drive from a variety of platforms enables you to "rev...

[[ Click on the title to access the full blog on the Cadence Community site. ]]




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Wally Rhines: Predicting Semiconductor Business Trends After Moore's Law

I recently attended a webinar presented by Wally Rhines about his new book, Predicting Semiconductor Business Trends After Moore's Law . Wally was the CEO of Mentor, as you probably know. Now he...

[[ Click on the title to access the full blog on the Cadence Community site. ]]




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IC Packagers: Advanced In-Design Symbol Editing

We have talked about aspects of the in-design symbol edit application mode in the past. This is the environment specific to the Allegro® Package Designer Plus layout tools allowing you to work...

[[ Click on the title to access the full blog on the Cadence Community site. ]]




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BoardSurfers: Training Insights: Placing Parts Manually Using Design for Assembly (DFA) Rules

If I talk about my life, it was much simpler when I used to live with my parents. They took good care of whatever I wanted - in fact, they still do. But now, I am living alone, and sometimes I buy...

[[ Click on the title to access the full blog on the Cadence Community site. ]]




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BoardSurfers: Bending the Flex Boards

When you design a rigid-flex board, the focus is, of course, on the bend. Your design might be bend to install (stable flexion) - it will be bent only a few times while installing. Or it might be dynamic - it will be bent regularly. It's important to...(read more)



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BoardSurfers: Training Insights: Creating Custom Reports using ‘Extract’

You must deal with many reports in your daily life – for your health, financial accounts, credit, your child’s academic records, and the count goes on. Ever noticed that these reports contain many details, most of which you don’t wa...(read more)



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BoardSurfers: Creating Footprints Using Templates in Library Creator

With ECAD-MCAD Library Creator, you can easily create footprints for your parts using thousands of ready-to-use templates that are provided with the tool.(read more)




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BoardSurfers: Footprints for Silicon - Two Steps to Creating PCB Footprints

Longfellow's metaphorical footprints on the sands of time is more profound and eternal no doubt but a footprint for silicon (a form of sand isn't it?) is as important for PCB designers. So, here we will list the steps to create a fo...(read more)



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BoardSurfers: Allegro In-Design IR Drop Analysis: Essential for Optimal Power Delivery Design

All PCB designers know the importance of proper power delivery for successful board design. Integrated circuits need the power to turn on, and ICs with marginal power delivery will not operate reliably. Since power planes can...(read more)




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BoardSurfers: Training Insights: Loading SKILL Programs Automatically

Imagine you are on a vacation with your family, and suddenly, your phone starts buzzing. You pick it up and what are you looking at is a bunch of pending, unanswered e-mails. You start recollecting the checklist you had made before taking off only to realize that you haven’t put on the automatic replies! (read more)




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BoardSurfers: Five Easy Steps to Create Footprints Using Packages in Library Creator

In my previous blog, I talked about creating a footprint using an existing template in Allegro ECAD-MCAD Library Creator and explained how easily you can access an existing template and create a package from it by just clicking a button. In this blog...(read more)




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BoardSurfers: Training Insights - Fundamentals of PDN for Design and PCB Layout

What is a Power Distribution Network (PDN) after all but resistance, inductance, and capacitance in the PCB and components? And, of course, it is there to deliver the right current and voltage to each component on your PCB. But is that all? Are there oth...(read more)




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BoardSurfers: Allegro In-Design Impedance Analysis: Screen your Routed Design Quickly

Have you ever manufactured a printed circuit board (PCB) without analyzing all the routed signal traces? Most designers will say “yes, all the time.” Trace widths and spacing are set by constraints, and many designers simply don’t h...(read more)




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BoardSurfers: Training Insights: Placing Parts Manually Using Design for Assembly (DFA) Rules

So, what if you can figure out all that can go wrong when your product is being assembled early on? Not guess but know and correct at an early stage – not wait for the fabricator or manufacturer to send you a long report of what needs to change. That’s why Design for Assembly (DFA) rules(read more)



  • Allegro PCB Editor

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IC Packagers: Five Steps to IC-Driven Package Design

They say Moore's law is slowing. It may be slowing but it is still running - it has not stopped! And, it has been running at full throttle for quite a few decades now.  The net result of this run? Well, you can't design ICs in isolation from the...(read more)



  • Allegro Package Designer

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IC Packagers: The Different Types of Mirrors

I’m not talking about carnival funhouse mirrors, but rather the different options for mirroring symbols, vias, and bond fingers in your IC Package layout. The Allegro Package Designer Plus and SiP Layout tools have two distinct styles of m...(read more)



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IC Packagers: Design Element Label Management

  A few weeks ago, we talked about template text labels for design-specific information. There, we were focused on labels that are specific to the design as a whole: revision information, dates, authors, etc. Today, we’re looking at a diff...(read more)



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IC Packagers: Identify Your Components

We’ve all seen bar codes and the more modern QR codes. They’re everywhere you go – items at the grocery store, advertisements and posters, even on websites. Did you know that, with the productivity toolbox in Allegro Package Designe...(read more)



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IC Packagers: Don’t Get Stranded on Islands, Delete Them!

No, this isn’t a Hollywood movie. We’re talking about pieces of plane shapes with no connections to them, not an idyllic private oasis in the Caribbean (sorry). Removing shape islands is something you’ve always been able to do in th...(read more)



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IC Packagers: A New Option in Bond Finger Solder Mask Openings

If you design wire bond packages, you’re familiar with the need for the bond fingers and rings on the package substrate layers to be exposed through the solder mask layer. If they aren’t, it becomes… rather difficult… to bon...(read more)



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IC Packagers: Time-Saving Alternatives to Show Element

In the Allegro back-end layout products like Allegro Package Designer Plus, it would be reasonable to assume that the most often used command is none other than “show element” (shortcut key F4). This command, runnable at nearly any t...(read more)



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  • Allegro PCB Editor

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IC Packagers: You Can Leave Your (Molding) Cap On…

Molding caps aren’t something we talk about too frequently around here. We all know they exist, and they serve an important purpose of protecting the delicate die from potentially harsh environmental conditions. They impact how well heat can be...(read more)



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IC Packagers: Shape Connectivity in the Allegro Data Model

Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain (any-angle routing, filled planes, and a multitude of pad ...(read more)



  • Allegro Package Designer
  • Allegro PCB Editor

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IC Packagers: Advanced In-Design Symbol Editing

We have talked about aspects of the in-design symbol edit application mode in the past. This is the environment specific to the Allegro Package Designer layout tools allowing you to work on symbol definitions directly in the context of your layout de...(read more)



  • Allegro Package Designer

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Library Characterization Tidbits: Over the Clouds and Beyond with Arm-Based Graviton and Cadence Liberate Trio

Cadence Liberate Trio Characterization Suite, ARM-based Graviton Processors, and Amazon Web Services (AWS) Cloud have joined forces to cater to the High-Performance Computing, Machine Learning/Artificial Intelligence, and Big Data Analytics sectors. (read more)




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Library Characterization Tidbits: Exploring Intuitive Means to Characterize Large Mixed-Signal Blocks

Let’s review a key characteristic feature of Cadence Liberate AMS Mixed-Signal Characterization that offers to you ease of use along with many other benefits like automation of standard Liberty model creation and improvement of up to 20X throughput.(read more)






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Library Characterization Tidbits: Recharacterize What Matters - Save Time!

Read how the Cadence Liberate Characterization solution effectively enables you to characterize only the failed or new arcs of a standard cell.(read more)




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Start Your Engines: AMSD Flex—Take your Pick!

Introduction to AMSD Flex mode and its benefits.(read more)



  • mixed signal design
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Start Your Engines: AMSD Flex – Your Instant Access to Latest Spectre Features!

This blog talks about how to enable the AMS Designer flex mode.(read more)



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#Coronavirus: যুদ্ধে লড়াইতে মুক্ত হস্তে দান তারকা ক্রীড়াবিদদের, সানিয়া মির্জা দিলেন‘এত’ কোটি




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#Coronavirus: মারণ ভাইরাসের প্রকোপ, শেষ হয়ে গেল একাধিক তারকা ক্রিকেটারের কেরিয়ার




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#BigNews: কেকেআরের পর নতুন ক্রিকেট দল কিনবেন শাহরুখ খান!




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CoronaVirus: મુંબઇમાં પ્લાઝમા થેરેપી બાદ દર્દીનું મોત

CoronaVirus: મુંબઇમાં પ્લાઝમા થેરેપી બાદ દર્દીનું મોત




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Coronavirus: মাস্ক পরবেন, নাকি পরবেন না? কী বলছে হু? কী বলছেন বিশেষজ্ঞদের একাংশ?




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BAPS: ભગવાન કોઈ ભક્તની જાતિ, વરણ કે રૂપથી નથી બંધાતા, ભગવાન તો ભક્તિને વશ થાય

ભગવાનઅને સંત આપણને સંસારમાંથી છોડાવવા માટે જે પ્રયત્ન કરે તે આપણને દુઃખ જેવું લાગે, તોપણ તે તેઓનું આપણા પરનું હેત છે.




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BAPS: માનવી સગવડની સવલતમાં પણ આજે આટલા દુઃખી કેમ? શું ખૂટે છે

ગરમીમાં પંખો કે A.C. બંધ થઈ જાય તો પણ આપણે અકળાઈ ઊઠીએ છીએ. આ આપણી વાસ્તવિકતા છે.




s:

BAPS: ઈમારત ટકાવવામાં મહત્ત્વનો ભાગ પાયો છે, તેમ સંસ્કૃતિને ટકાવવા મહત્ત્વનો ભાગ મંદિર છે

મંદિર સંસ્કૃતિનું તો રક્ષણ કરે જ છે, સાથે સાથે માનવજાતને જીવનમાં આવતા વિઘ્નોના વાવાઝોડા સામે ટકી રહેવાનું બળ પણ આપે છે. મંદિર દેશની તેમજ સમાજની એકતાનું પણ મૂળ કારણ છે




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BAPS: મનુષ્યનો ઘાતકશત્રુ એટલે ક્રોધ - 'થોડોક ક્રોધ ઊપજે તે પણ અતિશય દુઃખદાયી'

રાલ્ફ વાલ્ડો ઈમર્સન લખે છે કે ‘જેટલી મિનિટ તમે ગુસ્સે રહો છો તેટલી પ્રત્યેક મિનિટમાં તમે સુખની આઠ સેકંડ ખોઈ નાખો છો.’




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Astro tips: રોજની આટલી આદતો બદલશો તો ગ્રહોનું મળશે સારું પરિણામ

જ્યોતિષના જણાવ્યા પ્રમાણે આ પ્રકારની આદતો જીવનમાં સમસ્યાઓ ઊભી કરે છે. આવી સ્થિતિમાં જરૂરી છે કે આપણે રોજિંદી જીંદગીમાં આદતોમાં સુધારો કરવાથી ગ્રહો પણ સારા થશે અને શુભ પરિણામ પણ આપવાનું શરુ કરશે.