According to the book Electronic Design Automation For Integrated Circuits Handbook there are mutiple algorithms available. Quote from book: "One of the first complete ATPG algorithms is the D-algorithm [9]. Subsequently, other algorithms were proposed, including PODEM [14], FAN [15], and SOCRATES [10]."

I was wondering which algorithms are used in Cadence Modus.

Hello Everyone,

I was finishing the layout via Innovus and ran verifyConnectivity followed by checkRoute.

verifyConnectivity was okay and it showed no errors and no warnings, whereas checkRoute showed there are 3 unrouted nets.

When i ran the checkRoute command again immediately, it showed no unrouted/unconnected nets.

Which of these commands should we trust or is this really unrouted nets issue?

Looking forward for a response, thanks in advance.

Regards,

Vijay

Hi,

There was tool available with INCISIV called imc to view the coverage reports.

The question is: How can we view the code coverage reports generated with XCELIUM? I think imc is not available with XCELIUM?

Thanks in advance.

Hello, i have a logic output from a D-flipflop which generates a reset signal with variable pulse width. I want to stretch this LOW pulse width with an extra 100ns added to the original pulse width digitally, is there any way to do that?

Dear all,

I am using Conformal Constraint Designer (Version 17.1) to analyse a SystemVerilog based design.

While performing default HDL checks it finds  some violations (issues) in RTL and complains (warnings, etc) about RTL checks and others.

My questions:

Is there any directive which I can add to RTL (system Verilog) so that particular line of code or signal is ignored or not checked for HDL or RTL checks.

I can set ignore rules in rule manager (gui) but it does not seems effective if code line number changes or new signals are introduced.

What is the best way to customize default_hdl_rules ?

I will be grateful for your guidance.

Thanks for your time.

hi all, 

          what wrong with the error "param_write.log does not exist" when i export parameters in allegro 16.6 pcb board.

          someone can provide suggestions, thanks.

best regards.

For a netlist vs. netlist LEC flow we have to solve the following problem:

- in the RTL code we replicate a large array of N x M all-identical hard-macros, let call them MACRO_A

- MACRO_A is pre-assembled in Innovus and contains digital parts and analog parts (bottom-up hierarchical flow)

- at top-level (full-chip) we instantiate this array of all-identical macros

- in the top-level place-and-route flow we perform ecoChangeCell to remaster the top row of this array with MACRO_B

- MACRO_B is just a copy of the original MACRO_A cell containing same pins position, same internal digital functionality and also same digital layout, only slight differences in one analog block inside the macro

- MACRO_A and MACRO_B have the same .lib file generated with the do_extract_model command at the end of the Innovus flow, they only differ in the name of the macro

- when performing post-synthesis netlist vs post-place-and-route we load .lib files of both macros in Conformal LEC

- the LEC flow fails because Conformal LEC sees only MACRO_A instantiated in the post-synthesis netlist and both MACRO_A and MACRO_B in the post-palce-and-route netlist

Since both digital functionality and STD cells layout are the same between MACRO_A and MACRO_B we don't want to keep track of this difference already at RTL stage, we just want to perform this ECO change in place-and-route and force Conformal to assume equivalence between MACRO_A and MACRO_B .

Basically what I'm searching for is something similar to the add_instance_equivalences Conformal command but that works between Golden and Revised designs on cell primitives/black-boxes .

Is this flow supported ?

Thanks in advance

Luca

The following is valid SystemVerilog:

module mmio
#(parameter PORTS=2,
parameter ADDR_WIDTH=30)
(input logic[ADDR_WIDTH-1:0] addr[PORTS],
output logic ben[PORTS], // Bus enable
output logic men[PORTS]); // Memory enable

always_comb begin
for(int i = 0; i < PORTS; i++) begin
ben[i] = addr[i] >= 'h20080004 && addr[i] < 'h200c0000;
men[i] = ~ben[i];
end
end

endmodule : mmio

And if you instantiate it:

mmio #(1, 30) MMIO(.addr('{scalar_addr}),
.ben('{ben}),
.men('{men}));

Genus returns an error: "Could not synthesize non-constant range values. [CDFG-231] [elaborate]" Is this just not possible in Genus or could it be caused by something else?

As title,

How to dump waveform, fsdb in SimVision? 
(Simulation Analysis Environment  SimVision(64) 18.09-s001)
Please help.

Thanks.

It's been a while since you've heard from me...it has been a busy year for sure. One of the reasons I've been so quiet is that I was part of a team working diligently on our latest best kept secret: The MMSIM 12.1.1/MMSIM 13.1 Documentation has...(read more)

Hi Folks, A question that I've often received from designers, "Is there a method to determine the amount of memory required before I submit a job? I use distributed processing and need to provide an estimate before submitting jobs." The answer...(read more)

Hi All, Here's another great new feature that I've found very helpful... Broadband SPICE is a new tool for S-parameter simulation in Spectre RF. In the MMSIM13.1.1 ( MMSIM13.1 USR1) release (now available on http://downloads.cadence.com), a...(read more)

Last year, I wrote a blog post entitled Modeling Oscillators with Arbitrary Phase Noise Profiles . We now have an easier way to do this. Starting in MMSIM 13.1 , you can specify the phase noise as an instance parameter in Spectre sources, including...(read more)

Hi Folks, Check out this great new video on YouTube: CDNLive SV 2014: PMC Improves Visibility and Performance with Spectre APS In this video from CDNLive Silicon Valley 2014, Jurgen Hissen, principal engineer, MSCAD, at PMC, discusses an aggressive...(read more)

Did you check out the new Pnoise and Hbnoise Choosing Analyses forms in the MMSIM 15.1 and IC6.1.7 /ICADV12.2 releases? These forms have been significantly improved and simplified. The Direct Plot Form has also been enhanced and is much easy to use....(read more)

Hello Spectre Users, Simulating S-parameters in a time domain (transient, periodic steady state) simulator has been and continues to be a challenge for many analog and RF designers. I'm often asked: What is required in order to achieve accurate...(read more)

Hi All, If you were unable to attend IMS 2017 in June 2017, the IMS MicroApp “7 Habits of Highly Successful S-Parameters” is on our Cadence website. On Cadence Online Support , the in-depth AppNote is here: 20466646 . Best regards, Tawna...(read more)

The other day, I happened to sneak out some time for myself after having sent the kids to play in the neighborhood park. I made myself a hot cup of coffee and settled on the couch hoping to enjoy the silence in the house. But was it really ...(read more)

Hi,

I am trying to write a skill code where it takes form inputs by default and just displays tree directly.

i have written below code,

procedure( create_tree()
let(()

leHiTree()
leTreeForm->treeOption->value="Current to user level"
leTreeForm->userLevel->value= 31
ipcSleep(1)
hiFormDone(leTreeForm)

))

the form takes in values but it is not closing.

tried with regtimer in place of ipc sleep, didn't work.

how to close form(should be same as pressing OK)? 

Thanks in advance,

vishwas 

Hi,

I want to convert ircx file(which is from TSMC,inclued EM Information) to ict or emDataFile for Voltus-fi.

I tried many way, but I can not make it. Can anyone give me some advice?

and I  do not installed QRC.

below is some tools installed my server. 

IC617-64b.500.21 is used.

Hello,

I have created an appForm with  the following attachmentList and size:

?attachmentList list(hicLeftPositionSet | hicRightPositionSet ; field 1
                     hicLeftPositionSet | hicRightPositionSet ; field 2
etc.

?initialSize    800:800
?minSize        800:800
?maxSize       1600:800

If I reduce the minimum y-size (?minSize        800:200), scrollbars are not inserted, unless I remove the attachmentList constraints.

Is it possible to have both scrollbars and "hicLeftPositionSet | hicRightPositionSet"? 

Thank you,

Best regards,

Aldo

I can get the bound stdcells using bndGetBoundObjects, but not get what each individual stdcell corresponds in layout.

Is there a way to get the layout bound stdcells of an array schematic symbol if the layout stdcell name do or do not match the symbol naming?

Once the schematic array stdcells are bound to the layout stdcells, how to get the correct terminal term~>name and net~>name?

Example of a schematic symbol and layout stdcell:

Schematic

INV<0:2>    instTerms~>terms~>name = ("vss" "vdd" "A" "Y")

                   instTerms~>net~>name = ("<*3>vss" "<*3>vdd" "in<0:2>" "nand2A,nand3B,nor2B")

Layout ( I know it is bad practice, but it happens )

stdcell1 instTerms~>terms~>name = ("vss" "vdd" "A" "Y")

             instTerms~>net~>name = ("vss" "vdd" "in<0>" "nand2A")

I23        instTerms~>terms~>name = ("vss" "vdd" "A" "Y")

             instTerms~>net~>name = ("vss" "vdd" "in<1>" "nand3B")

INV(2) instTerms~>terms~>name = ("vss" "vdd" "A" "Y")

             instTerms~>net~>name = ("vss" "vdd" "in<2>" "nor2B")

Paul

Hi,

I am running simulation in ADEXL and need a custom function for VIVA to apply same procedure to all signals saved in output. For instance, I have clock nets and I want to get all of them and look at the duty-cycle, edge rate etc.

It is a little more involved than about part since I have some regex and setof to filter before processing but if I can get all signals for current history, I can postprocess them later.

In ocean, I am just doing outputs() and getting all saved signals but I was able to do this in VIVA calculator due to the difficulties in getting current history, test name and opening result directory

thanks

yayla

Version Info:

ICADV12.3 64b 500.21

spectre -W =>

Tool 'cadenceMMSIM' Current project version '16.10.479'
sub-version  16.1.0.479.isr9

Hi all,

I want to write a script SKILL to create the title & frame for view schematic. My question is whether SKILL supports any function for me to do this.

Best regards,

Huy Hoang

Howdy,

            In the netlist generated after parasitic extraction, nodes have been added at fracture points to add parasitic devices. For example, in the image below, I'm referring to the nodes IN#1 and IN#2. Is there a way to determine their co-ordinates relative to the layout co-ordinate system? I could not find them in the Skill command reference and when I query the parasitic elements in the extracted view, it gives the graphical pin locations of the elements rather than the physical.

Thanks

Audi

It’s been quite a long 5-year journey building and deploying Performance Analysis, Verification, and Debug capabilities for Arm-based SoCs. We worked with some of the smartest engineers on the planet. First with the engineers at Arm, with whom we...(read more)

Here we conclude the blog series and highlight the results of Mediatek 's use of Cadence Perspec™ System Verifier for their SoC level verification. In case you missed it, Part 1 of the blog is here , and Part 2 of the blog is here . One of their key...(read more)

It’s now official: Perspec System Verifier is rated the #1 product in the #1 category of Portable Stimulus, according to the 2017 EDA User Survey published on Deepchip.com. There were 33 user responses in favor of Perspec as the #1 tool, and dr...(read more)

It’s always good to hear what real users think of products. Here is a very detailed review (~4000 words) by an Anonymous user, nick named Ant-Man (from the movie). Overall it’s a very strong endorsement of Perspec, and summarize...(read more)

The Cadence® Connections® Verification Program brings together a worldwide network of services, training, and IP development experts that support Cadence verification solutions. The program members help customer accelerate the adoption of new...(read more)

The Accellera Portable Stimulus Working Group met at the DVCon 2018 to move the process forward towards ratification. While we can't predict exactly when it will be ratified, the goal is now more clearly in sight! Cadence booth was busy with a lo...(read more)

CDNLive is a user conference, and verification is one of the largest categories of content with multiple tracks covering multiple days. Portable stimulus is one of the hottest new areas in verification, and continues to be popular in all venues. At l...(read more)

Cadence pulled a fast one at DAC 2018, almost like a bait and switch. We advertised a hands-on workshop to learn about Accellera Portable Stimulus Specification (PSS) v1.0. But we made participants compete head to head, for prizes, and their pride! T...(read more)

Cadence continues to be a leader in SoC verification and has expanded our industry investment in Accellera portable stimulus language standardization. Some customers have expressed reservations that portable stimulus requires the effort of learn...(read more)

Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...(read more)

https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/cowos-info

I came across cadence old article that discussing about TSMC advance packaging technology such as InFO & CoWoS. However, I couldn’t find information such as what I/O interface standard is required to realize this multi-chip SiP. For example, Intel using their proprietary AIB interface for EMIB solution.

Besides, any idea if inFO also able to supports multi-chip integration for older node process to new node process such as 40-nm to 16-nm?

Hi all,

I have a question regarding the manufacture : how to check a cluster of same net vias spacing, with have no shape or cline covered

Did you know that there is a park in San Jose named after a disk drive? Actually, technically it is named after the first computer that used disk drives. You couldn't just go and buy a disk drive...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

The Linley Processor Conference always opens with a keynote by Linley Gwenapp giving an overview of processors in whatever is the hottest area. Most of the other presentations during the conference...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

The 2019 HF1 production release for Clarity, Celsius, and Sigrity Tools is now available for download at Cadence Downloads . SIGRITY2019 HF1 For information about supported platforms, compatibility...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

www.youtube.com/watch Made on my balcony (camera Carey Guo) Monday: EDA101 Video Tuesday: Weekend Update Wednesday: RAMAC Park and the Origin of the Disk Drive Thursday: 1G Mobile: AMPS, TOPS, C-450,...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

I recently attended a webinar presented by Wally Rhines about his new book, Predicting Semiconductor Business Trends After Moore's Law . Wally was the CEO of Mentor, as you probably know. Now he...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

Cadence has a new white paper out on Computational Software . I've written on these topics in Breakfast Bytes, most recently in the posts: Computational Software System Analysis: Computational...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

If I talk about my life, it was much simpler when I used to live with my parents. They took good care of whatever I wanted - in fact, they still do. But now, I am living alone, and sometimes I buy...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

Everyone keeps talking about “the cloud” this and “the cloud” that these days—but you’re a semiconductor designer. Everyone keeps saying “the cloud” is revolutionizing all aspects of electronics design—but what does it mean for you? Cadence's own Tom Hackett discussed this in a presentation at the Cadence Theater during DAC 2019.

What people refer to as “the cloud” is commonly divided into three categories: Infrastructure as a Service (IaaS), Platform as a Service (PaaS), and software as a Service (SaaS). With IaaS, you bring your own software—i.e. loading your owned or appropriately licensed tools onto cloud hardware that you rent by the minute. This service is available from providers like Google Cloud Platform, Amazon Web Service, and Microsoft Azure. In PaaS (also available from the major cloud providers), you create your own offering using capabilities and a software design environment provided by the cloud vendor that makes subsequent scaling and distribution really easy because the service was “born in the cloud”.  Lastly, there’s SaaS, where the cloud is used to access and manage functionality and data without requiring users to set up or manage any of the underlying infrastructure used to provide it.  SaaS companies like Workday and Salesforce deliver their value in this manner.  The Cadence Cloud portfolio makes use of both IaaS and SaaS, depending on the customers’ interest.  Cadence doesn’t have PaaS offerings because our customers don’t create their own EDA software from building blocks that Cadence provides.

All of these designations are great, but you’re a semiconductor designer. Presumably you use Workday or some similar software, or have in the past when you were an intern, but what about all of your tools? Those aren’t on the cloud.

Wait—actually, they are.

Using EDA tools in the cloud allows you to address complexity and data explosion issues you would have to simply struggle through before. Since you don’t have to worry about having the compute-power on-site, you can use way more power than you could before. You may be wary about this new generation of cloud-based tools, but don’t worry: the old rules of cloud computing no longer apply. Cloud capacity is far larger than it used to be, and it’s more secure. Updates to scheduling software means that resource competition isn’t as big of a deal anymore. Clouds today have nearly unlimited capacity—they’re so large that you don’t ever need to worry about running out of space.

The vast increase in raw compute available to designers through the cloud makes something like automotive functional safety verification, previously an extremely long verification task, doable in a reasonable time frame. With the cloud, it’s easy to scale the amount of compute you’re using to fit your task—whether it’s an automotive functional safety-related design or a small one.

Nowadays, the Cadence Cloud Portfolio brings you the best and brightest in cloud technology. No matter what your use case is, the Cadence Cloud Portfolio has a solution that works for you. You can even access the Palladium Cloud, allowing you to try out the benefits of an accelerator without having to buy one.

Cloud computing is the future of EDA. See the future here.

Autonomous vehicles are coming. In a statistic from the U.S. Department of Transportation, about 37,000 people died in car accidents in the United States in 2018. Having safe, fully automatic vehicles could drastically reduce that number—but the trick is figuring out how to make an autonomous vehicle safe. Internet-enabled systems in cars are more common than ever, and it’s unlikely that the use of them will slow or stop—and while they provide many conveniences to a driver, they also represent another attack surface that a potential criminal could use to disable a vehicle while driving.

So—what’s being done to combat this? Green Hills Software is on the case, and they explained the landscape of security in automotive systems in a presentation given by Max Hinson in the Cadence Theater at DAC 2019. They have software embedded [FS1] in most parts of a car, and all the major OEMs use their tech. The challenge they’ve taken on is far from a simple one—between the sheer complexity of modern automotive computer systems, safety requirements like the ISO 26262 standard, and the cost to develop and deploy software, they’ve got their work cut out for them. It’s the complexity of the systems that represents the biggest challenge, though. The autonomous cars of the future have dynamic behaviors, cognitive networks, require security certification to at least ASIL-D, require cyber security like you’d have on an important regular computer system to cover for the internet-enabled systems—and all of this comes with a caveat: under current verification abilities, it’s not possible to test every test case for the autonomous system. You’d be looking at trillions of test cases to reach full coverage—not even the strongest emulation units can cover that today.

With regular cars, you could do testing with crash-test dummies, and ramming the car into walls at high speeds in a lab and studying the results. Today, though, that won’t cut it. Testing like that doesn’t see if a car has side-channel vulnerabilities in its infotainment system, or if it can tell the difference between a stop sign and a yield sign. While driving might seem simple enough to those of us that have been doing it for a long time, to a computer, the sheer number of variables is astounding. A regular person can easily filter what’s important and what’s not, but a machine learning system would have to learn all of that from scratch. Green Hills Software posits that it would take nine billion miles of driving for a machine learning system of today’s caliber to reach an average driver’s level—and for an autonomous car, “average” isn’t good enough. It has to be perfect.

A certifier for autonomous vehicles has a herculean task, then. And if that doesn’t sound hard enough, consider this: in modern machine-vision systems, something called the “single pixel hack” can be exploited to mess them up. Let’s say you have a stop sign, and a system designed to recognize that object as a stop sign. Randomly, you change one pixel of the image to a different color, and then check to see if the system still recognizes the stop sign. To a human, who knows that a stop sign is octagonal, red, and has “STOP” written in white block letters, a stop sign that’s half blue and maybe bent a bit out of shape is still, obviously, a stop sign—plus, we can use context clues to ascertain that sign at an intersection where there’s a white line on the pavement in front of our vehicle probably means we should stop. We can do this because we can process the factors that identify a stop sign “softly”—it’s okay if it’s not quite right; we know what it’s supposed to be. Having a computer do the same is much more difficult. What if the stop sign has graffiti on it? Will the system still recognize it as a stop sign? How big of an aberration needs to be present before the system no longer acknowledges the mostly-red, mostly-octagonal object that might at one point have had “stop” written on it as a stop sign? To us, a stop sign is a stop sign, even with one pixel changed—but change it in the right spot, and the computer might disagree.

The National Institute of Security and Technology tracks vulnerabilities along those lines in all sorts of systems; by their database, a major vulnerability is found in Linux every three days. And despite all our efforts to promote security, this isn’t a battle we’re winning right now—the number of vulnerabilities is increasing all the time.

Check back next time to see the other side: what does Green Hills Software propose we do about these problems? Read part 2 now.

If you missed the first part of this series, you can find it here.

So: what does Green Hills Software propose we do?

The issue of “solving security” is, at its core, impossible—security can never be 100% assured. What we can do is make it as difficult as possible for security holes to develop. This can be done in a couple ways; one is to make small code in small packs executed by a “safing plan”—having each individual component be easier to verify goes a long way toward ensuring the security of the system. Don’t have sensors connect directly to objects—instead have them output to the safing plan first, which can establish control and ensure that nothing can be used incorrectly or in unintended ways. Make sure individual software components are sufficiently isolated to minimize the chances of a side-channel attack being viable.

What all of these practices mean, however, is that a system needs to be architected with security in mind from the very beginning. Managers need to emphasize and reward secure development right from the planning stages, or the comprehensive approach required to ensure that a system is as secure as it can be won’t come together. When something in someone else’s software breaks, pay attention—mistakes are costly, but only one person has to make it before others can learn from it and ensure it doesn’t happen again. Experts are experts for a reason—when an independent expert tells you something in your design is not secure, don’t brush them off because the fix is expensive. This is what Green Hills Software does, and it’s how they ensure that their software is secure.

Now, where does Cadence fit into all of this? Cadence has a number of certified secure offerings a user can take advantage of when planning their new designs. The Tensilica portfolio of IP is a great way to ensure basic components of your design are foolproof. As always, the Cadence Verification Suite is great for security verification in both simulation and emulation, and JasperGold platform’s formal apps are a part of that suite as well.

We are entering a new age of autonomous technology, and with that new age we have to update our security measures to match. It’s not good enough to “patch up” security at the end—security needs to beat the forefront of a verification engineer or hardware designer’s mind at all stages of development. For a lot of applications, quite literally, lives are at stake. It’s uncharted territory out there, but with Green Hills Software and Cadence’s tools and secure IP, we can ensure the safety of tomorrow.

We're happy to have guest blogger Thorsten Dworzak, Principal Consultant at Verilab GmbH, describe how he added Specman/e syntax to Sublime Text 3:

According to the 2018 StackOverflow Developer Survey, the popularity of development environments (IDEs, Text Editors) among software developers shows the following ranking:

1. Visual Studio Code 34.9%
2. Visual Studio 34.3%
3. Notepad++ 34.2%
4. Sublime Text 28.9%
5. Vim 25.8%
6. IntelliJ 24.9%
7. Android Studio 19.3%
8. (DVT) Eclipse 18.9%
9. …

15. Emacs 4.1%

Of these, only Vim, (DVT) Eclipse, and Emacs support editing in e-language (at least, last time I checked). Kate, which comes with KDE and also has a Specman mode, is not on this list.

I started using Sublime Text 3 some time ago. It offers packages that support a number of programming languages.

Though there is an e-language syntax available from Tsvi Mostovicz, it is unfinished work, and there are many syntactic constructs are missing. So, I created a fork of his project and finished it (it will eventually be merged back here).

It is a never-ending task because my code base for testing is limited and e is still undergoing development. The project is available through ST3's Package Control and you can contribute to it via Github.

I am eagerly waiting for your pull requests and/or comments and contributions!

Curious about what’s going on behind the scenes with verification? Bernard Murphy, Jim Hogan, and our own Paul Cunningham are on the case with the “Innovation in Verification” blog stream over at semiwiki.com. Every month, this trio reviews a newly-published paper in academia that pertains to verification and discusses its implications. Be sure to stop by—it’s a great place to see what might be coming down the pipeline someday.

This month, they discuss the implications of metamorphic testing. The purpose of metamorphic testing is to define a verification approach where is there is no “golden reference.” This situation comes up a lot now as designs grow in complexity, and it begs the question: “how does one know the design is verified if there is no standard to compare to?”. Metamorphic testing addresses the problem of not having a “gold standard” to compare to by comparing the results of related tests instead. The paper reviewed by this team used metamorphic testing to study methods of managing JavaScript tags.

Paul saw this as a valuable new class of coverage. Metamorphic testing represents a way to create better distribution analyses through understanding the relationships among tests. This can reveal critical-but-complex issues that traditional verification methods may overlook. He saw this as an emerging class of coverage that new verification tools could be built around. Paul asserted that a future metamorphic-testing-based tool’s main contribution to the field of verification would be to better analyze noisy performance results where the noise is multi-modal. It could be useful in detecting race conditions and similar hard-to-debug anomalies. Paul also sees metamorphic testing as ripe for ML techniques. Overall—Paul sees a bright future for metamorphic testing in verification.

Jim is reminded of Solido and Spice—these metamorphic testing capabilities are “more than just a feature”—they might be a product. Maybe even a whole new class of verification tools, as Paul said.

Bernard says that this topic is “too rich to address in one blog”, so be sure to head over to the post to see more of what the future has in store for verification.

You must deal with many reports in your daily life – for your health, financial accounts, credit, your child’s academic records, and the count goes on. Ever noticed that these reports contain many details, most of which you don’t wa...(read more)