The most important part of the men's golf season is traditionally held in the spring when post-season competition can lead to a national championship.  Before the team entered the spring, Head Golf Coach Gary Tanner recognized four players for their past performance at a recent home volleyball match.

Lawrence, Kansas – The Haskell men's golf team finished eighth at the Ottawa Invitational held at Eagle Bend Golf Course on Tuesday evening. The Indians finished with a two round score of 678. 

Lawrence, Kansas – The Haskell men's golf team finished 8th out of 9 teams at the Ottawa Spring Invitational held at Eagle Bend Golf Course on Monday. The Indians finished with a round score of 344 and the second round was cancelled due to snow on the course. 

Maryville, MO – The Haskell Men's golf team competed in the Graceland Invitational which was cut short due to inclement weather conditions on the second day. 

Haskell Golf team would have finished out their season at the PGA Minority National Championship Tournament in Port St. Lucie, Florida this weekend. The team was informed that they had two players fall below hour's just days before leaving towards Florida.

Lawrence, Kansas – The Haskell men's golf team finished 8th out of 11 teams in the Ottawa Invitational held at Eagle Bend Golf Course in Lawrence, Kansas on Monday and Tuesday. The Indians finished with a round score of 321, 331, with a total team score 652.

The collegiate races for the Haskell Invitational have been rescheduled for October 11 at 4pm.

Tomorrow, September 6, 2019, Haskell XC will compete in Bearcat open against Northwest MIssouri State!

Both Women's and Men's Cross Country improved their overall standings this weekend at the bearcat Open.

This week Cross Country is training for their first home meet on Saturday October 12, 2019 at 9:15 & 10:00 am during Homcoming Weekend!

Haskell Men's Cross CountryTop 20 finishers from Haskell's Invitational. From left to right Dorian Daw, Ronson Begay, Uriah Little Owl & Joshua Garcia (not pictured Tristan Antonio).

Women's Cross Country Pictured, Chantel Yazzie crossing the finish line as Haskell's first Women's Cross Country runner to cross at the Haskell Invitational. 

1 Dominican Peso = 425.1513 Vietnamese Dong

1 Dominican Peso = 0.1815 Venezuelan Bolivar Fuerte

1 Dominican Peso = 0.4876 Ukrainian Hryvnia

1 Dominican Peso = 0.159 Salvadoran Colon

1 Dominican Peso = 0.4034 Slovak Koruna

1 Dominican Peso = 0.0618 Peruvian Nuevo Sol

1 Dominican Peso = 0.2817 Maldivian Rufiyaa

1 Dominican Peso = 0.324 Moldovan Leu

1 Dominican Peso = 0.011 Latvian Lat

1 Dominican Peso = 0.1253 Bolivian Boliviano

1 Dominican Peso = 0.0328 Bulgarian Lev

Ottawa, Kansas - The Haskell Indian Nations University Men's track and field teams competed at the Ottawa Braves Invitational on Saturday.

1 Papua New Guinean Kina = 6821.5475 Vietnamese Dong

1 Papua New Guinean Kina = 2.9115 Venezuelan Bolivar Fuerte

1 Papua New Guinean Kina = 7.8237 Ukrainian Hryvnia

1 Papua New Guinean Kina = 2.5512 Salvadoran Colon

1 Papua New Guinean Kina = 6.4733 Slovak Koruna

1 Papua New Guinean Kina = 0.9909 Peruvian Nuevo Sol

1 Papua New Guinean Kina = 4.5195 Maldivian Rufiyaa

1 Papua New Guinean Kina = 5.198 Moldovan Leu

1 Papua New Guinean Kina = 0.1763 Latvian Lat

1 Papua New Guinean Kina = 2.0102 Bolivian Boliviano

1 Papua New Guinean Kina = 0.5263 Bulgarian Lev

1 Brunei Dollar = 16557.8167 Vietnamese Dong

1 Brunei Dollar = 7.067 Venezuelan Bolivar Fuerte

1 Brunei Dollar = 18.9903 Ukrainian Hryvnia

1 Brunei Dollar = 6.1925 Salvadoran Colon

1 Brunei Dollar = 15.7126 Slovak Koruna

1 Brunei Dollar = 2.4051 Peruvian Nuevo Sol

1 Brunei Dollar = 10.9702 Maldivian Rufiyaa

1 Brunei Dollar = 12.6171 Moldovan Leu

1 Brunei Dollar = 0.428 Latvian Lat

1 Brunei Dollar = 4.8793 Bolivian Boliviano

1 Brunei Dollar = 1.2775 Bulgarian Lev

Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components and calculation power to accommodate new performance-hungry applications such as machine learning and autonomous driving.  With increased number of SoC components, such as CPUs, GPUs, accelerators and I/O devices, comes increased demand to correctly model interoperability of various components. Traditional simulation of complex systems requires accurate models of all components comprising the system and normally results in very long simulation times. A better way is to create a set of typical traffic profiles which describe behavior of system’s masters and slaves. Such profiles should be abstract to be applied to various protocols and interfaces and be portable to be applied throughout different SoC design and verification cycles.

To address the challenges outlined above, Arm has recently announced availability of the AMBA® Adaptive Traffic Profiles (AMBA ATP) specification which lays foundation of a new synthetic traffic framework. The AMBA ATP specification includes detailed information of various transaction types and timing characteristics of those transactions. The traffic profiles defined in the specification are abstract in nature and thus could be used to generate stimuli for various standard AMBA protocols and in various environments such as RTL-based simulation, FPGA prototyping and final SoC verification. The traffic profiles outlined in the specification include a set of parameters to define timing relationships between transactions as well as timing relationships within individual transactions. Even though the traffic profile represents the behavior of a single agent it could be applied either in a concurrent manner (e.g. write and read traffic profiles running in parallel) or in a sequential manner (e.g. when one traffic completes before the next one start). Moreover, when simulating a reasonably complex system, it is possible to coordinate traffic profiles generated by multiple components. While providing abstract definition of traffic profiles, the AMBA ATP specification focuses on the use of traffic profiles with an AMBA AXI interface, outlining signaling, timing relationships between different transaction phases and between different transactions. The same application principles could be used to map the abstract traffic profiles to other AMBA protocols such as AMBA5 CHI protocol.  

To facilitate adoption of the AMBA Adaptive Traffic Profiles, Cadence has recently announced availability of SystemVerilog UVM ATP Sequence Layer which automatically implements mapping of an abstract ATP traffic to AMBA protocol specific traffic, generated by Cadence AMBA Verification IP. The ATP layer is implemented as a SystemVerilog UVM virtual sequence with the sequence item including all ATP transaction parameters as defined in the specification.

Using the provided sequence infrastructure, users can write tests to define and coordinate traffic profiles for various components in the system. The ATP Layer automatically converts the abstract traffic profile into AMBA protocol-specific traffic, e.g., AMBA5 CHI protocol traffic.

 A sample code below, shows an example of a read profile translated by Cadence ACE Verification IP in ACE protocol traffic.

   `uvm_do_with(ace_atp_vseq,                                            

                       {ace_atp_vseq.agentId == agent_id;                                // ATP agent id

                        ace_atp_vseq.atpDirection == ATP_READ;                    // direction of bursts issued by virtual sequence

                        ace_atp_vseq.startAddress == start_address;                // start of address range being accessed

                        ace_atp_vseq.endAddress == end_address;                  // end of address range being accessed

                        ace_atp_vseq.atpDomain == atp_domain;                      // domain to use for transactions

                        ace_atp_vseq.addressPattern == ATP_SEQUENTIAL;  // address pattern

                        ace_atp_vseq.transactionSize == 64;                             // number of bytes in each burst

                        ace_atp_vseq.dataSize == 4;                                          // number of bytes in each transfer

                        ace_atp_vseq.rate == 150.0/(50.0);                                // requestedBandwidth / clkFrequency

                        ace_atp_vseq.start == ATP_EMPTY;                              // start condition of the ATP FIFO

                        ace_atp_vseq.full == 128;                                               // full level of the ATP FIFO

                        ace_atp_vseq.numOfTransactions == 500;                    // number of bursts issued by this sequence

                        ace_atp_vseq.ARTV == 2;                                              // sub-transaction delay

                        ace_atp_vseq.RBR == 3;                                                // sub-transaction delay

                       });

In addition to the ATP Layer for Cadence Simulation-Based AMBA Verification IP, Cadence supports the ATP functionality in Acceleration-Based AMBA Verification IP. For detailed information about ATP support in Cadence Simulation-Based and Acceleration-Based Verification IP, visit ip.cadence.com.

With more and more SoCs employing sophisticated interconnect IP to link multiple processor cores, caches, memories, and dozens of other IP functions, the designs are enabling a new generation of low-power servers and high-performance mobile devices. The complexity of the interconnects and their advanced configurability contributes to already formidable design and verification challenges which lead to the following questions:

While your interconnect subsystem might have a correct functionality, are you starving your IP functions of the bandwidth they need? Are requests from latency-critical initiators processed on time? How can you ensure that all applications will receive the desired bandwidth in steady-state and corner use-cases?

To answer these questions, Cadence recommends the Performance Verification Methodology to ensure that the system performance meets requirements at the different levels:

1. Performance characterization: The first level of verification aims to verify the path-to-path traffic measuring the performance envelope. It targets integration bugs like clock frequency, buffer sizes, and bridge configuration. It requires to analyze the latency and bandwidth of design’s critical paths.
2. Steady state workloads: The second level of verification aims to verify the master-by-master defined loads using traffic profiles. It identifies the impact on bandwidth when running multi-master traffic with various Quality-of-Service (QoS) settings. It analyzes the DDR sub-system’s efficiency, measures bandwidth and checks whether masters’ QoS requirements are met.
3. Application specific use cases: The last level of verification simulates the use-cases and reaches the application performance corner cases. It analyzes the master-requested bandwidth as well as the DDR sub-system’s efficiency and bandwidth.

Cadence has developed a set of tools to assist customers in performance validation of their SoCs. Cadence Interconnect Workbench simplifies the setup and measurement of performance and verification testbenches and makes debugging of complex system behaviors a snap. The solution works with Cadence Verification IPs and executes on the Cadence Xcelium® Enterprise Simulator or Cadence Palladium® Accellerator/Emulator, with coverage results collected and analyzed in the Cadence vManager  Metric-Driven Signoff Platform.

To verify the performance of the Steady State Workloads, Arm has just released a new AMBA Adaptive Traffic Profile (ATP) specification which describes AMBA abstract traffic attributes and defines the behavior of the different traffic profiles in the system.

With the availability of Cadence Interconnect Workbench and AMBA VIP support of ATP, early adopters of the AMBA ATP specification can begin working immediately, ensuring compliance with the standard, and achieving the fastest path to SoC performance verification closure.

For more information on the AMBA Adaptive Traffic Profile, you can visit Dimitry's blog on AMBA Adaptive Traffic Profiles: Addressing The Challenge. 

More information on Cadence Interconnect Workbench solution is available at Cadence Interconnect Solution webpage.

Thierry