Hello,
I'm exploring VManager tool capabilities.

I launched a simulation with xrun, which terminates with a fatal error (`uvm_fatal actually).

Then I imported the flow session, through VManager -> Regression -> Collect Runs, linking the directory with ucm and ucd of just failed run.

VManager imports the test with following attributes:

Total Runs =1

#Passed =1

#Failed =0

What I'm missing here? It should be imported as failed test.

If I right click on flow name and choose Analyze All Runs, VManager brings me to Analysis tab and I can see only a PASSED tag in Runs subwindow.

Thank you for any help

Hi all,

I would like to understand if it is possible from Simvision to get the information regarding the view of a block. In principle using the Schematic Tracer Simvision is able to find the information about the config of that particular model, but I did not found a command for describing the nature of the module (for example if it is schematic or rtl or real model...)

Any functions that I can use for this purpose?

Many thanks

Hello!

I have input signal like this  ->  input  wire [ADM_NUM-1:0][1:0] m_axi_ddr_rresp.

When i want to analyze coverage from IMC  this signal not covered!

Can i collect coverage for this signal?

Hi All,

I'm trying to understand checkpoint concept. When I found save and restart concept in cdnshelp, There is just describing about "$save" and "xrun -r "~~~".

and I found also the below link about save restart and it saves your time.

But I can't find any benefits from my experiment from save&restart article( I fully agree..the article)

Ok, So I'v got some experiment  Here.

1. I declared $save and got the below result as I expected within the simple UVM code.

In UVM code...

$display("TEST1");
$display("TEST2");
$save("SAVE_TEST");
$display("TEST3");
$display("TEST4");

And I restart at "SAVE_TEST" point by xrun -r "SAVE_TEST", I've got the below log

xcelium> run
TEST3
TEST4

Ok, It's Good what I expected.(The concept of Save and Restore is simple: instead of re-initializing your simulation every time you want to run a test, only initialize it once. Then you can save the simulation as a “snapshot” and re-run it from that point to avoid hours of initialization times. It used to be inconvenient. I agree..)

2. But The Problem is that I can't restart with modified code. Let's see the below example.

I just modified TEST5 instead of "TEST3"

$display("TEST1");
$display("TEST2");
$save("SAVE_TEST");
$display("TEST5"); //$display("TEST3");
$display("TEST4");

and I rerun with xrun -r "SAVE_TEST", then I've got the same log

xcelium> run
TEST3
TEST4

There is no "TEST5". Actually I expected "TEST5" in the log.From here We know $save can't support partially modified code after $save. 

Actually, through this, we can approach to our goal about saving developing time. 

So I want to know Is there any possible way that instead of re-initializing our simulation every time we want to run a test, only initialize it once and keep developing(debugging) our code ?

If we do, Could you let me know the simple example?

I have a problem connected with my AXI4 coverage.

I enable coverage collection in AXI4 

      set_config_int("axi4_active_slave_agent_0.monitor.coverModel", "burst_started_enable", 1);
      set_config_int("axi4_active_slave_agent_0.monitor.coverModel", "coverageEnable", 1);

but i don't have a result.

I think the problem in Callback, but i try to connect all callback and i don't have positive result.

Can you help me?

Hi all,

         I want to know how to run a regressive test in cadence and merge all ncsim .trn file of each test case into a single file to view all waveform in simvision. I am using Makefile to invoke the test case.

         eg:-

               test0:

                     irun -uvm -sv -access +rwc $(RTL) $(INTER) $(PKG) $(TOP) $(probe) +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test0

             test1:

                   irun -uvm -sv -access +rwc $(RTL) $(INTER) $(PKG) $(TOP) $(probe) +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test1

          I just to call test0 followed by test1 or parallel both test and view the waveform for both tests case.

        I new to this tool and help me with it

Hi  all,

          I am getting this warning in while generating the coverage report, can you help me to clear this warning?

ncsim: *W,COVOPM: Coverage configuration file command "set_covergroup -optimize_model" can be specified to improve the performance and scalability of coverage model containing SV covergroups. It may be noted that subsequent merging of a coverage database saved with this command and a coverage database saved without this command is not allowed.

Hi all,

I need to develop a digital design/verification solution to compile,elaborate and simulate SV designs (basically a complex xrun wrapper). I am an experienced user of xrun and I have done a number of these wrappers over the years but this one is to be more of a tool, intented to be used Company-wise, so it needs to be very well thought and engineered.

It needs to be robust, simple and extensible. It needs to support multi-snapshot elaboration, run regressions on machine farms, collect coverage, create reports, etc.

I've been browsing the vast amount of documentation on XCELIUM and, although very good, I can't find any document which puts together all the pieces of what I am trying to achieve. I suppose I am more clear on the elaboration, compilation and simulation part but I am really lacking on the other areas like : LSF, regressions coverage, where does vManager fits in all this, etc.

I'd appreciate if someone can comment on whether there is a document which depicts how such a DV flow can be put together from scratch, or whether there is a kind of RAK with some example xrun wrapper.

Thanks

Hello folks,

Greetings.

One of my customer claims that he is using Cadence IES version 18.09.011 with Vivado 2019.2. The version of IES that we officially support with Vivado 2019.2 is 15.20.073. Though the tool is forward compatible, I am not sure what are the versions of IES that are released after 15.20.073. Could you please give me a list of the versions of Cadence IES released after 15.20.073 and which is the latest version as of now ?

Best regards,

Chinmay

Hi,

I found a basic Specman E/Verilog program at http://www.asic-world.com/examples/specman/memory.html and I would like to run it through a vsif file, with vManager.

I'm able to run it, without problems, with this command : xrun -Q -unbuffered '-timescale' '1ns/1ns' '-access' '+rw' memory_tb.v mem_tb_top.e test_write_read_all.e.

I wrote a first vsif which look like this:

---- vm_basic.vsif -----

session vm_basic {
        top_dir : /home/cadence/xrunTest/;
        output_mode: terminal;
};

group basic {
        test test {
                run_script: xrun -Q -unbuffered '-timescale' '1ns/1ns' '-access' '+rw' memory_tb.v mem_tb_top.e test_write_read_all.e
        };
};

----------------------------

This solution didn't work due to the prompt change with xrun, and I have no clue how to manage this issue.

Have you any idea?

Best regards,

Yohan

Hi Team,

I would like to download "Incisive Metrics Center User Guide", I could not find in the cadence/support/manuals. Can you please provide me the link or path to download the same ? I am doing functional coverage with IMC. 

Thank You,

Mahesh

Hi,

I am facing this elaboration error when using Xcelium:

Command>

    xmverilog -v200x +access+r +xm64bit -f vlist -reflib plib -timescale 1ns/1ps

Log>

    xmelab: *E,CUVMUR (<name>.v,538|18): instance 'LUTP0.C GLAT3' of design unit 'tlatntscad12' is unresolved in 'worklib.LUTP0:v'.

I guess the plib was not referred to as the simulation configuration because the tlatntscad12 is included in plib.

The plib is compiled by INCISIVE 13.20 and I am using the Xcelium 19.30.

Please tell me the correct command on how to refer to the library directory compiled by different versions.

Thank you,

I am importing sessions which are run by other people to analyse and I would like to remove them from my vManager Regressions tab as they become obsolete. As I am not the original person who run the sims, I cannot "delete" sessions. What are my options? Thanks.

I'm in the process of weeding a regression test list. I have a coverage database from the full regression list and would like to diff it with the coverage database from the new reduced regression test list. If possible I would than like to trace back any buckets covered with the full list, but not with the partial list, into the original tests that covered them.

Is that possible using IMC? if not, is it possible to do from Specman itself?

(Note that we're not using vManager)

Thanks,

Avidan

I'm trying to compile a simple verilog file using xmvlog. I run the following command,

"xmvlog myfile.v"

Then I get the following error,

"xmvlog: *F,DIRDEC: Can't save decompressed versions of compressed files."

I used to use xmvlog with no issues, this error started to come up now. The message is not helpful either. How can I solve this?

I appreciate any help, thanks in advance.

They say Moore's law is slowing. It may be slowing but it is still running - it has not stopped! And, it has been running at full throttle for quite a few decades now.  The net result of this run? Well, you can't design ICs in isolation from the...(read more)

In the Allegro back-end layout products like Allegro Package Designer Plus, it would be reasonable to assume that the most often used command is none other than “show element” (shortcut key F4). This command, runnable at nearly any t...(read more)

Molding caps aren’t something we talk about too frequently around here. We all know they exist, and they serve an important purpose of protecting the delicate die from potentially harsh environmental conditions. They impact how well heat can be...(read more)

Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain (any-angle routing, filled planes, and a multitude of pad ...(read more)

We have talked about aspects of the in-design symbol edit application mode in the past. This is the environment specific to the Allegro Package Designer layout tools allowing you to work on symbol definitions directly in the context of your layout de...(read more)

Here are two screen capture of Before and After Autorouting my board. Padstacks have all been revised and corrected. The Capture Schematic is correct. All Footprints have been verified after Padstack revision. a new NETLIST generation have been done after some corrections made in Capture. I have imported the new Logic. I revised my Layout Cross Section as such: TOP, GND, VCC, BOTTOM. Both VCC and GND shapes have been assigned to their respective logical GND and VCC Nets (verified). Yet, I still have the Autorouter to systematically use extra vias to make GND and VCC connections to the VCC and GND planes. Where a simple utilisation of the part padstack inner layer would have been indicated. What Im I missing ?

I've redesigned a custom TO220FLAT Package

First I created a TO220shape.ssm  with PCB Editor. Then I created a surface mount T220build.pad in Padstack Editor using TO220shape.ssm. Then I created a TO220FLAT.psm in PCB Editor. I placed 3 Connect pins and 9 Mechanical pins for the TO220 TAB, using standard through-hole pads for better current handling.

Adding those Mechanical pins created many DRC errors caused by the proximity of those pads attached to the TO220shape.

Thru Pin to SMD Pin Spacing (-200.0 0.0) 5 MIL OVERLAP DEFAULT NET SPACING CONSTRAINTS Mechanical Pin "Pad50sq30d" Pin "T220build, 2"

I corrected the situation (so I though) by Waiving those DRC errors, thinking that they could not cause any problem and because that’s what I want, i.e.: 9 through-holes under the TO220 device. The idea being that when this device is mounted flat on the PCB it could carry lots of current via 9 pads that could make a good high current conductor to inner layers.

I then saved the Package and updated all related footprint schematic parts  in Capture. Created a new Netlist. Then I imported the new logic into PCB Editor to reflect that change. When the File > Import > Logic is finished I get no feedback error! (which, for me is a substantial achievement in itself)

Now, in the Design Window I see all those DRC errors popping up again, despite the fact that I waived those DRCs back in the Padstack edition. If I run a Design Rule Check (DRC) Report I will see all those DRC listed again. Now, I understand that I can go ahead and waive all those DRCs (100 in total) but I’m thinking there is got to be a better way of doing this.

Please, any advise is welcome. Thanks

Hello all,

We are designing a backplane and in the design we are using some custom prefixes using the Advance Annotation tool. When annotating the occurances I get the following error:

ERROR(ORDBDLL-1224): The total number of components for prefix J0C exceeds the range supplied for it.
Increase the End value of the range.

Thanks in advance for the help

--Tom

Greeting to all:

I am new in this tool, only 2 weeks. Trying to create a new Via with smaller size drill hole from exiting 13 mils size to 10 mils size. I got the message as imaged below. Any advise what to do?  Thanks in advance.

Hi everybody,

I've created a symbol with custom pad shapes. Everything looks correct in the symbol editor.

And the 3d view looks correct (upside down to show placement)

But when I try to place it on the pcb the 2 "T" shaped pads aren't in the correct location.

I have the pad shape centered on the pad...

with no offset on the padstack editor.

Does anybody know how to fix this?

Thank you!

Hi There,

The variant bom I set gone dissapear. Is there any way to recover this back from the old design file? 

This is the second time it happen to me. Not really sure what could cause this. 

Thanks,

Pornchai

Hi, I am uploading a register class, which can be used for modeling hardware registers. I am uploading the source code and examples on how to run it. I also have a user guide which has all the APIs listed and explained. The user guide is ARV.pdf in the attached tar file. I have named the class ARV, which stands for Architect's Register View. It has got very good randomization and coverage features. Users have told me that its better than RAL. You can download it from http://verisilica.info/ARV.php
. There is a limit of 750KB in this cadence website. The ARV file is 4MB. That is why, I am uploading it at this site. I have a big pdf documentation and a doxygen documentation there. That is the reason for the bigger file size. The password to open the ZIP file is ovm_arv. I hope, everyone will use these classes.

Please contact me for any help.
Regards ANil

Hi All.

I put together a small Perl script to generate vr_ad register definitions from SPIRIT (IP-XACT) XML.
If you've got not idea what IP-XACT is, have a look here http://www.spiritconsortium.org/, then start pestering your design manager to use it :-)

The script can filter out registers and override R/W access types if needed.

An example XML file is included with the package so that you can play with it, and there's a detailed README.txt as well.

Here's an example of the generated e code:

// Automatically generated from xdmac.xml
// DO NOT EDIT, or your changes may be lost
<'

import vr_ad/e/vr_ad_top;

// Component = XDMAC
// memoryMap = xdmac
extend vr_ad_map_kind : [XDMAC];

// addressBlock = dma_eth
extend vr_ad_reg_file_kind : [DMA_ETH];

extend DMA_ETH vr_ad_reg_file {
  keep size == 20;
  keep addressing_width_in_bytes == 4;
};

// Register = command
// Reset    = 0x00
reg_def COMMAND DMA_ETH 0x0 {
  // Field resv3 = command[31:29]
  reg_fld resv3 : uint(bits:3) : R : 0 : cov ;
  // Field transfer_size = command[28:19]
  reg_fld transfer_size : uint(bits:10) : RW : 0 : cov ;
  // Field dma_transfer_target = command[18:14]
  reg_fld dma_transfer_target : uint(bits:5) : RW : 0 : cov ;
  // Field resv2 = command[13:10]
  reg_fld resv2 : uint(bits:4) : R : 0 : cov ;
  // Field transmit_receive = command[9:9]
  reg_fld transmit_receive : uint(bits:1) : RW : 0 : cov ;
  // Field resv1 = command[8:5]
  reg_fld resv1 : uint(bits:4) : R : 0 : cov ;
  // Field dest_address_enable = command[4:4]
  reg_fld dest_address_enable : uint(bits:1) : RW : 0 : cov ;
  // Field source_address_enable = command[3:3]
  reg_fld source_address_enable : uint(bits:1) : RW : 0 : cov ;
  // Field word_size = command[2:0]
  reg_fld word_size : uint(bits:3) : R : 0 : cov ;
};

// Register = queue_exec
// Reset    = 0x00
reg_def QUEUE_EXEC DMA_ETH 0x10 {
  // Field resv = queue_exec[31:1]
  reg_fld resv : uint(bits:31) : R : 0 : cov ;
  // Field exec = queue_exec[0:0]
  reg_fld exec : uint(bits:1) : RW : 0 : cov ;
};

extend XDMAC vr_ad_map {
  dma_eth : DMA_ETH vr_ad_reg_file;

  post_generate() is also {
    add_with_offset(0x00, dma_eth);
    dma_eth.reset();
  };
}
'>

Any comments, please feed them back to me so I can enhance the script.
Note that this forum forces me to post a .zip file rather than .tgz, please be careful to unpack the file under Linux, not Windows, else the DOS linefeeds will corrupt the Perl and XML files.

Steve

 Hi,

I'm using OVM transaction level tracing in SV. I was wondering if I can have simvision render different types of transactions with different colors e.g. based on a transaction attribute. I know how to do it at signal level using mnemonics but I haven't succeeded doing this at transaction level. Anyone?

 -Joep

In a nutshell, tags allows you to navigate through program code distributed over multiple files effectively. e.g if you see a function call or a struct in e-code and want to "jump" to the definition (which may be in a different file) then you just hit CTRL+] in Vim! Pressing CTRL+t will take you back where you came from. Check out http://vim.wikia.com/wiki/Browsing_programs_with_tags#Using_tags if you want to learn more about how to use tags with Vim.

This utility can generate tags file for your e files. It can either walk through e import order, a directory recursively or all directories on SPECMAN_PATH recursively! The tags file will have tags for struct, unit, types, events, defines, fields, variables, etc.

For help and some examples, just run ctags4e -help.

Hello All,

Following is the einstein's puzzle solved by cadence Incisive92  (solved in less than 3 seconds -> FAST!!!!!!)

Thanks,

Vinay Honnavara

Verification engineer at Keyu Tech

vinayh@keyutech.com

 // Author: Vinay Honnavara

// Einstein formulated this problem : he said that only 2% in the world can solve this problem
// There are 5 different parameters each with 5 different attributes
// The following is the problem

// -> In a street there are five houses, painted five different colors (RED, GREEN, BLUE, YELLOW, WHITE)

// -> In each house lives a person of different nationality (GERMAN, NORWEGIAN, SWEDEN, DANISH, BRITAIN)

// -> These five homeowners each drink a different kind of beverage (TEA, WATER, MILK, COFFEE, BEER),

// -> smoke different brand of cigar (DUNHILL, PRINCE, BLUE MASTER, BLENDS, PALL MALL)

// -> and keep a different pet (BIRD, CATS, DOGS, FISH, HORSES)


///////////////////////////////////////////////////////////////////////////////////////
// *************** Einstein's riddle is: Who owns the fish? ***************************
///////////////////////////////////////////////////////////////////////////////////////

/*
Necessary clues:

1. The British man lives in a red house.
2. The Swedish man keeps dogs as pets.
3. The Danish man drinks tea.
4. The Green house is next to, and on the left of the White house.
5. The owner of the Green house drinks coffee.
6. The person who smokes Pall Mall rears birds.
7. The owner of the Yellow house smokes Dunhill.
8. The man living in the center house drinks milk.
9. The Norwegian lives in the first house.
10. The man who smokes Blends lives next to the one who keeps cats.
11. The man who keeps horses lives next to the man who smokes Dunhill.
12. The man who smokes Blue Master drinks beer.
13. The German smokes Prince.
14. The Norwegian lives next to the blue house.
15. The Blends smoker lives next to the one who drinks water.
*/




typedef enum bit [2:0]  {red, green, blue, yellow, white} house_color_type;
typedef enum bit [2:0]  {german, norwegian, brit, dane, swede} nationality_type;
typedef enum bit [2:0]  {coffee, milk, water, beer, tea} beverage_type;
typedef enum bit [2:0]  {dunhill, prince, blue_master, blends, pall_mall} cigar_type;
typedef enum bit [2:0]  {birds, cats, fish, dogs, horses} pet_type;




class Einstein_problem;

    rand house_color_type house_color[5];
    rand nationality_type nationality[5];
    rand beverage_type beverage[5];
    rand cigar_type cigar[5];
    rand pet_type pet[5];
        rand int arr[5];
    
    constraint einstein_riddle_solver {
    
        
    
        foreach (house_color[i])
            foreach (house_color[j])
               if (i != j)
                house_color[i] != house_color[j];
        foreach (nationality[i])
            foreach (nationality[j])
               if (i != j)
                nationality[i] != nationality[j];
        foreach (beverage[i])
            foreach (beverage[j])
               if (i != j)
                beverage[i] != beverage[j];
        foreach (cigar[i])
            foreach (cigar[j])
               if (i != j)
                cigar[i] != cigar[j];
        foreach (pet[i])
            foreach (pet[j])
               if (i != j)
                pet[i] != pet[j];
    
    
        //1) The British man lives in a red house.
        foreach(nationality[i])
                (nationality[i] == brit) -> (house_color[i] == red);
                
        
        //2) The Swedish man keeps dogs as pets.
        foreach(nationality[i])
                (nationality[i] == swede) -> (pet[i] == dogs);
                
                
        //3) The Danish man drinks tea.        
        foreach(nationality[i])
                (nationality[i] == dane) -> (beverage[i] == tea);
        
        
        //4) The Green house is next to, and on the left of the White house.
        foreach(house_color[i])        
                 if (i<4)
                    (house_color[i] == green) -> (house_color[i+1] == white);
        
        
        //5) The owner of the Green house drinks coffee.
        foreach(house_color[i])
                (house_color[i] == green) -> (beverage[i] == coffee);
                
        
        //6) The person who smokes Pall Mall rears birds.
        foreach(cigar[i])
                (cigar[i] == pall_mall) -> (pet[i] == birds);
        
        
        //7) The owner of the Yellow house smokes Dunhill.
        foreach(house_color[i])
                (house_color[i] == yellow) -> (cigar[i] == dunhill);
        
        
        //8) The man living in the center house drinks milk.
        foreach(house_color[i])
                if (i==2) // i==2 implies the center house (0,1,2,3,4) 2 is the center
                    beverage[i] == milk;
        
        
        
        //9) The Norwegian lives in the first house.
        foreach(nationality[i])        
                if (i==0) // i==0 is the first house
                    nationality[i] == norwegian;
        
        
        
        //10) The man who smokes Blends lives next to the one who keeps cats.
        foreach(cigar[i])        
                if (i==0) // if the man who smokes blends lives in the first house then the person with cats will be in the second
                    (cigar[i] == blends) -> (pet[i+1] == cats);
        
        foreach(cigar[i])        
                if (i>0 && i<4) // if the man is not at the ends he can be on either side
                    (cigar[i] == blends) -> (pet[i-1] == cats) || (pet[i+1] == cats);
        
        foreach(cigar[i])        
                if (i==4) // if the man is at the last
                    (cigar[i] == blends) -> (pet[i-1] == cats);
        
        foreach(cigar[i])        
                if (i==4)
                    (pet[i] == cats) -> (cigar[i-1] == blends);
        
        
        //11) The man who keeps horses lives next to the man who smokes Dunhill.
        foreach(pet[i])
                if (i==0) // similar to the last case
                    (pet[i] == horses) -> (cigar[i+1] == dunhill);
        
        foreach(pet[i])        
                if (i>0 & i<4)
                    (pet[i] == horses) -> (cigar[i-1] == dunhill) || (cigar[i+1] == dunhill);
                    
        foreach(pet[i])        
                if (i==4)
                    (pet[i] == horses) -> (cigar[i-1] == dunhill);
                    


        //12) The man who smokes Blue Master drinks beer.
        foreach(cigar[i])
                (cigar[i] == blue_master) -> (beverage[i] == beer);
        
        
        //13) The German smokes Prince.
        foreach(nationality[i])        
                (nationality[i] == german) -> (cigar[i] == prince);
        

        //14) The Norwegian lives next to the blue house.
        foreach(nationality[i])
                if (i==0)
                    (nationality[i] == norwegian) -> (house_color[i+1] == blue);
        
        foreach(nationality[i])        
                if (i>0 & i<4)
                    (nationality[i] == norwegian) -> (house_color[i-1] == blue) || (house_color[i+1] == blue);
        
        foreach(nationality[i])        
                if (i==4)
                    (nationality[i] == norwegian) -> (house_color[i-1] == blue);
        

        //15) The Blends smoker lives next to the one who drinks water.            
        foreach(cigar[i])            
                if (i==0)
                    (cigar[i] == blends) -> (beverage[i+1] == water);
        
        foreach(cigar[i])        
                if (i>0 & i<4)
                    (cigar[i] == blends) -> (beverage[i-1] == water) || (beverage[i+1] == water);
                    
        foreach(cigar[i])        
                if (i==4)
                    (cigar[i] == blends) -> (beverage[i-1] == water);
        
    } // end of the constraint block
    


    // display all the attributes
    task display ;
        foreach (house_color[i])
            begin
                $display("HOUSE : %s",house_color[i].name());
            end
        foreach (nationality[i])
            begin
                $display("NATIONALITY : %s",nationality[i].name());
            end
        foreach (beverage[i])
            begin
                $display("BEVERAGE : %s",beverage[i].name());
            end
        foreach (cigar[i])
            begin
                $display("CIGAR: %s",cigar[i].name());
            end
        foreach (pet[i])
            begin
                $display("PET : %s",pet[i].name());
            end
        foreach (pet[i])
            if (pet[i] == fish)
                $display("THE ANSWER TO THE RIDDLE : The %s has %s ", nationality[i].name(), pet[i].name());
    
    endtask // end display
    
    
endclass




program main ;

    initial
        begin
            Einstein_problem ep;
            ep = new();
            if(!ep.randomize())
                $display("ERROR");
            ep.display();
        end
endprogram // end of main

        

Hello All,

I have a situation where i want to implement 8 instance of some particular reg_file which all have many reg_def and reg_fld.

For example :
I have 8 instance of one DUT module (TEST0, TEST1,TEST2... TEST8), since its all are the instance so all the instance will have the sets of registers.. so to implement reg for one instance i can write code like..

extend vr_ad_reg_file_kind : [TEST0];
extend TEST0 vr_ad_reg_file {
keep size == 256;
};
reg_def EX_REG_TX_DATA TEST0 8’h00 {
// name : type : mask : reset value
reg_fld data : uint(bits:8) : RW : 0;
};

But now the issue is inside 1 instance i have around 256 registers, and i need to implement for all the 8 instance.... so can anyone suggest me how we can make instance for vr_ad_reg_file, otherwise i have to write same code for all the 8 instance.

Thanks

 hi,

i am doing a project on synchronous fifo design using verilog. below written is my coding. after simulation the waveform is showing error regarding its not giving value of rdata_valid and is showing a red line in waveform and due to it address is also not being taken.i have attached the waveform also. the logic for write logic is also not accepting the address(no change occurs while changing value of read_ptr). i have attached my file with it so plz refer to it.

plz help me out in this. your guidance and solns will help me in completing my project work.

thank you

lov sareen

Just in time for the holidays, inside the posted tar ball is some code to solve 9x9 Sudoku puzzles with the Assertion-Driven Simulation (ADS) capability of Incisive Enterprise Verifier (IEV). Enjoy! Joerg Mueller Solutions Engineer for Team Verify

Hi all 

Good day.

Can anyone tell me whether it is possible to view the signals once it is modified from its previous values without closing the simvision window. If possible kindly let me know the command for it(Linux).

 Is it possible to view the schematic for the code written?? Kindly instruct me.

 Thanks all.

S K S 

Hello,

 I am working in a digital design. The functional, post synthesis and post P&R without IO pads are all working fine, i.e., functionally and with clean timing reports "no setup/hold violations". I just added the IO pads to the same design, I had to change the timing constraints a bit for the synthesis but I have a clean design at SOC Encounter, i.e., clean DRC and clean timing reports "no setup/hold violations". However, when I perform simulation using the exported net-list from SOC Encounter together with SDF exported from the same tool, I got a lot of hold violations. Consequently, the design is not funcitioning.

Why and how I can overcome or trobleshoot this issue?

In waiting for your feedback and comments.

Regards.

I want to write a transition coverage on an enumeration. One of the parts of that transition is a queue of the enum. I construct this queue in my constructor. Considering the example below, how would one go about it.

In my coverage bin I can create a range like this A => [queue1Enum[0]:queue1Enum[$]] => [queue2Enum[0]:queue2Enum[$]]. But I only get first and last element then.

typedef enum { red, d_green, d_blue, e_yellow, e_white, e_black } Colors;
 Colors dColors[$];
 Colors eColors[$];
 Lcolors = Colors.first();
 do begin
  if (Lcolors[0].name=='d') begin
   dColors.push_back(Lcolors);
  end
  if (Lcolors[0].name=='e') begin
   eColors.push_back(Lcolors);
  end
 end while(Lcolors != Lcolors.first())

 covergroup cgTest with function sample(Colors c);
   cpTran : coverpoint c{
      bins t[] = (red => dColors =>eColors);   
   }
 endgroup

Hello,

I have a question I want to create a cover that consists a sparse values, pre-computed (a list or define) for example l = {1; 4; 7; 9; 2048; 700} I'd like to cover that data a (uint(bits:16)) had those values, Any suggestion on how to achieve this, I'd prefer to stay away from macros, and avoid to write a lot of code

struct inst {

  data :uint(bits:16);
  opcode :uint(bits:16);
  !valid_data : list of uint(bits:16) = {0; 12; 10; 700; 890; 293;};
  event data_e;
  event opcode_e;

  cover data_e is {
     item data using radix = HEX, ranges = {
     //I dont want to write all of this
     range([0], "My range1");
     range([10], "My range2");
     //... many values in between
    range([700], "My rangen");
    };

    item opcode;

   cross data, opcode;
};

post_generate() is also {
    emit data_e;
};
};

Exporting a waveform into a vcsv file returns the error:

The wsSaveTraceCommand command generated an exception basic_string::_S_construct null not valid.

Only the first row of the vcsv file is created (";Version, 1, 0"). This was the first time I've exported waveforms generated with Assembler. I had no issue before with the combination of ADE L, Parametric sweep and ViVA XL. My project uses ICADV 12.3. I have not found any related forum entry or documentation. How could I export the waveforms in vcsv? Exporting the values into a table and then exporting into a csv works, but my post-processing script was written for vcsv format.

I'm trying to set up a VHDL-AMS simulation, so I made a new cell, selected the vhdlamstext type, and copied some example from the web. But when I hit the save and compile button, I first got the following NOLSTD error:

https://www.edaboard.com/showthread.php?27832-Simulating-a-VHDL-design-in-ldv5-1

So I added said file to my cds.lib and tried again. But now I'm getting this:

ncvhdl_p: *F,DLUNNE: Can't find STANDARD at /cadappl/ictools/cadence_ic/6.1.7.721/tools/inca/files/STD.

If I go over to the Library Browser, it indeed shows that the library is completely empty. Properties show it has the following files attached.

In the file system I've also found a STD.src folder. Is there a way to recompile the library properly? Supposedly this folder includes precompiled versions, but looks like not really.

Hi all,

Is there any tutorial which explains the process of plotting the ISF function for a certain oscillator ?

Thank you.

Hi ,

     I have designed analog IP in cadence ADE and simulated in spectre. All corner results looks good. when i run monte carlo 1000 runs have high current in 125C two runs. Simulated with same setup in different user, all clean.Need to know what type sampling method used and why its not clean with my setup.

Thanks,

Anbarasu

Hello,

I am running a transient simulation on my circuit and usually my simulation time took me more than a day (The circuit is quite big). I am usually saving specific nodes to decrease the simulation time. My problem is, since it usually took me one day to finish I need to save my trans simulation just in case something bad happens. I am aware that the transient simulation have the options for save/restore. But, when I tried to use it I have some problem. Whenever I restore the save file, it starts where it ends before (expected function) but my data is incomplete. It doesn't save the previous data. Its kind of my data is incomplete. What I did is set the saveperiod and savefile. I hope someone can help me. Thank you!

Regards,

Kiel

Hello,

I am trying to import multiple verilog modules defined in a single file with "`define" directive in the top using Verilog In. The code below is an example of what my file contains.

When I use the settings below to import the modules into a library, it imports it correctly but completely ignores all `define directive; hence when I simulate using any of the modules below the simulator errors out requesting these variables.

My question: Is there a way to make Verilog In consider `define directives in every module cell created? 

Code to be imported by Cadence Verilog In:

--------------------------------------------------------

`timescale 1ns/1ps
`define PROP_DELAY 1.1
`define INVALID_DELAY 1.3

`define PERIOD 1.1
`define WIDTH 1.6
`define SETUP_TIME 2.0
`define HOLD_TIME 0.5
`define RECOVERY_TIME 3.0
`define REMOVAL_TIME 0.5
`define WIDTH_THD 0.0

`celldefine
module MY_FF (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF
`endcelldefine

`timescale 1ns/1ps
`celldefine
module MY_FF2 (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF2
`endcelldefine

--------------------------------------------------------

I am using the following Cadence versions:

MMSIM Version: 13.1.1.660.isr18

Virtuoso Version: IC6.1.8-64b.500.1

irun Version: 14.10-s039

Spectre Version: 18.1.0.421.isr9

Hello,

I am trying to use calcVal for creating a spec condition from a simulated parameter and although this works perfectly fine in corner simulations, I am having some difficulties in Monte-Carlo (and I will explain).

(I have also read "Using calcVal() and its arguments with ADE Assembler" in Resources > Rapid Adoption Kits but couldn't find any relevant information that would help me address the "issue").

In the above example I am performing a MC simulation which has 2 corners of 10 runs each. I would like to get the minimum value of variable "OC_limit_thres" out of those 10 runs and pass it as my upper limit to a range argument for variable "OC_flag_thres", so the CPK can be calculated.

So the range statement should in reality be like this:

range 32m 44.34m (for corner 0)

range 32m 43.14m (for corner 1)

If I open the Detail - Transpose view in the Results tab, the calcVal("OC_limit_thres" "Currlim_TurnOn_C11") is calculated perfectly fine for each run but here I need one single value out of those 10 runs - in this case the minimum - in order for calcVal to evalute on multiple runs of 1 corner.

How can this be done please?

Thank you in advance for your time.

Hi,

I want to convert ircx file(which from TSMC) to ict or emDataFile for Voltus-fi.

I tried many way, but I can not make it.

and I  do not installed QRC.

below is some tools installed my server. 

IC617-64b.500.21 is used.

Hello,

I find a strange issue when using design variable -> right-click -> copy from cellview in assembler. Cadence version is IC618-64b. 500.9

In fact, I set the value of variable (e.g., AAA = 100), then after I right-click -> copy from cellview, AAA's is updated to other value. In my opinion "copy from cellview" should only update the missing variable to the list, but not change any variable value. 

Is there any mechanism could change variable value when using "copy from cellview"?

Thanks

Hi,

I am trying to characterize a D flip-flop for low voltage operation (0.6V) using Cadence Liberate (V16). This is a positive edge triggered D flip flop based on true-single-phase clocking scheme. After the characterization, the measurements reported for hold constraint arcs seem to deviate significantly from its (spectre) spice simulation.

The constraint and the power settings to the liberate are as follows : 

# -------------------------------------------- Timing Constraints --------------------------------------------------------------------------------
### Input waveform ###
set_var predriver_waveform 2;# 2=use pre-driver waveform
### Capacitance ###
set_var min_capacitance_for_outputs 1;# write min_capacitance attribute for output pins
### Timing ###
set_var force_condition 4
### Constraint ###
set_var constraint_info 2
#set_var constraint_search_time_abstol 1e-12 ;# 1ps resolution for bisection search
set_var nochange_mode 1 ;# enable nochange_* constraint characterization
### min_pulse_width ###
set_var conditional_mpw 0
set_var constraint_combinational 2

#---------------------------------------------- CCS Settings ----------------------------------------------------------------------------------------
set_var ccsn_include_passgate_attr 1
set_var ccsn_model_related_node_attr 1
set_var write_library_is_unbuffered 1

set_var ccsp_min_pts 15 ;# CCSP accuracy
set_var ccsp_rel_tol 0.01 ;# CCSP accuracy
set_var ccsp_table_reduction 0 ;# CCSP accuracy
set_var ccsp_tail_tol 0.02 ;# CCSP accuracy
set_var ccsp_related_pin_mode 2 ;# use 3 for multiple input switching scnarios and Voltus only libraries

#----------------------------------------------- Power ---------------------------------------------------------------------------------------------------
### Leakage ###
set_var max_leakage_vector [expr 2**10]
set_var leakage_float_internal_supply 0 ;# get worst case leakage for power switch cells when off
set_var reset_negative_leakage_power 1 ;# convert negative leakage current to 0

### Power ###
set_var voltage_map 1 ;# create pg_pin groups, related_power_pin / related_ground_pin
set_var pin_based_power 0 ;# 0=based on VDD only; 1=power based on VDD and VSS (default);
set_var power_combinational_include_output 0 ;# do not include output pins in when conditions for combinational cells

set_var force_default_group 1
set_default_group -criteria {power avg} ;# use average for default power group

#set_var power_subtract_leakage 4 ;# use 4 for cells with exhaustive leakage states.
set_var subtract_hidden_power 2 ;# 1=subtract hidden power for all cells
set_var subtract_hidden_power_use_default 3 ;# 3=subtract hidden power from matched when condition then default group
set_var power_multi_output_binning_mode 1 ;# binning for multi-output cell considered for both timing and power arcs
set_var power_minimize_switching 1
set_var max_hidden_vector [expr 2**10]
#--------------------------------------------------------------------------------------------------------------------------------------------------------------

I specifically used set_var constraint_combinational 2 in the settings, in case the Bisection pass/fail mode fails to capture the constraints. In my spice simulation, the hold_rise (D=1, CLK=R, Q=R) arc at-least requires ~250 ps for minimum CLK/D slew combination (for the  by default smallest capacitive load as per Liberate)  while Liberate reports only ~30 ps. The define_cell template to this flip flop is pretty generic, which does not have any user specified arcs. So which settings most likely affecting the constraint measurements in Liberate and how can I debug this issue ?

Thanks

Anuradha

Hello,

I am trying to import (in spectre) an spice model of a ceramic capacitor manufactured by Samsung EM. The link that includes the model is here :-

http://weblib.samsungsem.com/mlcc/mlcc-ec.do?partNumber=CL05A156MR6NWR

They proved static spice model and interactive spice model.

I had no problem while including the static model.

However, the interactive model which models voltage and temperature coefficients seems to not be an ordinary spice model. They provide HSPICE, LTSPICE, and PSPICE model files and I failed to include any of them.

Any suggestions ?