1 Papua New Guinean Kina = 4.537 Egyptian Pound

1 Papua New Guinean Kina = 4.1577 Estonian Kroon

1 Papua New Guinean Kina = 37.4116 Algerian Dinar

1 Papua New Guinean Kina = 16.045 Dominican Peso

1 Papua New Guinean Kina = 2.0059 Danish Krone

1 Papua New Guinean Kina = 7.3265 Czech Republic Koruna

1 Papua New Guinean Kina = 165.8525 Costa Rican Colon

1 Papua New Guinean Kina = 1135.88 Colombian Peso

1 Papua New Guinean Kina = 2.0622 Chinese Yuan Renminbi

1 Papua New Guinean Kina = 240.7325 Chilean Peso

1 Papua New Guinean Kina = 0.2831 Swiss Franc

1 Papua New Guinean Kina = 0.4086 Canadian Dollar

1 Papua New Guinean Kina = 3.5402 Botswana Pula

1 Papua New Guinean Kina = 1.6711 Brazilian Real

1 Papua New Guinean Kina = 2.0102 Bolivian Boliviano

1 Papua New Guinean Kina = 0.412 Brunei Dollar

1 Papua New Guinean Kina = 0.1102 Bahraini Dinar

1 Papua New Guinean Kina = 0.5263 Bulgarian Lev

1 Papua New Guinean Kina = 24.777 Bangladeshi Taka

1 Papua New Guinean Kina = 0.4461 Australian Dollar

1 Papua New Guinean Kina = 19.3777 Argentine Peso

1 Papua New Guinean Kina = 0.5233 Netherlands Antillean Guilder

1 Papua New Guinean Kina = 1.0708 United Arab Emirates Dirham

1 Brunei Dollar = 3672.0066 Zambian Kwacha

1 Brunei Dollar = 21.1263 New Taiwan Dollar

1 Brunei Dollar = 6.9144 Swedish Krona

1 Brunei Dollar = 2.4273 Papua New Guinean Kina

1 Brunei Dollar = 1.1528 New Zealand Dollar

1 Brunei Dollar = 7.2294 Norwegian Krone

1 Brunei Dollar = 0.2189 Kuwaiti Dinar

1 Brunei Dollar = 863.1108 South Korean Won

1 Brunei Dollar = 2.4813 Israeli New Sheqel

1 Brunei Dollar = 0.6871 Swiss Franc

1 Brunei Dollar = 8.5931 Botswana Pula

Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends upon how and where it is used and in part, because even the best IP may work better in one system than another—even in chips developed by the same vendor.  

So, how do you measure IP quality and why it is so complicated?

The answer depends on who is asking. Most of the time, the definition of IP quality depends on your vantage point.  If you are an R&D manager, IP quality means something. If you are a global supply manager, IP quality means something else. If you are an SoC start-up, your measure of quality is quite different from that of an established fabless company. If you are designing IP in-house, then your considerations are very different than being a commercial IP vendor. If you are designing an automotive SoC, then we are in a totally different category. How about as an IP vendor? How do you articulate IP quality metrics to your customers?

This varies greatly by the type of IP, as well. When it comes to interface (hard) IP and controllers, if you are an R&D manager, your goal is to design IP that meets the IP specifications and PPA (power, performance, and area) targets. You need to validate your design via silicon test chips. This applies to all hard PHYs, which must be mapped to a particular foundry process. For controllers that are in RTL form—we called these soft IP—you have to synthesize them into a particular target library in a particular foundry process in order to realize them in a physical form suitable for SoC integration. Of course, your design will need to go through a series of design validation steps via simulation, design verification and passing the necessary DRC checks, etc. In addition, you want to see the test silicon in various process corners to ensure the IP is robust and will perform well under normal process variations in the production wafers.

For someone in IP procurement, the measure of quality will be based on the maturity of the IP. This involves the number of designs that have been taped out using this IP and the history of bug reports and subsequent fixes. You will be looking for quality of the documentation and the technical deliverables. You will also benchmark the supplier’s standard operating procedures for bug reporting and technical support, as well as meeting delivery performance in prior programs. This is in addition to the technical teams doing their technical diligence.

An in-house team that is likely to design IP for a particular SoC project will be using an established design flow and will have legacy knowledge of last generation’s IP. They may be required to design the IP with some reusability in mind for future programs. However, such reusability requirements will not need to be as stringent and as broad as those of commercial IP vendors because there are likely to be established metrics and procedures in place to follow as part of the design team’s standard operating procedures. Many times, new development based on a prior design that has been proven in use will be started, given this stable starting point. All of these criteria help the team achieve a quality outcome more easily.

Then, if designing for an automotive SoC, additional heavy lifting is required.  Aside from ensuring that the IP meets the specifications of the protocol standards and passes the compliance testing, you also must pay attention to meeting functional safety requirements. This means adherence to ISO 26262 requirements and subsequently achieving ASIL certification. Oftentimes, even for IP, you must perform some AEC-Q100-related tests that are relevant to IP, such as ESD, LU, and HTOL.

To read more, please visit: https://semiengineering.com/why-ip-quality-is-so-difficult-to-determine/

With more and more SoCs employing sophisticated interconnect IP to link multiple processor cores, caches, memories, and dozens of other IP functions, the designs are enabling a new generation of low-power servers and high-performance mobile devices. The complexity of the interconnects and their advanced configurability contributes to already formidable design and verification challenges which lead to the following questions:

While your interconnect subsystem might have a correct functionality, are you starving your IP functions of the bandwidth they need? Are requests from latency-critical initiators processed on time? How can you ensure that all applications will receive the desired bandwidth in steady-state and corner use-cases?

To answer these questions, Cadence recommends the Performance Verification Methodology to ensure that the system performance meets requirements at the different levels:

1. Performance characterization: The first level of verification aims to verify the path-to-path traffic measuring the performance envelope. It targets integration bugs like clock frequency, buffer sizes, and bridge configuration. It requires to analyze the latency and bandwidth of design’s critical paths.
2. Steady state workloads: The second level of verification aims to verify the master-by-master defined loads using traffic profiles. It identifies the impact on bandwidth when running multi-master traffic with various Quality-of-Service (QoS) settings. It analyzes the DDR sub-system’s efficiency, measures bandwidth and checks whether masters’ QoS requirements are met.
3. Application specific use cases: The last level of verification simulates the use-cases and reaches the application performance corner cases. It analyzes the master-requested bandwidth as well as the DDR sub-system’s efficiency and bandwidth.

Cadence has developed a set of tools to assist customers in performance validation of their SoCs. Cadence Interconnect Workbench simplifies the setup and measurement of performance and verification testbenches and makes debugging of complex system behaviors a snap. The solution works with Cadence Verification IPs and executes on the Cadence Xcelium® Enterprise Simulator or Cadence Palladium® Accellerator/Emulator, with coverage results collected and analyzed in the Cadence vManager  Metric-Driven Signoff Platform.

To verify the performance of the Steady State Workloads, Arm has just released a new AMBA Adaptive Traffic Profile (ATP) specification which describes AMBA abstract traffic attributes and defines the behavior of the different traffic profiles in the system.

With the availability of Cadence Interconnect Workbench and AMBA VIP support of ATP, early adopters of the AMBA ATP specification can begin working immediately, ensuring compliance with the standard, and achieving the fastest path to SoC performance verification closure.

For more information on the AMBA Adaptive Traffic Profile, you can visit Dimitry's blog on AMBA Adaptive Traffic Profiles: Addressing The Challenge. 

More information on Cadence Interconnect Workbench solution is available at Cadence Interconnect Solution webpage.

Thierry

PCIe has been widely adopted in the electronics industry since its first debut in 2003 (PCIe 1.0 standard release) for wide breach of applications, from Data Center Server, Networking, to Mobile, AI/ML, Automotive, IoT, and many others…. It’s a versatile, high-performance, robust, mature interconnect standard with full “backward compatibility” (e.g., a PCIe 3.0 device can still function well in a PCIe 4.0 system) which enables a solid and strong PCIe eco-system in the industry.  While the market, so as the users,  are enjoying the systems, e.g., desktop/laptop, powered (or to be more specific: “bridged”) by PCIe 3.0 since 2010, the industry is pushing hard for the PCIe 4.0 eco-system enablement. Earlier this year, AMD announced it X570 chipset would support the PCIe 4.0 interface and Phison also introduced the world’s first PCIe 4.0 SSD.

On the standard evolution front, the official PCIe 5.0 came out in May 2019, doubling the data rate to 32GT/s from 16GT/s in PCIe 4.0. The PCIe 6.0 standard will be released in 2021 based on the announcement made by PCI-SIG in June’19 with the goal to further double the data rate to 64GT/s with incorporating the PAM4 coding.

PCIe Protocol Evolution

Having said that, is the latest generation of PCIe always desired?  

My answer would be positive. Just like car maker/enthusiast has kept pursuing faster car in the history, there is no doubt that these speed enhancements/upgrades in the electronic world certainly provide a tremendous benefit for especially those applications craving the most throughput, such as Data center, HPC, Networking, Cloud and AI applications.   

But, does every application have to opt for the fastest speed (bandwidth)? My view would be leaning toward “Not really”. Just like we don’t need a 3-second sport car (meaning 0-60mph acceleration < 3s) for daily commute though it would certainly spice some driving fun on the road, but it may not be "the best fit" for most of commuters.

There are applications still well satisfied with PCIe 3.0 (or even older PCIe 2.0) for its best performance and cost balance.  Those applications include, but not limit to, IoT/consumer, Edge AI, SSD (non-enterprise),…etc. They typically need to make trade-off in between the cost, power consumption (especially battery powered), flexibility on changing product features, and time-to-market (TTM). To address such type of market needs, Cadence also offers an PPA (Performance, Power, Area) optimized PCIe 3.0 solution in addition to its high-performance PCIe 4.0 product line.

Cadence PCIe 3.0 PHY Solution (with Multi-Protocol Multi-Link feature)

With leveraging the multi-protocol SerDes implementation, the same Cadence PHY IP support multi-protocol and multi-link operation. Such a multi-protocol enabled PHY gives the SoC developers the optimum flexibility to integrate multiple commonly used interface protocols (e.g., PCIe 3.0 + USB 3.0) with using only a single PHY design.  This would largely save the product development time (faster TTM), reduce the risk of using multiple different PHY instances (for different protocol needs), and with the configurability to enable different product features/protocols.

Some people might say PCIe 3.0 era has gone. I was not quite yet being convinced as I still see its potential to shine a lot of market use cases. What do you think?

More Information

For more information on Cadence's PCIe IP offerings, see our PCI Express page.

For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website.

Related Posts

• Blog: PCIe Gen4: It’s Official, We’re Compliant
• Blog: The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016
• Blog: Cadence PCIe Solutions: Configurable, Compliant, and Low Power

USB4 can simultaneously tunnel USB3, PCIe and DisplayPort native protocol traffic through a hierarchy of USB4 routers. The key to tunneling of these protocols is routing table programmed at each ingress adapter. An entry of a routing table maps an incoming HopID, called Input/Ingress HopID to a corresponding pair of Output/Egress Adapter and Egress/Output HopID.

The responsibility of programming routing tables lies with the Connection Manager. Connection Manager, having the complete view of the hierarchy of the routers, programs the routing tables at all relevant adapter ports. Accordingly, the USB3, PCIe and DisplayPort protocol tunneled packets are routed, and reach their respective intended destinations.

The diagrammatic representation below is an example of tunneling of USB3 protocol traffic from USB4 Host Router to USB4 Peripheral Device Router through a USB4 Hub Router. The path from USB3 Host to USB3 Device is depicted by routing tables indicated at A -> B -> C -> D, and the one from USB3 Device to USB3 Host by routing tables indicated at E -> F -> G -> H . Note that the Input HopID from and Output HopID to all three protocol adapters for USB3, PCIe and DisplayPort Aux traffic, are fixed as 8, and for DisplayPort Main Link traffic are fixed as 9.

Once the native protocol traffic come into the transport layer of a USB4 router, the transport layer of it does not know to which native protocol a tunneled packet belongs to. The only way a transport layer tunneled packet is routed through the hierarchy of the routers is using the HopID values and the information programmed in the routing tables.

The figure below shows an example of tunneling of all the three USB3, PCIe and DisplayPort protocol traffic together. The transport layer tunneled packets of each of these native protocols are transported simultaneously through the routers hierarchy.

 Cadence has a mature Verification IP solution for the verification of USB3, PCIe and DisplayPort tunneling. This solution also employs the industry proven VIPs of each of these native protocols for native USB3, PCIe and DisplayPort traffic.

Once while eating dinner in Montreal, our friendly, intoxicated waitress plopped herself in my lap and proceeded to tell us about how obsessed she was with the CD that was playing - singing out the lyrics at an ungodly volume and flinging her arms about. Wow, I thought to myself, people who listen to Morcheeba sure seem to have a lot of fun, and promised to check them out.

Several CDs later, they are firmly one of my favorites. And their trip hop meditation, 2003’s Charango remains one of my most played CDs.

Morcheeba (Mor = more, Cheeba = pot) are brothers Ross and Paul Godfrey with singer Skye Edwards (who has since been replaced). Part trance, part ambience, Charango is full of smooth, snogworthy jams. And just as you surrender to its seductive groove, Slick Rick shows up with a rap called “Women Lose Weight”.

Lamenting his wife putting on weight after having kids and stalled by his mistress who wants a clean break before she shacks up with him, he decides the easiest way out of it all is to kill the spouse. Considering different ways to do the deed, he finally rams his car into her Chevy over a long lunch break one fine day. It is an unexpected, stunning, tongue-in-cheek social commentary that makes it a CD you won’t forget easily.

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A couple of evenings ago, my cousin Debika and I were discussing how we’d react if we were told we had just a few months to live. She said she would try and do everything she liked in that time, and surround herself with her family. I said that I’d be inclined to save people I cared for the pain of watching me die—whatever that took. Ironically and unexpectedly, shortly after this conversation, we found ourselves watching François Ozon’s remarkable film Time to Leave.

The film begins with its protagonist, Romain, discovering that he is terminally ill with cancer, and deciding not to bother with treatment. He does not tell his friends or family of his condition. He is rude to his sister, and drives her to tears. He tells his lover, Sasha, that he does not love him, and drives him to move out of their house. This is a transparent lie, but though we see it, Sasha doesn’t. He confides to his grandmother—marvellously played by Jeanne Moreau—because she is like him, and “will die soon.” But even in this winding up, complications ensue.

Melvil Poupaud plays Romain, and is magnificent – understated, yet effortlessly expressive. But it is Ozon’s storytelling that makes this film memorable. It is spare, focussing only on the essential, and revealing its essence. There is not a frame out of place in this heartbreaking film that ends, like Romain, too soon and in great beauty.

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I’m coming to the party late—last weekend, for the first but not the last time, I watched Manish Acharya’s comedy, Loins of Punjab Presents. Behan____, what a film! 

I will not rehearse the synopsis or plot, partly because of the lateness of the hour, but also because it is available here. Instead, let me note quickly that the comedy keeps ticking, and the attention to detail in all matters, from the plot to the casting, makes this film a pleasure to watch.

Let me use one scene to make a point about where the film is coming from. Ishitta Sharma, playing a demure, Gujju girl called Preeti Patel, is one of the competitors in the Desi Idol competition in New Jersey. We have watched her sing beautifully, and we have watched her stay silent, eyes downcast, as her family-members make fools of themselves. But there’s a moment later in the film, when an older, wily competitor, played with classy ease by Shabana Azmi, tries to manipulate her. And suddenly, in the blink of an eye, Preeti Patel turns upon the Shabana character. It’s as if she always had a dagger hiding in her hand.

When I saw that, I thought that there was a similar strength in the movie I was watching. It’s all laughs but it has a quicksilver intelligence within. It is a declaration of independence by the desi diaspora—and what is great is that it celebrates this freedom by mocking, and loving, almost everything in sight.

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Pablo Bartholomew’s beautiful photo-show “Outside In” opened in Manhattan a few evenings ago. The exhibition is being held at Bodhi Art in Chelsea. Black-and-white photographs from the seventies and the eighties—reflecting Bartholomew’s engagement with people and places in Delhi, Bombay, and Calcutta.

These are not the pictures that made Bartholomew famous. The undying image of the father brushing the dust from the face of the child he is burying—that was the iconic photograph from the Bhopal tragedy in 1984. It also won for Bartholomew, still in his twenties, the World Press Photo’s Picture of the Year Award.

The images in “Outside In” do not commemorate grim tragedies or celebrate well-publicised public events. Instead, they are documents that offer intimate recall of a period and a milieu. Please click here to look at these photographs.

People who share a context with the photographer will have their own private reading of the scenes. For me, they evoke days when happiness seemed only one chai and a Wills Navy Cut away. There is charm and candor in these scenes. And because the young believe they will live forever, there is nothing defensive or stuck-up or overly self-conscious about their faces and postures.

Even the language of the captions is true to this spirit: “Self-portrait after a trippy night…”; “Nona writing and Alok zonked out…”; “Hanging out with the Maharani Bagh gang….” The exhibition catalogue has a fine essay by Aveek Sen that has also been published in the latest issue of Biblio.

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Literate Indians should be familiar with Ashis Nandy’s remark: “Cricket is an Indian game accidentally discovered by the English.“ A Trinidadian Indian by the name of Chuck Ramkissoon, in Joseph O’Neill’s superbly inflected novel “Netherland”, is also fond of making bold pronouncements on the behalf of the game he wants to introduce to the U.S. “I’m saying that people, all people, Americans, whoever, are at their most civilized when they’re playing cricket. What’s the first thing that happens when Pakistan and India make peace? They play a cricket match…”

It’s now my turn to be bold: “Netherland” is more of an Indian novel than the recent, much feted, Indian fiction. This is not only because O’Neill’s novel feeds our national obsession with the game. Nor even its exquisite description of what transpires on the playing field: “…. where the white-clad ring of infielders, swanning figures on the vast oval, again and again converge in unison toward the batsman and again and again scatter back to their starting points, a repetition of pulmonary rhythm, as if the field breathed through its luminous visitors.” No. My pronouncement is based on the fact that the Indian characters in the book are highly individualized and yet fully global in their identity. “Netherland” is not a sociological-historical epic thesis, nor is it a shallow, cynical report on injustice in the hinterland. Rich in observation, reporting as much on the interior life as on the life outside, it is a captivating literary achievement. A masterpiece.

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I loved Nina Paley’s brilliant animated film Sita Sings the Blues. If you’re reading this, stop right now—and watch the film here.

Paley has set the story of the Ramayana to the 1920s jazz vocals of Annette Hanshaw. The epic tale is interwoven with Paley’s account of her husband’s move to India from where he dumps her by e-mail. The Ramayana is presented with the tagline: “The Greatest Break-Up Story Ever Told.”

All of this should make us curious. But there are other reasons for admiring this film:

The film returns us to the message that is made clear by every village-performance of the Ramlila: the epics are for everyone. Also, there is no authoritative narration of an epic. This film is aided by three shadow puppets who, drawing upon memory and unabashedly incomplete knowledge, boldly go where only pundits and philosophers have gone before. The result is a rendition of the epic that is gloriously a part of the everyday.

This idea is taken even further. Paley says that the work came from a shared culture, and it is to a shared culture that it must return: she has put the film on Creative Commons—viewers are invited to distribute, copy, remix the film.

Of course, such art drives the purists and fundamentalists crazy. On the Channel 13 website, “Durgadevi” and “Shridhar” rant about the evil done to Hinduism. It is as if Paley had lit her tail (tale!) and set our houses on fire!

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Sample clues

5 across: The US president’s bird (3,5,3)

11 down: Group once known as the Quarrymen (7)

10 across: Cavalry sword (5)

19 across: Masonic ritual (5,6)

1 down: Pioneer of Ostpolitik (6)

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