IDA activities in July included an endorsement from X-Fab for EMX as well as multiple multiphysics blog posts spanning SI, PI, thermal, EM and microwave analysis domains.(read more)

Microwaves & RF's David Maliniak interviews Sherry Hess of Cadence about recently announced products of Optimality and OnCloud.(read more)

IDA activities in August showcased two video interviews with David Maliniak of Microwaves & RF magazine. New posts, datasheets, application notes and white papers highlight multiphysics analysis spanning SI, PI, thermal, EM and microwave analysis domains are also featured.(read more)

Hi *,

I am simulating a 32kHz high Q crystal oscillator with a pulse shaping circuit. I set up a PSS analysis using the Shooting Newton engine. I set a beat frequency of 32k and used the crystal output and ground as reference nodes. After the initial transient the amplitude growth was already pretty much settled such that the shooting iterations could continue the job.

My problem is: In 5...10% of my PVT runs the simulator detects a frequency divider in the initial transient simulation. The output log says:

Frequency divided by 3 at node <xxx>

The Estimated oscillating frequency from Tstab Tran is = 11.0193 kHz .

However, the mentioned node is only part of the control logic and is always constant (but it has some ripples and glitches which are all less than 30uV). These glitches spoil my fundamental frequency (11kHz instead of 32kHz). Sometimes the simulator detects a frequency division by 2 or 3 and the mentioned node <xxx> is different depending on PVT - but the node is always a genuine high or low signal inside my control logic.

How can I tell the simulator that there is no frequency divider and it should only observe the given node pair in the PSS analysis setup to estimate the fundamental frequency? I have tried the following workarounds but none of them worked reliably:

- extended/reduced the initial transient simulation time

- decreased accuracy

- preset override with Euler integration method for the initial transient to damp glitches

- tried different initial conditions

- specified various oscillator nodes in the analysis setup form

By the way, I am using Spectre X (version 21.1.0.389.ISR8) with CX accuracy.

Thanks for your support and best regards

Stephan

Hi

I have fixed a SPACING RULE (SP1) for a CLASS_DIFF_PAIR whereas for via associated to the net (DP_VIA), the DISTANCE > 60mils respect to ANY other vias (PTH, BB, TEST vias)

Now my problem is that this rules should NOT be applied for GND VIAS (STICHING VIA) which must be placed at a distance < 40mils respect to DP_VIA

How to create an exemption to the SPACING RULE (SP1)?

A more appropriate title for this blog could be “All Vehicles with ADAS Need the Midas Functional Safety Platform”.

EVs tend to have advanced driving assistance systems (ADAS) because they’re newer, but not all vehicles with ADAS are EVs!

Certifying Advanced Driver Assistance Systems (ADAS) is a multifaceted process involving rigorous testing, validation, and regulatory compliance to ensure safety and reliability.
As ADAS technologies become increasingly sophisticated, the certification process is evolving to meet these challenges.

The ISO26262 standard provides the requirements to be met to attain safety certification for digital designs.

One of the key aspects of ADAS certification is functional safety. This includes:

• Ensuring the system operates as intended under all conditions, including failures.
• Adherence to standards like ISO26262.
• Rigorous testing to identify potential hazards and mitigate risks.

The Midas Safety Platform provides early-phase exploration of functional safety architectures and leverages native chip design data to perform accurate safety analysis efficiently.

The platform is a unified solution available across Cadence products, and with its modular architecture, it supports both embedded and standalone usage with the Cadence flow.

After extracting the design information, an output Midas database file contains the isolated DUT and provides the design components and their fault tolerances to various tools in the flow.

Conformal can easily verify design transformations that include necessary components like TMR for safety.

In these videos, we explore how to create reports for both Transient and Permanent faults.

Creating Detailed FMEDA in Midas (Video)

Creating Architectural FMEDA in Midas (Video) 

Also, read this blog post for additional motivation: What Is Zonal Architecture? And Why Is it Upending the Automotive Supply Chain?

What Next?

Join the Midas Safety Platform Introduction and the Functional Safety Implementation and Verification with Midas trainings and learn more about:

• Setting up and defining the USF file
• Using the Midas Safety Platform to create functional safety reports, and
• Midas integration with the Genus  Synthesis Solution, Innovus  Implementation System, and Conformal Equivalence Checker tools to implement functional safety

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In this training webinar, we explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow. We will guide you through the essential steps in creating integrated circuits, the building blocks of modern electronics.

We’ll break down the process into manageable stages, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore:

• Key concepts of specifying chip behavior and performance
• How to translate ideas into a digital blueprint and transform that into a design
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This webinar provides practical knowledge, making it your gateway to understanding the magic behind RTL-to-GDSII front-end design flow.

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Date and Time

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The course includes slides with audio and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training.

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

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Cadence RTL-to-GDSII Flow

Xcelium Simulator

Verilog Language and Application

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