Thomas Zunie, a junior from Zuni, NM takes first in the Men's 5000 meter run in a time of 17:21.41.  Zunie's finish in the 5000 garnered him a First Team All-Conference.  Zunie also earned a third place in the 1500 meter run with a time of 4:33.77.   

Last week the weather disrupted the Indians as they opened the Outdoor Season at Pittsburg State University.  Thunderstorms and lightning prevented numerous races and events from running on schedule.  For many, the meet yesterday was their opportunity to finally compete.

Haskell will play host to the 2014 Midlands Collegiate Athletic Conference Outdoor Track and Field Championships on April 25th and 26th. 

Ottawa, Kansas - The Haskell Indian Nations University Men's track and field teams competed at the Ottawa Braves Invitational on Saturday.

The Men's Track & Field team finished their season at Baker Invite on April 29th. Here are some of the athlete's best finishes throughout the season. The Seniors behind the Track & Field program are Isaac Johnson and Stephen Esmond (SR). 

1 Papua New Guinean Kina = 6821.5475 Vietnamese Dong

1 Papua New Guinean Kina = 2.5512 Salvadoran Colon

1 Papua New Guinean Kina = 2874.3171 Sierra Leonean Leone

1 Papua New Guinean Kina = 2.8486 Swedish Krona

1 Papua New Guinean Kina = 1.2982 Romanian Leu

1 Papua New Guinean Kina = 2.9784 Norwegian Krone

1 Papua New Guinean Kina = 16.5657 Macedonian Denar

1 Papua New Guinean Kina = 355.5874 South Korean Won

1 Papua New Guinean Kina = 42.6308 Icelandic Krona

1 Papua New Guinean Kina = 4306.6366 Indonesian Rupiah

1 Papua New Guinean Kina = 7.2967 Honduran Lempira

1 Papua New Guinean Kina = 2.2642 Hong Kong Dollar

1 Papua New Guinean Kina = 4.1577 Estonian Kroon

1 Papua New Guinean Kina = 2.0059 Danish Krone

1 Papua New Guinean Kina = 165.8525 Costa Rican Colon

1 Brunei Dollar = 16557.8167 Vietnamese Dong

1 Brunei Dollar = 6.1925 Salvadoran Colon

1 Brunei Dollar = 6976.7771 Sierra Leonean Leone

1 Brunei Dollar = 6.9144 Swedish Krona

1 Brunei Dollar = 3.1512 Romanian Leu

1 Brunei Dollar = 7.2294 Norwegian Krone

1 Brunei Dollar = 40.2097 Macedonian Denar

1 Brunei Dollar = 863.1108 South Korean Won

1 Brunei Dollar = 103.4771 Icelandic Krona

1 Brunei Dollar = 10453.4198 Indonesian Rupiah

1 Brunei Dollar = 17.7111 Honduran Lempira

1 Brunei Dollar = 5.4958 Hong Kong Dollar

1 Brunei Dollar = 10.0919 Estonian Kroon

1 Brunei Dollar = 4.8688 Danish Krone

1 Brunei Dollar = 402.5707 Costa Rican Colon

With more and more SoCs employing sophisticated interconnect IP to link multiple processor cores, caches, memories, and dozens of other IP functions, the designs are enabling a new generation of low-power servers and high-performance mobile devices. The complexity of the interconnects and their advanced configurability contributes to already formidable design and verification challenges which lead to the following questions:

While your interconnect subsystem might have a correct functionality, are you starving your IP functions of the bandwidth they need? Are requests from latency-critical initiators processed on time? How can you ensure that all applications will receive the desired bandwidth in steady-state and corner use-cases?

To answer these questions, Cadence recommends the Performance Verification Methodology to ensure that the system performance meets requirements at the different levels:

1. Performance characterization: The first level of verification aims to verify the path-to-path traffic measuring the performance envelope. It targets integration bugs like clock frequency, buffer sizes, and bridge configuration. It requires to analyze the latency and bandwidth of design’s critical paths.
2. Steady state workloads: The second level of verification aims to verify the master-by-master defined loads using traffic profiles. It identifies the impact on bandwidth when running multi-master traffic with various Quality-of-Service (QoS) settings. It analyzes the DDR sub-system’s efficiency, measures bandwidth and checks whether masters’ QoS requirements are met.
3. Application specific use cases: The last level of verification simulates the use-cases and reaches the application performance corner cases. It analyzes the master-requested bandwidth as well as the DDR sub-system’s efficiency and bandwidth.

Cadence has developed a set of tools to assist customers in performance validation of their SoCs. Cadence Interconnect Workbench simplifies the setup and measurement of performance and verification testbenches and makes debugging of complex system behaviors a snap. The solution works with Cadence Verification IPs and executes on the Cadence Xcelium® Enterprise Simulator or Cadence Palladium® Accellerator/Emulator, with coverage results collected and analyzed in the Cadence vManager  Metric-Driven Signoff Platform.

To verify the performance of the Steady State Workloads, Arm has just released a new AMBA Adaptive Traffic Profile (ATP) specification which describes AMBA abstract traffic attributes and defines the behavior of the different traffic profiles in the system.

With the availability of Cadence Interconnect Workbench and AMBA VIP support of ATP, early adopters of the AMBA ATP specification can begin working immediately, ensuring compliance with the standard, and achieving the fastest path to SoC performance verification closure.

For more information on the AMBA Adaptive Traffic Profile, you can visit Dimitry's blog on AMBA Adaptive Traffic Profiles: Addressing The Challenge. 

More information on Cadence Interconnect Workbench solution is available at Cadence Interconnect Solution webpage.

Thierry

Verification of a USB4 router design is not just about USB4 but also about the inclusion of the three other major protocols namely, USB3, DisplayPort (DP), and PCI Express (PCIe). These protocols can be simultaneously tunneled through a USB4 router. Put in simple terms, such tunneling involves the conversion of the respective native USB3, DP, or PCIe protocol traffic into the USB4 transport layer packets, which are tunneled through a USB4 fabric, and converted back into the respective original native protocol traffic.

It may sound simple but is perhaps not.

There are several aspects in a router that come into picture to carry out this task of conversion of native protocol traffic, route it to the intended destination, and then convert it back to the original form. Some of those are the USB3, DP and PCIe protocol adapters, transport mechanism using routing, flow control, paths, path set-up and teardown, control and configuration, configuration spaces.

That is not all. There are core USB4 specific logical layer intricacies as well, which carry out the tasks of ensuring that all the USB4 ports and links are working as desired to provide up to 40Gbps speed and that the USB4 traffic flows through out the fabric in the intended way. These bring on the table features like High Speed link, ordered sets, lane initialization, lane adapter state machine, low power, lane bonding, RS-FEC, side band channel, sleep and wake, error checking.

All of these put together give rise to a very large verification space against which a USB4 router design should be verified. If we were to break down this space it can be broadly put in the following major dimensions,

• Protocol Adapter Layer
  • USB3 tunneling
  • DP tunneling
  • PCIe tunneling
• Host Interface Adapter Layer
• Transport Layer
  • Flow control
  • Routing
  • Paths
• Configuration layer and control packet protocol
• Configuration spaces
• Logical Layer

The independent verification of these dimensions is not all that would qualify the design as verified. They have to be verified in various combinations of each other too. Overall, all the parts of a USB4 router system need to be working together coherently.

For example, the following diagram depicts the various layers that a USB4 router may comprise of,

A USB4 router or a domain of routers does not work on its own. There is a Connection Manager per domain, which is a software-based entity managing a domain. A router provides the various capabilities for a Connection Manager to carry out its responsibilities of managing a domain.

It would not be an exaggeration to say that the spectrum of verification of a USB4 router ranges from the very minute details of logical layer to the system-level like multiple dependencies as the whole USB4 system is brought up layer by layer, step-by-step.

Cadence has a mature Verification IP solution that can help in the verification of USB4 designs. Cadence has taken an active part in the working group that defined the USB4 specification and has created a comprehensive Verification IP that is being used by multiple members in the last two years.

If you plan to have a USB4 compatible design, you can reduce the risk of adopting a new technology by using our proven and mature USB4 Verification IP. Please contact your Cadence local account team for more details and to get connected.

PCI-SIG DevCon 2019 APAC tour has come to Tokyo and Taipei this year. The focus is predominantly around the latest updates for PCIe Gen 5 which its version 1.0 specification was just released this year in May.  A series of presentations provided by PCI-SIG on the day 1 with comprehensive information covering all aspects of Gen 5 specification, including protocol, logical, electrical, compliance updates. On the day 2 (only in Taipei), several member companies shared their view on Testing, PCB analysis and Signal integrity. The exhibit is also another spotlight of this event where the member companies showcased their latest PCIe solutions.

Presentation Track (Taipei), Exhibit (Tokyo), Exhibit (Taipei) 

Cadence, as the market leading PCIe IP vendor, participated APAC tour this year with bringing in its latest PCIe IP solution offering (Gen 5/4) to the region as well as showcasing two live demo setups in the exhibit floor. One setup is the PCIe software development kit (SDK) while the other is the Interop/compliance/debug platform. Both come with the Cadence PCIe Gen 4 hardware setup and its corresponding software kit.

The SDK can be used for Device Driver Development, Firmware Development, and for pre-silicon emulation as well. It supports Xtensa and ARM processor with Linux OS and it also equip with Ethernet interface which can be used for remote debugging. It also supports PCIe stress tests for Speed change, link enable/disable, entry/exist for lower power states, …etc. 

Cadence PCIe 4.0 Software Development Kit

The “System Interop/Compliance/Debug platform” was set up to test with multiple endpoint and System platforms. This system come with integrated Cadence software for basic system debug without the need for analyzer to perform the analysis, such as LTSSM History, TS1/TS2 transmitted/received with time stamp, Link training phases, Capturing Packet errors details, Capturing PHY TX/RX internal state machine details, ...etc.

Cadence PCIe System Interop/Compliance/Debug Platform

The year 2019 is certainly a "fruitful year" for the PCIe as more Gen 4 products are now available in the market, Gen 5 v1.0 specification got officially ratified, and PCI-SIG's revealing of Gen 6 specification development. We were glad to be part of this APAC tour with the chance to further introduce Cadence’s complete and comprehensive PCIe IP solution.

See you all next year in APAC again!

More Information

For more information on Cadence's PCIe IP offerings, see our PCI Express page.

For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website.

Related Posts

• Blog: Did You “Stress Test” Yet? Essential Step to Ensure a Quality PCIe 4.0 Product
• Blog: PCIe Gen4: It’s Official, We’re Compliant
• Blog: PCIe 3.0 Still Shines While PCIe Keeps Evolving
• Blog: The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016

Verifying lane adapter state machine in a router design is quite an involved task and needs verification from several aspects including that for its link training functionality.

The diagram below shows two lane adapters connected to each other and each going through the link training process. Each training sub-state transition is contingent on conditions for both transmission and reception of relevant ordered sets needed for a transition. Until conditions for both are satisfied an adapter cannot transition to the next training sub-state.

As deduced from the lane adapter state machine section of USB4 specification, the reception condition for the next training sub-state transition is less strict than that of the transmission condition. For ex., for LOCK1 to LOCK2 transition, the reception condition requires only two SLOS symbols in a row being detected, while the transmission condition requires at least four complete SLOS1 ordered sets to be sent.

From the above conditions in the specification, it is a possibility that a lane adapter A may detect the two SLOS or TS ordered sets, being sent by the lane adapter B on the other end, in the very beginning as soon as it starts transmitting its own SLOS or TS ordered sets. On the other hand, it is also a possibility that these SLOS or TS ordered sets are not yet detected by lane adapter A even when it has met the condition of sending minimum number of SLOS or TS ordered sets.

In such a case, lane adapter A, even though it has satisfied the transmission condition cannot transition to the next sub-state because the reception condition is not yet met. Hence lane adapter A must first wait for the required number of ordered sets to be detected by it before it can go to the next sub-state. But this wait cannot be endless as there are timeouts defined in the specification, after which the training process may be re-attempted.

This interlocked way of operation also ensures that state machine of a lane adapter does not go out of sync with that of the other lane adapter. Such type of scenarios can occur whenever lane adapter state machine transitions to the training state from other states.

Cadence has a mature Verification IP solution for the verification of various aspects of the logical layer of a USB4 router design, with verification capabilities provided to do a comprehensive verification of it.

Pablo Bartholomew’s beautiful photo-show “Outside In” opened in Manhattan a few evenings ago. The exhibition is being held at Bodhi Art in Chelsea. Black-and-white photographs from the seventies and the eighties—reflecting Bartholomew’s engagement with people and places in Delhi, Bombay, and Calcutta.

These are not the pictures that made Bartholomew famous. The undying image of the father brushing the dust from the face of the child he is burying—that was the iconic photograph from the Bhopal tragedy in 1984. It also won for Bartholomew, still in his twenties, the World Press Photo’s Picture of the Year Award.

The images in “Outside In” do not commemorate grim tragedies or celebrate well-publicised public events. Instead, they are documents that offer intimate recall of a period and a milieu. Please click here to look at these photographs.

People who share a context with the photographer will have their own private reading of the scenes. For me, they evoke days when happiness seemed only one chai and a Wills Navy Cut away. There is charm and candor in these scenes. And because the young believe they will live forever, there is nothing defensive or stuck-up or overly self-conscious about their faces and postures.

Even the language of the captions is true to this spirit: “Self-portrait after a trippy night…”; “Nona writing and Alok zonked out…”; “Hanging out with the Maharani Bagh gang….” The exhibition catalogue has a fine essay by Aveek Sen that has also been published in the latest issue of Biblio.

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