If I talk about my life, it was much simpler when I used to live with my parents. They took good care of whatever I wanted - in fact, they still do. But now, I am living alone, and sometimes I buy...

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Complexity is driving the urgency for advanced artificial intelligence systems more than ever—and that means someone has to supply the tools to create those systems. Cadence is up to the task: we’ve been expanding our AI offerings. If you haven’t already seen what Cadence can do for your AI needs, or if you’re not quite up-to-date on this whole AI boom, let this presentation given by K.T. Moore at the Cadence Theater at DAC bring you up to speed.

The technology behind AI isn’t as new as you’d think—the principles that govern how AI learns have been in development since 1959, when Arthur Samuel defined the concept of “machine learning.” At the time, there was nothing even resembling the necessary compute power to put Samuel’s concepts into practice—but now we can. AI designs are huge, and they’re massively parallel—simulating them on older computers and simulators would have taken ages; never mind how long it would take to do some by-hand measure like they had to do in the '60s.

But with advancements in server technology and the parallelization technology in products like Xcelium Parallel Logic Simulator and JasperGold smart technology, plus hardware-based engines like the Palladium and Protium platforms, verifying AI designs is not only possible—it’s easy.  But, read on, its not just about simulation technology.

AI tech is flooding the industry. It’s applicable to almost every vertical—cloud computing can use AI to intelligently manage a user’s required resources, consumer electronics are using it to tailor a user experience based on a whole host of collected data, automotive companies want to use AI to drive cars, healthcare to assist in diagnoses given a set of symptoms and a database of other, similar patients—and that’s saying nothing of the multitude of industrial applications. AI is also useful in the creation of developers’ tools themselves. Part of what’s causing the semiconductor industry boom is just this—an exploding interest in AI chips. And with 5G technology imminent, and with the looming billion-gate plus sizes of the SoCs that implement 5G, AI-assisted developers' tools might need to become the norm, not an outlier.

So: in all of this, where is Cadence?

Cadence is focusing its efforts on two areas, dubbed “machine learning inside” and “machine learning outside.” ML inside in the digital design flow refers to improving PPA, faster engines, and better testing and diagnostics. None of this physically affects how you use a tool, but it makes using that tool a much better experience. ML outside talks about the design flow in general, working toward an automated design flow, as well as productivity improvements across the flow. These things do change how you use a tool, but don’t worry, it’s all for the better.

Additionally, Cadence is working to improve design enablement; that is, hardware and software co-design. Smart Genus and Innovus solutions make designing your SoC easier than ever—using the full flow can result in up to a 21% PPA gain.

If you’re looking specifically for IP to enable AI on your SoC, the Tensilica DNA 100 processor has you covered, too. It’s great for companies designing edge or AI chips, offers great compression rates and efficient power usage, and has 4.7X the performance of other AI SoC IP on similar array sizes.

Cadence has you covered no matter where you’re going in this new world of AI systems—with our AI-enabled tools, IP,  and our strong partner ecosystem, you can be at ease knowing you’ll be supported no matter how complex your needs are.

Everyone keeps talking about “the cloud” this and “the cloud” that these days—but you’re a semiconductor designer. Everyone keeps saying “the cloud” is revolutionizing all aspects of electronics design—but what does it mean for you? Cadence's own Tom Hackett discussed this in a presentation at the Cadence Theater during DAC 2019.

What people refer to as “the cloud” is commonly divided into three categories: Infrastructure as a Service (IaaS), Platform as a Service (PaaS), and software as a Service (SaaS). With IaaS, you bring your own software—i.e. loading your owned or appropriately licensed tools onto cloud hardware that you rent by the minute. This service is available from providers like Google Cloud Platform, Amazon Web Service, and Microsoft Azure. In PaaS (also available from the major cloud providers), you create your own offering using capabilities and a software design environment provided by the cloud vendor that makes subsequent scaling and distribution really easy because the service was “born in the cloud”.  Lastly, there’s SaaS, where the cloud is used to access and manage functionality and data without requiring users to set up or manage any of the underlying infrastructure used to provide it.  SaaS companies like Workday and Salesforce deliver their value in this manner.  The Cadence Cloud portfolio makes use of both IaaS and SaaS, depending on the customers’ interest.  Cadence doesn’t have PaaS offerings because our customers don’t create their own EDA software from building blocks that Cadence provides.

All of these designations are great, but you’re a semiconductor designer. Presumably you use Workday or some similar software, or have in the past when you were an intern, but what about all of your tools? Those aren’t on the cloud.

Wait—actually, they are.

Using EDA tools in the cloud allows you to address complexity and data explosion issues you would have to simply struggle through before. Since you don’t have to worry about having the compute-power on-site, you can use way more power than you could before. You may be wary about this new generation of cloud-based tools, but don’t worry: the old rules of cloud computing no longer apply. Cloud capacity is far larger than it used to be, and it’s more secure. Updates to scheduling software means that resource competition isn’t as big of a deal anymore. Clouds today have nearly unlimited capacity—they’re so large that you don’t ever need to worry about running out of space.

The vast increase in raw compute available to designers through the cloud makes something like automotive functional safety verification, previously an extremely long verification task, doable in a reasonable time frame. With the cloud, it’s easy to scale the amount of compute you’re using to fit your task—whether it’s an automotive functional safety-related design or a small one.

Nowadays, the Cadence Cloud Portfolio brings you the best and brightest in cloud technology. No matter what your use case is, the Cadence Cloud Portfolio has a solution that works for you. You can even access the Palladium Cloud, allowing you to try out the benefits of an accelerator without having to buy one.

Cloud computing is the future of EDA. See the future here.

In the former blog about Python and Specman: Specman: Python Is here!, we described the technical information around Specman-Python integration. Since Python provides so many easy to use existing libraries in various fields, it is very tempting to leverage these cool Python apps.

Coverage has always been the center of the verification methodology, however in the last few years it gets even more focus as people develop advanced utilities, usually using Machine Learning aids. Anyhow, any attempt to leverage your coverage usually starts with some analysis of the behavior and trends of some typical tests. Visualizing the data makes it easier to understand, analyze, and communicate. Fortunately, Python has many Visualization libraries.

In this blog, we show an example of how you can use the plotting Python library (matplotlib) to easily display coverage information during a run. In this blog, we use the Specman Coverage API to extract coverage data, and a Python module to display coverage grades interactively during a single run and the way to connect both.

Before we look at the example, if you have read the former blog about Specman and Python and were concerned about the fact that python3 is not supported, we are glad to update that in Specman 19.09, Python3 is now supported (in addition to Python2).

The Testcase
Let’s say I have a stable verification environment and I want to make it more efficient. For example: I want to check whether I can make the tests shorter while hardly harming the coverage. I am not sure exactly how to attack this task, so a good place to start is to visually analyze the behavior of the coverage on some typical test I chose. The first thing we need to do is to extract the coverage information of the interesting entities. This can be done using the old Coverage API. 

Coverage API
Coverage API is a simple interface to extract coverage information at a certain point. It is implemented through a predefined struct type named user_cover_struct. To use it, you need to do the following:

1. Define a child of user_cover_structusing like inheritance (my_cover_struct below).
2. Extend its relevant methods (in our example we extend only the end_group() method) and access the relevant members (you can read about the other available methods and members in cdnshelp).
3. Create an instance of the user_cover_structchild and call the predefined scan_cover() method whenever you want to query the data (even in every cycle). Calling this method will result in calling the methods you extended in step 2.  

 The code example below demonstrates these three steps. We chose to extend the end_group() method and we keep the group grade in some local variable. Note that we divide it by 100,000,000 to get a number between 0 to 1 since the grade in this API is an integer from 0 to 100,000,000. 

Pass the Data to a Python Module
After we have extracted the group grade, we need to pass the grade along with the cycle and the coverage group name (assuming there are a few) to a Python module. We will take a look at the Python module itself later. For now, we will first take a look at how to pass the information from the e code to Python. Note that in addition to passing the grade at certain points (addVal method), we need an initialization method (init_plot) with the number of cycles, so that the X axis can be drawn at the beginning, and end_plot() to mark interesting points on the plot at the end. But to begin with, let’s have empty methods on the Python side and make sure we can just call them from the e code.

 # plot_i.py
def init_plot(numCycles):
    print (numCycles)
def addVal(groupName,cycle,grade):
    print (groupName,cycle,grade)
def end_plot():
    print ("end_plot") 

And add the calls from e code:

 Before running this, note that you need to ensure that Specman finds the Python include and lib directories, and Python finds our Python module. To do this, you need to define a few environment variables: SPECMAN_PYTHON_INCLUDE_DIR, SPECMAN_PYTHON_LIB_DIR, and PYTHONPATH. 

 The Python Module to Draw the Plot
After we extracted the coverage information and ensured that we can pass it to a Python module, we need to display this data in the Python module. There are many code examples out there for drawing a graph with Python, especially with matplotlib. You can either accumulate the data and draw a graph at the end of the run or draw a graph interactively during the run itself- which is very useful especially for long runs.

Below is a code that draws the coverage grade of multiple groups interactively during the run and at the end of the run it prints circles around the maximum point and adds some text to it. I am new to Python so there might be better or simpler ways to do so, but it does the work. The cool thing is that there are so many examples to rely on that you can produce this kind of code very fast.

 In the example we used, we had two interesting entities: packet and state_machine, thus we had two equivalent coverage groups. When running our example connecting to the Python module, we get the following graph which is displayed interactively during the run.

When analyzing this specific example, we can see two things. First, packet gets to a high coverage quite fast and significant part of the run does not contribute to its coverage. On the other hand, something interesting happens relating to state_machine around cycle 700 which suddenly boosts its coverage. The next step would be to try to dump graphic information relating to other entities and see if something noticeable happens around cycle 700.

To run a complete example, you can download the files from: https://github.com/okirsh/Specman-Python/

Do you feel like analyzing the coverage behavior in your environment? We will be happy to hear about your outcomes and other usages of the Python interface.

Orit Kirshenberg
Specman team

We're happy to have guest blogger Thorsten Dworzak, Principal Consultant at Verilab GmbH, describe how he added Specman/e syntax to Sublime Text 3:

According to the 2018 StackOverflow Developer Survey, the popularity of development environments (IDEs, Text Editors) among software developers shows the following ranking:

1. Visual Studio Code 34.9%
2. Visual Studio 34.3%
3. Notepad++ 34.2%
4. Sublime Text 28.9%
5. Vim 25.8%
6. IntelliJ 24.9%
7. Android Studio 19.3%
8. (DVT) Eclipse 18.9%
9. …

15. Emacs 4.1%

Of these, only Vim, (DVT) Eclipse, and Emacs support editing in e-language (at least, last time I checked). Kate, which comes with KDE and also has a Specman mode, is not on this list.

I started using Sublime Text 3 some time ago. It offers packages that support a number of programming languages.

Though there is an e-language syntax available from Tsvi Mostovicz, it is unfinished work, and there are many syntactic constructs are missing. So, I created a fork of his project and finished it (it will eventually be merged back here).

It is a never-ending task because my code base for testing is limited and e is still undergoing development. The project is available through ST3's Package Control and you can contribute to it via Github.

I am eagerly waiting for your pull requests and/or comments and contributions!

Our customers’ tests have become more complex, longer, and consume more resources than before. This increases the need to optimize the regression while not compromising on coverage.

Some advanced customers of Specman use Machine Learning based solutions to optimize the regressions while some use simpler solutions. Based on a request of an advanced customer, we added a new Coverage API in Specman 19.09 called Coverage Callback. In 20.03, we have further enhanced this API by adding more options. Now there are two Coverage APIs that provide coverage information during the run (the old scan_cover API and this new Callback API). This blog presents these two APIs and compares between them while focusing on the newer one.

Before we get into the specifics of each API, let’s discuss what is common between these APIs and why we need them. Typically, people observe the coverage model after the test ends, and get to know the overall contribution of the test to the coverage. With these two APIs, you can observe the coverage model during the test, and hence, get more insight into the test progress.

Are you wondering about what you can do with this information? Let’s look at some examples.

1. Recognize cases when the test continues to run long after it already reached its coverage goal.
2. View the performance of the coverage curve. If a test is “stuck” at the same grade for a long time, this might indicate that the test is not very good and is just a waste of resource.

These analyses can be performed in the test itself, and then a test can decide to either stop the run, or change something in it configuration, or – post run. You can also present them visually for some analysis, as shown in the blog: Analyze Your Coverage with Python.

scan_cover API (or “Scanning the Coverage Model”)

With this API you can get the current status for any cover group or item you are interested in at any point in time during the test (by calling scan_cover()). It is very simple to use; however it has performance penalty. For getting the coverage grade of any cover group during the test, you should
1. Trigger the scan_cover at any time when you want the coverage model to be scanned.
2. Implement the scan_cover related methods, such as start_item() and end_bucket(). In these methods, you can query the current grade of group/item/bucket.
The blog mentioned earlier: Analyze Your Coverage with Python describes the details and provides an example.

Callback API

The Callback API enables you to get a callback for a desired cover group(s), whenever it is sampled. This API also provides various query methods for getting coverage related information such as what the current sampled value is. So, in essence, it is similar to scan_cover API, but as the phrase says: “same same but different”:

1. Callback API has almost no performance penalty while scan_cover API does.
2. Callback API contains a richer set of query methods that provide a lot of information about the current sampled value (vs just the grade with scan_cover).
3. Using scan_cover API, you decide when you want to query the coverage information (you call scan_cover), while with the Callback API you query the coverage information when the coverage is sampled (from do_callback). So, scan_cover gives you more flexibility, but you do need to find the right timing for this call.

There is no absolute advantage of either of these APIs, this only depends on what you want to do.  

Callback API details

The Callback API is based on a predefined struct called: cover_sampling_callback. In order to use this API, you need to:

1. Define a struct inheriting cover_sampling_callback (cover_cb_save_data below)
   1. Extend the predefined do_callback() method. This method is a hook being called whenever any of the cover groups that are registered to the cover_sampling_callback instance is being sampled.
   2. From do_callback() you can access coverage data by using queries such as: is_currently_per_type(), get_current_group_grade() and get_current_cover_group() (as in the example below) and many more such as: get_relevant_group_layers() and get_simple_cross_sampled_bucket_name().
2. Register the desired cover group(s) to this struct instance using the register() method.

Take a look at the following code:

// Define a coverage callback.
// Its behavior – print to screen the current grade.
struct cover_cb_save_data like cover_sampling_callback {
    do_callback() is only {
       // In this example, we care only about the per_type grade, and not per_instance
       if is_currently_per_type() {           
            var cur_grade : real = get_current_group_grade();
            sys.save_data (get_current_cover_group().get_name(), cur_grade);
        };//if
    };//do_callback()
};// cover_cb_send_data


extend sys {
    !cb : cover_cb_save_data;

   // Instantiate the coverage callback, and register to it two of my coverage groups
    run() is also {
       cb  = new  with {
        var gr1:=rf_manager.get_struct_by_name("packet").get_cover_group("packet_cover");
        .register(gr1);
        var gr2:=rf_manager.get_struct_by_name("sys").get_cover_group("mem_cover");
       .register(gr2);
       };//new  
    };//run()

  save_data(group_name : string, group_grade : real) is {
        //here you either print the values to the screen, update a graph you show or save to a db 
  };// save_data
};//sys

In the blog Analyze Your Coverage with Python mentioned above, we show an example of how you can use the scan_cover API to extract coverage information during the run, and then use the Specman-Python API to display the coverage interactively during the run (using plotting Python library - matplotlib). If you find this usage interesting and you want to use the same example, by the Callback API instead of the scan_cover API, you can download the full example from GIT from here: https://github.com/efratcdn/cover_callback.

Specman Team

All PCB designers know the importance of proper power delivery for successful board design. Integrated circuits need the power to turn on, and ICs with marginal power delivery will not operate reliably. Since power planes can...(read more)

What is a Power Distribution Network (PDN) after all but resistance, inductance, and capacitance in the PCB and components? And, of course, it is there to deliver the right current and voltage to each component on your PCB. But is that all? Are there oth...(read more)

Have you ever manufactured a printed circuit board (PCB) without analyzing all the routed signal traces? Most designers will say “yes, all the time.” Trace widths and spacing are set by constraints, and many designers simply don’t h...(read more)

So, what if you can figure out all that can go wrong when your product is being assembled early on? Not guess but know and correct at an early stage – not wait for the fabricator or manufacturer to send you a long report of what needs to change. That’s why Design for Assembly (DFA) rules(read more)

On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release.  Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release.

When we talk about low-power verification its easy to equate it with simulation.  For certain, simulation is the heart of a low-power verification solution. Simulation enables engineers to run their design in the context of power intent.  The challenge is that a simulation-only approach is inadequate. For example, if engineers could achieve SoC quality by verifying the individual function of each power control module (PCM), then simulation could be enough.  For a single power domain, simulation can be enough. 

However, when the SoC has multiple power domains -- and we have seen SoCs with hundreds of them -- engineers have to check the PCMs and all of the arcs between the power modes.  These SoCs often synchronize some of the domain switching to reduce overall complexity, creating the potential for signal skew errors on the control signals for the connected domains.  Managing these complexities requires verification methodologies including advanced debug, verification planning, assertion-based verification, Universal Verification Methodology - Low Power (UVM-LP), and more (see Figure 1).

Figure 1:  Comprehensive Low-Power Verification 

But even advanced verification methodologies on top of simulation aren't enough.  For example, the state machine that defines the legal and illegal power mode transitions is often written in software. The speed and capacity of the Palladium emulation platform is ideal to verify in this context, and it is integrated with simulation sharing debug, UVM acceleration, and static checks for low-power. And, it reports verification progress into a holistic plan for the SoC.  Another example is the ability to compare the design in the implementation flow with the design running in simulation to make sure that what we verify is what we intend to build.

Taken together, verification across multiple engines provides the comprehensive low-power verification needed for today's advanced node SoCs.  That's the heart of this low-power verification announcement. 

Another point you may have noticed is the extension of the Common Power Format (CPF) based power-aware support in the Incisive Enterprise Simulator to IEEE 1801.  We chose to bring IEEE 1801 to simulation first because users like you sometimes need to mix vendors for regression flows.  Over time, Cadence will extend the low-power capabilities throughout its product suite to IEEE 1801.

If you are using CPF today, you already have the best low-power solution. The evidence is clear:  the upcoming IEEE 1801-2013 update includes many of the CPF features contributed to 1801/UPF to enable methodology convergence.  Since you already have those features in the CPF flow, any migration before you have a mature IEEE 1801-2013 tool flow would reduce the functionality you have today.

If you are using Unified Power Format (UPF) 1.0 today, you want to start planning your move toward the IEEE 1801-2013 standard.  A good first step would be to move to the IEEE 1801-2009 standard.  It fills holes in the earlier UPF 1.0 definition.  While it does lack key features in -2013, it is an improvement that will make the migration to -2013 easier. The Incisive 13.1 release will run both UPF 1.0 and IEEE 1801-2009 power intent today.

Over the next few weeks you'll see more technical blogs about the low-power capabilities coming in the Incisive 13.1 release.  You can also join us on June 19 for a webinar that will introduce those capabilities using the reference design supplied with the Incisive Enterprise Simulator release.

=Adam "The Jouler" Sherer

(Yes, "Sherilog" is still here.  :-) )

The IEEE has announced the publication of the new 1801-2013 standard, also known as UPF 2.1, and immediate availability for free download through the IEEE 1801-2013 Get Program. Even though the standard is new to the whole world, for the people of the IEEE working group this standard is finally done and is in the past now.

There is a Chinese saying "好事多磨" which means "good things take time to happen." I forgot the exact time when I first joined the working group for the new standard -- about two and half years ago -- but I do remember long hours of meetings and many "lively" debates and discussions. Since the "hard time" has passed us, I would like to share some fun facts about the working group and the standard.

• The 1801 working group is the largest entity based ballot group in IEEE-SA history.
• The new standard was initially planned for 2012, but was delayed purely due to the large amount of work required.
• At one point, the group was debating on whether the new standard should be called UPF 2.1 or 3.0. It may sound weird now but we spent quite some time discussing this. Eventually we settled on 2.1 as it was the original plan.
• The 1801-2013 document has 358 pages which is 53% thicker than previous version (the sheer amount of changes in the new standard indicate that this is more than just a normal incremental update of the previous version as suggested by naming it 2.1)
• Around 300 real issues were reported over the previous version and a majority of them were fixed in the new release.
• This is the first release with constructs and semantics coming from Common Power Format (CPF), a sign of convergence of the two industry leading power formats.
• There are about 100 working group meetings in my Outlook calendar since 2011, with meeting times ranging from 2 hours to 8 hours.
• We extensively used Google Drive (which was called Google Docs when the working group started), a great tool for productivity. I cannot imagine how any standard could have been done before Google existed!

Personally, I had an enjoyable journey, especially from having the privilege to work with many industry experts who are all passionate about low power. I do have one more thing to share though. My older daughter went from middle school to high school during the period of the development of the new standard. Since most of the meetings took place in the early morning California time, she had to endure the pain of listening to all these discussions on power domain, power switches, etc. on her way to school.

I asked her if she learned anything. She told me that other than being able to recognize the voices of Erich, John and Joe on the line, she also learned that she would never want to become an electrical or computer engineer! She was so happy that the meetings stopped a couple of months ago. But what I did not tell her is that the meetings will resume after DAC! Well, I am sure this will be a big motivation for her to get her own driving license in the summer.

If you want to get some quick technical insights into the new standard, check out my recent EE Times article IEEE 1801-2013: A bold step towards power format convergence.

Qi Wang

DAC is right around the corner! On the demo floor at Cadence® Booth #2214, we will demonstrate how to use the Cadence mixed-signal and low-power solution to design, verify, and implement a microcontroller-based mixed-signal design. The demo design architecture is very similar to practical designs of many applications like power management ICs, automotive controllers, and the Internet of Things (IoT). Cadene tools demonstrated in this design include Virtuoso® Schematic Editor, Virtuoso Analog Design Environment, Virtuoso AMS Designer, Virtuoso Schematic Model Generator, Virtuoso Power Intent Assistant, Incisive® Enterprise Simulator with DMS option, Virtuoso Digital Implementation, Virtuoso Layout Suite, Encounter® RTL Compiler, Encounter Test, and Conformal Low Power. An extended version of this demo will also be shown at the ARM® Connected Community Pavilion Booth #921.

For additional highlights on Cadence mixed-signal and low-power solutions, stop by our booth for:

• The popular book, Mixed-signal Methodology Guide, which will be on sale during DAC week!
• A sneak preview of the eBook version of the Mixed-signal Methodology Guide
• Customer presentations at the Cadence DAC Theater
  • 9am, Tuesday, June 4  ARM  Low-Power Verification of A15 Hard Macro Using CLP 
  • 10:30am, Tuesday, June 4  Silicon Labs  Power Mode Verification in Mixed-Signal Chip
  • 12:00pm, Tuesday, June 4  IBM  An Interoperable Flow with Unified OA and QRC Technology Files
  • 9am, Wednesday, June 5  Marvell  Low-Power Verification Using CLP
  • 4pm, Wednesday, June 5  Texas Instruments  An Inter-Operable Flow with Unified OA and QRC Technology Files
• Partner presentations at the Cadence DAC Theater
  • 10am, Monday, June 3  X-Fab  Rapid Adoption of Advanced Cadence Design Flows Using X-FAB's AMS Reference Kit
  • 3:30pm, Monday, June 3  TSMC TSMC Custom Reference Flow for 20nm -  Cadence Track
  • 9:30am,Tuesday, June 4  TowerJazz   Substrate Noise Isolation Extraction/Model Using Cadence Analog Flow
  • 12:30pm, Wednesday, June 5  GLOBALFOUNDRIES  20nm/14nm Analog/Mixed-signal Flow
  • 2:30pm, Wednesday, June 5  ARM  Cortex®-M0 and Cortex-M0+: Tiny, Easy, and Energy-efficient Processors for Mixed-signal Applications
• Technology sessions at suites
  • 10am, Monday, June 3    Low-power Verification of Mixed-signal Designs
  • 2pm, Monday, June 3      Advanced Implementation Techniques for Mixed-signal Designs
  • 2pm, Monday, June 3      LP Simulation: Are You Really Done?
  • 4pm, Monday, June 3      Power Format Update: Latest on CPF and IEEE 1801  
  • 11am, Wednesday, June 5   Mixed-signal Verification
  • 11am, Wednesday, June 5   LP Simulation: Are You Really Done?
  • 4pm, Wednesday, June 5   Successful RTL-to-GDSII Low-Power Design (FULL)
  • 5pm, Wednesday, June 5   Custom/AMS Design at Advanced Nodes

We will also have three presentations at the Si2 booth (#1427):

• 10:30am, Monday, June 3   An Interoperable Implementation Solution for Mixed-signal Design
• 11:30am, Tuesday, June 4   Low-power Verification for Mixed-signal Designs Using CPF
• 10:30am, Wednesday, June 5   System-level Low-power Verification Using Palladium

We have a great program at DAC. Click the link for complete Cadence DAC Theater and Technology Sessions. Look forward to seeing you at DAC!     

If you weren't able to attend the 2013 DVCon, you missed out on a great IEEE 1801/UPF tutorial delivered by members of the IEEE committee. Accellera had the event recorded and that recording is now posted on the Accellera.org website. Regardless of your work so far with low power design and verification, you need to watch this video.

Power management is becoming ubiquitous in our world. The popular aspect is that reduced power is good for the evironment and that is true. But for those teams that have been building chips around the 40nm node and below, there is another truth. Power management is required simply to get working silicon in many cases. As the industry expands the number of designs with power management and forges deeper into advanced nodes, we steadily identify improvements to the power format descriptions. The most recent set of imporvements to the IEEE 1801 standard are now available in the 2013 version of that standard.

To help bring the standard to life, five representatives from the IEEE joined to deliver a tutorial at DVCon in 2013. Qi Wang (Cadence), Erich Marschner (Mentor), Jeffrey Lee (Synopsys), John Biggs (ARM), and Sushma Honnavarra-Prasad (Broadcom) each contributed to the tutorial. It started with a review of the UPF basics that led to the IEEE 1801 standard delivered by the EDA companies. The IEEE 1801 users then presented tutorial content on how to apply the standard. The session then concluded with a look forward to the IEEE 1801-2013 (UPF 2.1) standard. The standard was released two months after the DVCon tutorial and is available through the Accellera Get program.

So after the bowl games are over and you'vre returned through the woods and back over the river from Grandma's, grab a cup of hot cocoa and learn more about the power standards you may well be using in 2014.

Regards,

Adam "The Jouler" Sherer

Hi,
I am new to the circuit design and troubleshooting. My project is to design a trans-impedance amplifier using Cadence that can amplify a signal coming from a photodiode. I started out with the regulated cascode configuration as shown in the circuit below. I look at the frequency response using AC simulation and it looks like a high pass (/net 5). The results doesn ot show any gain (transient response), or expected low-pass roll-off in the AC response.

First thing, I looked into the operating regions of the MOSFETs and adjusted the input dc voltage of the Vsin to 0.5 to make sure that the T0, T1 mosfets are in saturation(checked this with the print->dc operating points). Beyond this point, I am not sure on how to proceed and interpret the results to make changes. Any help would be greatly appreciated.

Thanks,

-Rakesh.

Virtuoso Version -- IC6.1.7-64b.500.23

Cadence Spectre Version -- 17.10.515

I have a very simple circuit. Please find attached. It is basically a resistor across a port. I run a S-param simulation and can plot the S-params, but unfortunately not the Z-param or Y-param. 

/resized-image/__size/320x240/__key/communityserver-discussions-components-files/33/Capture_5F00_Sch.JPG

/resized-image/__size/320x240/__key/communityserver-discussions-components-files/33/Capture_5F00_Error.JPG

Can anyone point me in the correct direction to sort out this problem? The zpm does work in another design environment, but not in the new design environment (a new project). The virtuoso and the cadence-spectre versions match in both the project environments. I am at a loss at what to look for. 

Hello,

Would anyone know how to setup a PSS or QPSS simulation with 25% dutycycle clock sources or if such a thing is possible with QPSS.

Fig1 (below) is a snapshot of the circuit I am trying to characterize. This has 4 clock ports each with 25%duty cycle in the ON state. Fig2 below shows two of these clocks.

Each path in the circuit consists of two switches with a low pass RC sandwiched in between. The Input is a 50Ohm port sine wave and the output is a 1K resistor. The output nets of all paths are connected together.

I am trying to determine the swept frequency response from input to output (voltage) when the input is from 500Mhz to  510MHz. The Period (T=1/Fp) of each of the pulses is such that Fp=500MHz. The first pulse source has a delay=0, second has delay=T/4, third delay=2T/4, etc...

I am currently getting it working and seeing the correct result (bandpass response) with Transient but the problem is doing a dft at 500MHz with 10KHz spacings needs at least 100us and takes up a lot of time and disk space.

Many Thanks,
Chris.

Fig1

Fig2

Hello, I have a problem with a certain type of transistor,my hyrarchy has a lot components an sub components and visually inspecting them is very hard.

is there a way like in other cadence layout viewer tools , to enter the name of the component or a NET somewhere and it will focus on it visualy or give the hyrarchy path to it?

Thanks.

Hello, I am trying to use two inductors in my LNA as shown bellow to have a S-PARAM response so i will have S11 with lowerst possible values and tweak them for matching network. However when i ran EXPLORER live tuning with SParam as shown bellow i get no change in the response.

I know that Cgs and Cgd with the inductors having a resonance so by Varying L value i should have seen the change in resonance location,

But there is no change.Where did i go wrong?

Thanks. 

Hi all,

What is the most accurate way to simulate the gm of  RF transistors (RF stage) of an active mixer (single balanced or Gilbert cell)?

I tried to simulate it with many ways such as:

1. DC annotation (but of course its incorrect due to the switching operation of the mixer)

2. d(i_ds)/d(v_gs) using HB analysis and then taking the value at zero (since it is a DC characteristic). In this way I chose in the simulator results of HB: Voltage, spectrum, rms, magnitude. 

3. Using the OP, OPT buttons in the calculator and then extracting the gm of the transistor. 

The problem is that each way gives a different value which makes the procedure of designing an active mixer very difficult. In addition, when I simulate the voltage conversion gain of the active mixer and trying to compare it to the formula (2/pi)*gm*RL (either in linear or dB), I get numbers which are way too far from simulations. I understand that I would not get the same results but not different by hundreds percent. 

I see in many publications that people are plotting graphs of mixer's gm vs. different parameters and starting to doubt whether the results are correct.

I would appreciate any help,

Thanks in advance

Hello, i need to test the  parameter Kf under some conditions in subthreshold.i cannot just plot the OP param,becasue i need to derive it under certain conditions.

Spectre(of Cadence) like BSIM(of Berkley) has developed a method for deriving each parameter in their model.

Is there a way to help me with such manual where i can test in cadence virtuoso the Kf parameter shown in the formula bellow?

Thanks.

hi everyone, 

i'm trying to create a netlist for aging simulation. i would like to simulate how power, Gain and PAE (efficiency) are inlfuenced after 3 hours

i would be grateful if someone can correct my syntax in the netlist since i'm trying to make a sweep HB  simulation where the input power is the parameter.

i did it without any error for the sp (S parameters)  simulation.

you can see the images for both sp and hb simulation netlists. (from left to right: sp aging netlist; hb aging netlist)

i will be grateful if someone can provide me some syntax advices.

thanks,

best regards

hello there, i'm a student studying allegro PCB designer.

There are some commands that i can do with GUI, but i want to know what kind of commands i used so that i can route with commands only(ex) skill).

Is there any file that i can see what kind of commands i used something like log files or command history?

thank you for reading this long boring question.

Other tools allow a sanity check of placement density vs available board space.  There is an older post "Skill code to evaluate all components area (Accumulative Place bound area)"  (9 years ago) that has a couple of examples that no longer work or expired.

This would be useful to provide feedback to schismatic and project managers regarding the component density on the PCB and how it will affect the routing abilities.  Thermal considerations can be evaluated as well 

Has anyone attempted this or still being done externally in spread sheets?

Hello, i am a student who is studying Allegro tool with SKILL.

I have a question about SKILL axlSegDelayAndZ0. The reference says this function "returns the delay and impedance of a cline segment."

I want to know how many components does this tool consider when calculating timing delay from the length. 

How steep is input signal's rise transition? Is rise transition shape isosceles trapezoid or differential increasing shape?

Also, if it is a multi fan-out, the rise transition time will be different net by net. How can this tool can calculate in this case?

I want to hear answers about these questions.

Thank you for reading this long boring questions, and i will be waiting for answers.

I have made a customized menu in PCB Editor which I now would like to fill with content.

First of all I would like to have commands to add (or delete) layers in the board. I have parameter files (.prm) that describes both the stackup and the artwork for 2, 4, 6 and 8 layers.

I guess I could record a script (macro) where I use the "Import Parameter file" dialogue but this will get windows flickering by etc. Can I do this with SKILL instead?

I realize that it is possible (somehow) to do a SKILL-script that completely builds up the stackup and artworks for boards with different number of layers but I then have to edit the SKILL everytime I need to change anything. My thinking is that it perhaps is easier just to call the prm-file, which is easy to modify from within Allegro without knowing anything about SKILL.

I'm also looking for a solution to remove some Subclasses, containing certain keywords with a SKILL script but since I'm completely new to SKILL I don't really know where to begin.

Any assistance would be much appreciated.

For a project, we depend on capturing warnings. This works fine in Virtuoso but behaves differently in Allegro.

In our observations

Virtuoso:

>>> warn("Hello")

*WARNING* Hello

Allegro:

>>> warn("Hello")

*WARNING* Hello

But when we capture the warning:

Virtuoso:

>>> warn("Hello") getWarn()

"Hello"

Allegro:

>>> warn("Hello") getWarn()

"*WARNING* Hello"

This is a Problem for because we put an empty String in the warn and depend on the fact that no Warning results in an empty String but on Allegro the output always begins with *WARNING*

Is there a way to make the behavior consistent in both versions?

This is the 15th installment of The Rationalist, my column for the Times of India.

It’s election season, and promises are raining down on voters like rose petals on naïve newlyweds. Earlier this week, the Congress party announced a minimum income guarantee for the poor. This Friday, the Modi government released a budget full of sops. As the days go by, the promises will get bolder, and you might feel important that so much attention is being given to you. Well, the joke is on you.

Every election, HL Mencken once said, is “an advance auction sale of stolen goods.” A bunch of competing mafias fight to rule over you for the next five years. You decide who wins, on the basis of who can bribe you better with your own money. This is an absurd situation, which I tried to express in a limerick I wrote for this page a couple of years ago:

POLITICS: A neta who loves currency notes/ Told me what his line of work denotes./ ‘It is kind of funny./ We steal people’s money/And use some of it to buy their votes.’

We’re the dupes here, and we pay far more to keep this circus going than this circus costs. It would be okay if the parties, once they came to power, provided good governance. But voters have given up on that, and now only want patronage and handouts. That leads to one of the biggest problems in Indian politics: We are stuck in an equilibrium where all good politics is bad economics, and vice versa.

For example, the minimum guarantee for the poor is good politics, because the optics are great. It’s basically Garibi Hatao: that slogan made Indira Gandhi a political juggernaut in the 1970s, at the same time that she unleashed a series of economic policies that kept millions of people in garibi for decades longer than they should have been.

This time, the Congress has released no details, and keeping it vague makes sense because I find it hard to see how it can make economic sense. Depending on how they define ‘poor’, how much income they offer and what the cost is, the plan will either be ineffective or unworkable.

The Modi government’s interim budget announced a handout for poor farmers that seemed rather pointless. Given our agricultural distress, offering a poor farmer 500 bucks a month seems almost like mockery.

Such condescending handouts solve nothing. The poor want jobs and opportunities. Those come with growth, which requires structural reforms. Structural reforms don’t sound sexy as election promises. Handouts do.

A classic example is farm loan waivers. We have reached a stage in our politics where every party has to promise them to assuage farmers, who are a strong vote bank everywhere. You can’t blame farmers for wanting them – they are a necessary anaesthetic. But no government has yet made a serious attempt at tackling the root causes of our agricultural crisis.

Why is it that Good Politics in India is always Bad Economics? Let me put forth some possible reasons. One, voters tend to think in zero-sum ways, as if the pie is fixed, and the only way to bring people out of poverty is to redistribute. The truth is that trade is a positive-sum game, and nations can only be lifted out of poverty when the whole pie grows. But this is unintuitive.

Two, Indian politics revolves around identity and patronage. The spoils of power are limited – that is indeed a zero-sum game – so you’re likely to vote for whoever can look after the interests of your in-group rather than care about the economy as a whole.

Three, voters tend to stay uninformed for good reasons, because of what Public Choice economists call Rational Ignorance. A single vote is unlikely to make a difference in an election, so why put in the effort to understand the nuances of economics and governance? Just ask, what is in it for me, and go with whatever seems to be the best answer.

Four, Politicians have a short-term horizon, geared towards winning the next election. A good policy that may take years to play out is unattractive. A policy that will win them votes in the short term is preferable.

Sadly, no Indian party has shown a willingness to aim for the long term. The Congress has produced new Gandhis, but not new ideas. And while the BJP did make some solid promises in 2014, they did not walk that talk, and have proved to be, as Arun Shourie once called them, UPA + Cow. Even the Congress is adopting the cow, in fact, so maybe the BJP will add Temple to that mix?

Benjamin Franklin once said, “Democracy is two wolves and a lamb voting on what to have for lunch.” This election season, my friends, the people of India are on the menu. You have been deveined and deboned, marinated with rhetoric, seasoned with narrative – now enter the oven and vote.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
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This is the 17th installment of The Rationalist, my column for the Times of India.

One of my favourite English words comes from chess. If it is your turn to move, but any move you make makes your position worse, you are in ‘Zugzwang’. Narendra Modi was in zugzwang after the Pulwama attacks a few days ago—as any Indian prime minister in his place would have been.

An Indian PM, after an attack for which Pakistan is held responsible, has only unsavoury choices in front of him. He is pulled in two opposite directions. One, strategy dictates that he must not escalate. Two, politics dictates that he must.

Let’s unpack that. First, consider the strategic imperatives. Ever since both India and Pakistan became nuclear powers, a conventional war has become next to impossible because of the threat of a nuclear war. If India escalates beyond a point, Pakistan might bring their nuclear weapons into play. Even a limited nuclear war could cause millions of casualties and devastate our economy. Thus, no matter what the provocation, India needs to calibrate its response so that the Pakistan doesn’t take it all the way.

It’s impossible to predict what actions Pakistan might view as sufficient provocation, so India has tended to play it safe. Don’t capture territory, don’t attack military assets, don’t kill civilians. In other words, surgical strikes on alleged terrorist camps is the most we can do.

Given that Pakistan knows that it is irrational for India to react, and our leaders tend to be rational, they can ‘bleed us with a thousand cuts’, as their doctrine states, with impunity. Both in 2001, when our parliament was attacked and the BJP’s Atal Bihari Vajpayee was PM, and in 2008, when Mumbai was attacked and the Congress’s Manmohan Singh was PM, our leaders considered all the options on the table—but were forced to do nothing.

But is doing nothing an option in an election year?

Leave strategy aside and turn to politics. India has been attacked. Forty soldiers have been killed, and the nation is traumatised and baying for blood. It is now politically impossible to not retaliate—especially for a PM who has criticized his predecessor for being weak, and portrayed himself as a 56-inch-chested man of action.

I have no doubt that Modi is a rational man, and knows the possible consequences of escalation. But he also knows the possible consequences of not escalating—he could dilute his brand and lose the elections. Thus, he is forced to act. And after he acts, his Pakistan counterpart will face the same domestic pressure to retaliate, and will have to attack back. And so on till my home in Versova is swallowed up by a nuclear crater, right?

Well, not exactly. There is a way to resolve this paradox. India and Pakistan can both escalate, not via military actions, but via optics.

Modi and Imran Khan, who you’d expect to feel like the loneliest men on earth right now, can find sweet company in each other. Their incentives are aligned. Neither man wants this to turn into a full-fledged war. Both men want to appear macho in front of their domestic constituencies. Both men are masters at building narratives, and have a pliant media that will help them.

Thus, India can carry out a surgical strike and claim it destroyed a camp, killed terrorists, and forced Pakistan to return a braveheart prisoner of war. Pakistan can say India merely destroyed two trees plus a rock, and claim the high moral ground by returning the prisoner after giving him good masala tea. A benign military equilibrium is maintained, and both men come out looking like strong leaders: a win-win game for the PMs that avoids a lose-lose game for their nations. They can give themselves a high-five in private when they meet next, and Imran can whisper to Modi, “You’re a good spinner, bro.”

There is one problem here, though: what if the optics don’t work?

If Modi feels that his public is too sceptical and he needs to do more, he might feel forced to resort to actual military escalation. The fog of politics might obscure the possible consequences. If the resultant Indian military action causes serious damage, Pakistan will have to respond in kind. In the chain of events that then begins, with body bags piling up, neither man may be able to back down. They could end up as prisoners of circumstance—and so could we.

***

Also check out:

Why Modi Must Learn to Play the Game of Chicken With Pakistan—Amit Varma
The Two Pakistans—Episode 79 of The Seen and the Unseen
India in the Nuclear Age—Episode 80 of The Seen and the Unseen

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
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This is the 19th installment of The Rationalist, my column for the Times of India.

A friend of mine was very impressed by the interview Narendra Modi granted last week to Akshay Kumar. ‘Such a charming man, such great work ethic,’ he gushed. ‘He is the kind of uncle I would want my kids to have.’ And then, in the same breath, he asked, ‘How can such a good man be such a bad prime minister?”

I don’t want to be uncharitable and suggest that Modi’s image is entirely manufactured, so let’s take the interview at face value. Let’s also grant Modi his claims about the purity of his neeyat (intentions), and reframe the question this way: when it comes to public policy, why do good intentions often lead to bad outcomes? To attempt an answer, I’ll refer to a story a friend of mine, who knows Modi well, once told me about him. 

Modi was chilling with his friends at home more than a decade ago, and told them an incident from his childhood. His mother was ill once, and the young Narendra was tending to her. The heat was enervating, so the boy went to the switchboard to switch on the fan. But there was no electricity. My friend said that as he told this story, Modi’s eyes filled with tears. Even after all these years, he was moved by the memory.

My friend used this story to make the point that Modi’s vision of the world is experiential. If he experiences something, he understands it. When he became chief minister of Gujarat, he made it his stated mission to get reliable electricity to every part of Gujarat. No doubt this was shaped by the time he flicked a switch as a young boy and the fan did not budge. Similarly, he has given importance to things like roads and cleanliness, since he would have experienced the impact of those as a young man.

My term for him, inspired by Rajat Kapoor’s 2014 film, is ‘the ankhon dekhi prime minister’. At one level, this is a good thing. He sees a problem and works for the rest of his life to solve it. But what of things he cannot experience?

The economy is a complex beast, as is society itself, and beyond a certain level, you need to grasp abstract concepts to understand how the world works. You cannot experience them. For example, spontaneous order, or the idea that society and markets, like language, cannot be centrally directed or planned. Or the positive-sum nature of things, which is the engine of our prosperity: the idea that every transaction is a win-win game, and that for one person to win, another does not have to lose. Or, indeed, respect for individual rights and free speech.

One understands abstract concepts by reading about them, understanding them, applying them to the real world. Modi is not known to be a reader, and this is not his fault. Given his background, it is a near-miracle that he has made it this far. He wasn’t born into a home with a reading culture, and did not have either the resources or the time when he was young to devote to reading. The only way he could learn about the world, thus, was by experiencing it.

There are two lessons here, one for Modi himself and others in his position, and another for everyone.

The lesson in this for Modi is a lesson for anyone who rises to such an important position, even if he is the smartest person in the world. That lesson is to have humility about the bounds of your knowledge, and to surround yourself with experts who can advise you well. Be driven by values and not confidence in your own knowledge. Gather intellectual giants around you, and stand on their shoulders.

Modi did not do this in the case of demonetisation, which he carried out against the advice of every expert he consulted. We all know the damage it caused to the economy.

The other learning from this is for all of us. How do we make sense of the world? By connecting dots. An ankhon-dekhi approach will get us very few dots, and our view of the world will be blurred and incomplete. The best way to gather more dots is reading. The more we read, the better we understand the world, and the better the decisions we take. When we can experience a thousand lives through books, why restrict ourselves to one?

A good man with noble intentions can make bad decisions with horrible consequences. The only way to hedge against this is by staying humble and reading more. So when you finish reading this piece, think of an unread book that you’d like to read today – and read it!

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
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This is the 20th installment of The Rationalist, my column for the Times of India.

Amit Shah’s induction into the union cabinet is such an interesting moment. Even partisans who oppose the BJP, as I do, would admit that Shah is a political genius. Under his leadership, the BJP has become an electoral behemoth in the most complicated political landscape in the world. The big question that now arises is this: can Shah do for India what he did for the BJP?

This raises a perplexing question: in the last five years, as the BJP has flourished, India has languished. And yet, the leadership of both the party and the nation are more or less the same. Then why hasn’t the ability to manage the party translated to governing the country?

I would argue that there are two reasons for this. One, the skills required in those two tasks are different. Two, so are the incentives in play.

Let’s look at the skills first. Managing a party like the BJP is, in some ways, like managing a large multinational company. Shah is a master at top-down planning and micro-management. How he went about winning the 2014 elections, described in detail in Prashant Jha’s book How the BJP Wins, should be a Harvard Business School case study. The book describes how he fixed the BJP’s ground game in Uttar Pradesh, picking teams for 147,000 booths in Uttar Pradesh, monitoring them, and keeping them accountable.

Shah looked at the market segmentation in UP, and hit upon his now famous “60% formula”. He realised he could not deliver the votes of Muslims, Yadavs and Jatavs, who were 40% of the population. So he focussed on wooing the other 60%, including non-Yadav OBCs and non-Jatav Dalits. He carried out versions of these caste reconfigurations across states, and according to Jha, covered “over 5 lakh kilometres” between 2014 and 2017, consolidating market share in every state in this country. He nurtured “a pool of a thousand new OBC and Dalit leaders”, going well beyond the posturing of other parties.

That so many Dalits and OBCs voted for the BJP in 2019 is astonishing. Shah went past Mandal politics, managing to subsume previously antagonistic castes and sub-castes into a broad Hindutva identity. And as the BJP increased its depth, it expanded its breadth as well. What it has done in West Bengal, wiping out the Left and weakening Mamata Banerjee, is jaw-dropping. With hindsight, it may one day seem inevitable, but only a madman could have conceived it, and only a genius could have executed it.

Good man to be Home Minister then, eh? Not quite. A country is not like a large company or even a political party. It is much too complex to be managed from the top down, and a control freak is bound to flounder. The approach needed is very different.

Some tasks of governance, it is true, are tailor-made for efficient managers. Building infrastructure, taking care of roads and power, building toilets (even without an underlying drainage system) and PR campaigns can all be executed by good managers. But the deeper tasks of making an economy flourish require a different approach. They need a light touch, not a heavy hand.

The 20th century is full of cautionary tales that show that economies cannot be centrally planned from the top down. Examples of that ‘fatal conceit’, to use my hero Friedrich Hayek’s term, include the Soviet Union, Mao’s China, and even the lady Modi most reminds me of, Indira Gandhi.

The task of the state, when it comes to the economy, is to administer a strong rule of law, and to make sure it is applied equally. No special favours to cronies or special interest groups. Just unleash the natural creativity of the people, and don’t try to micro-manage.

Sadly, the BJP’s impulse, like that of most governments of the past, is a statist one. India should have a small state that does a few things well. Instead, we have a large state that does many things badly, and acts as a parasite on its people.

As it happens, the few things that we should do well are all right up Shah’s managerial alley. For example, the rule of law is effectively absent in India today, especially for the poor. As Home Minister, Shah could fix this if he applied the same zeal to governing India as he did to growing the BJP. But will he?

And here we come to the question of incentives. What drives Amit Shah: maximising power, or serving the nation? What is good for the country will often coincide with what is good for the party – but not always. When they diverge, which path will Shah choose? So much rests on that.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
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This is the 22nd installment of The Rationalist, my column for the Times of India.

Trade wars are on the rise, and it’s enough to get any nationalist all het up and excited. Earlier this week, Narendra Modi’s government announced that it would start imposing tariffs on 28 US products starting today. This is a response to similar treatment towards us from the US.

There is one thing I would invite you to consider: Trump and Modi are not engaged in a war with each other. Instead, they are waging war on their own people.

Let’s unpack that a bit. Part of the reason Trump came to power is that he provided simple and wrong answers for people’s problems. He responded to the growing jobs crisis in middle America with two explanations: one, foreigners are coming and taking your jobs; two, your jobs are being shipped overseas.

Both explanations are wrong but intuitive, and they worked for Trump. (He is stupid enough that he probably did not create these narratives for votes but actually believes them.) The first of those leads to the demonising of immigrants. The second leads to a demonising of trade. Trump has acted on his rhetoric after becoming president, and a modern US version of our old ‘Indira is India’ slogan might well be, “Trump is Tariff. Tariff is Trump.”

Contrary to the fulminations of the economically illiterate, all tariffs are bad, without exception. Let me illustrate this with an example. Say there is a fictional product called Brump. A local Brump costs Rs 100. Foreign manufacturers appear and offer better Brumps at a cheaper price, say Rs 90. Consumers shift to foreign Brumps.

Manufacturers of local Brumps get angry, and form an interest group. They lobby the government – or bribe it with campaign contributions – to impose a tariff on import of Brumps. The government puts a 20-rupee tariff. The foreign Brumps now cost Rs 110, and people start buying local Brumps again. This is a good thing, right? Local businesses have been helped, and local jobs have been saved.

But this is only the seen effect. The unseen effect of this tariff is that millions of Brump buyers would have saved Rs 10-per-Brump if there were no tariffs. This money would have gone out into the economy, been part of new demand, generated more jobs. Everyone would have been better off, and the overall standard of living would have been higher.

That brings to me to an essential truth about tariffs. Every tariff is a tax on your own people. And every intervention in markets amounts to a distribution of wealth from the people at large to specific interest groups. (In other words, from the poor to the rich.) The costs of this are dispersed and invisible – what is Rs 10 to any of us? – and the benefits are large and worth fighting for: Local manufacturers of Brumps can make crores extra. Much modern politics amounts to manufacturers of Brumps buying politicians to redistribute money from us to them.

There are second-order effects of protectionism as well. When the US imposes tariffs on other countries, those countries may respond by imposing tariffs back. Raw materials for many goods made locally are imported, and as these become expensive, so do those goods. That quintessential American product, the iPhone, uses parts from 43 countries. As local products rise in price because of expensive foreign parts, prices rise, demand goes down, jobs are lost, and everyone is worse off.

Trump keeps talking about how he wants to ‘win’ at trade, but trade is not a zero-sum game. The most misunderstood term in our times is probably ‘trade-deficit’. A country has a trade deficit when it imports more than what it exports, and Trump thinks of that as a bad thing. It is not. I run a trade deficit with my domestic help and my local grocery store. I buy more from them than they do from me. That is fine, because we all benefit. It is a win-win game.

Similarly, trade between countries is really trade between the people of both countries – and people trade with each other because they are both better off. To interfere in that process is to reduce the value created in their lives. It is immoral. To modify a slogan often identified with libertarians like me, ‘Tariffs are Theft.’

These trade wars, thus, carry a touch of the absurd. Any leader who imposes tariffs is imposing a tax on his own people. Just see the chain of events: Trump taxes the American people. In retaliation, Modi taxes the Indian people. Trump raises taxes. Modi raises taxes. Nationalists in both countries cheer. Interests groups in both countries laugh their way to the bank.

What kind of idiocy is this? How long will this lose-lose game continue?

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
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This is the 23rd installment of The Rationalist, my column for the Times of India.

I had a strange dream last night. I dreamt that the government had passed a law that made using laptops illegal. I would have to write this column by hand. I would also have to leave my home in Mumbai to deliver it in person to my editor in Delhi. I woke up trembling and angry – and realised how Indian farmers feel every single day of their lives.

My column today is a tale of two satyagrahas. Both involve farmers, technology and the freedom of choice. One of them began this month – but first, let us go back to the turn of the millennium.

As the 1990s came to an end, cotton farmers across India were in distress. Pests known as bollworms were ravaging crops across the country. Farmers had to use increasing amounts of pesticide to keep them at bay. The costs of the pesticide and the amount of labour involved made it unviable – and often, the crops would fail anyway.

Then, technology came to the rescue. The farmers heard of Bt Cotton, a genetically modified type of cotton that kept these pests away, and was being used around the world. But they were illegal in India, even though no bad effects had ever been recorded. Well, who cares about ‘illegal’ when it is a matter of life and death?

Farmers in Gujarat got hold of Bt Cotton seeds from the black market and planted them. You’ll never guess what happened next. As 2002 began, all cotton crops in Gujarat failed – except the 10,000 hectares that had Bt Cotton. The government did not care about the failed crops. They cared about the ‘illegal’ ones. They ordered all the Bt Cotton crops to be destroyed.

It was time for a satyagraha – and not just in Gujarat. The late Sharad Joshi, leader of the Shetkari Sanghatana in Maharashtra, took around 10,000 farmers to Gujarat to stand with their fellows there. They sat in the fields of Bt Cotton and basically said, ‘Over our dead bodies.’ ¬Joshi’s point was simple: all other citizens of India have access to the latest technology from all over. They are all empowered with choice. Why should farmers be held back?

The satyagraha was successful. The ban on Bt Cotton was lifted.

There are three things I would like to point out here. One, the lifting of the ban transformed cotton farming in India. Over 90% of Indian farmers now use Bt Cotton. India has become the world’s largest producer of cotton, moving ahead of China. According to agriculture expert Ashok Gulati, India has gained US$ 67 billion in the years since from higher exports and import savings because of Bt Cotton. Most importantly, cotton farmers’ incomes have doubled.

Two, GMO crops have become standard across the world. Around 190 million hectares of GMO crops have been planted worldwide, and GMO foods are accepted in 67 countries. The humanitarian benefits have been massive: Golden Rice, a variety of rice packed with minerals and vitamins, has prevented blindness in countless new-born kids since it was introduced in the Philippines.

Three, despite the fear-mongering of some NGOs, whose existence depends on alarmism, the science behind GMO is settled. No harmful side effects have been noted in all these years, and millions of lives impacted positively. A couple of years ago, over 100 Nobel Laureates signed a petition asserting that GMO foods were safe, and blasting anti-science NGOs that stood in the way of progress. There is scientific consensus on this.

The science may be settled, but the politics is not. The government still bans some types of GMO seeds, such as Bt Brinjal, which was developed by an Indian company called Mahyco, and used successfully in Bangladesh. More crucially, a variety called HT Bt Cotton, which fights weeds, is also banned. Weeding takes up to 15% of a farmer’s time, and often makes farming unviable. Farmers across the world use this variant – 60% of global cotton crops are HT Bt. Indian farmers are so desperate for it that they choose to break the law and buy expensive seeds from the black market – but the government is cracking down. A farmer in Haryana had his crop destroyed by the government in May.

On June 10 this year, a farmer named Lalit Bahale in the Akola District of Maharashtra kicked off a satyagraha by planting banned seeds of HT Bt Cotton and Bt Brinjal. He was soon joined by thousands of farmers. Far from our urban eyes, a heroic fight has begun. Our farmers, already victimised and oppressed by a predatory government in countless ways, are fighting for their right to take charge of their lives.

As this brave struggle unfolds, I am left with a troubling question: All those satyagrahas of the past by our great freedom fighters, what were they for, if all they got us was independence and not freedom?

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

This is the 24th installment of The Rationalist, my column for the Times of India.

Back in the last decade, I was a cricket journalist for a few years. Then, around 12 years ago, I quit. I was jaded as hell. Every game seemed like déjà vu, nothing new, just another round on the treadmill. Although I would remember her fondly, I thought me and cricket were done.

And then I fell in love again. Cricket has changed in the last few years in glorious ways. There have been new ways of thinking about the game. There have been new ways of playing the game. Every season, new kinds of drama form, new nuances spring up into sight. This is true even of what had once seemed the dullest form of the game, one-day cricket. We are entering into a brave new world, and the team leading us there is England. No matter what happens in the World Cup final today – a single game involves a huge amount of luck – this England side are extraordinary. They are the bridge between eras, leading us into a Golden Age of Cricket.

I know that sounds hyperbolic, so let me stun you further by saying that I give the IPL credit for this. And now, having woken up you up with such a jolt on this lovely Sunday morning, let me explain.

Twenty20 cricket changed the game in two fundamental ways. Both ended up changing one-day cricket. The first was strategy.

When the first T20 games took place, teams applied an ODI template to innings-building: pinch-hit, build, slog. But this was not an optimal approach. In ODIs, teams have 11 players over 50 overs. In T20s, they have 11 players over 20 overs. The equation between resources and constraints is different. This means that the cost of a wicket goes down, and the cost of a dot ball goes up. Critically, it means that the value of aggression rises. A team need not follow the ODI template. In some instances, attacking for all 20 overs – or as I call it, ‘frontloading’ – may be optimal.

West Indies won the T20 World Cup in 2016 by doing just this, and England played similarly. And some sides began to realise was that they had been underestimating the value of aggression in one-day cricket as well.

The second fundamental way in which T20 cricket changed cricket was in terms of skills. The IPL and other leagues brought big money into the game. This changed incentives for budding cricketers. Relatively few people break into Test or ODI cricket, and play for their countries. A much wider pool can aspire to play T20 cricket – which also provides much more money. So it makes sense to spend the hundreds of hours you are in the nets honing T20 skills rather than Test match skills. Go to any nets practice, and you will find many more kids practising innovative aggressive strokes than playing the forward defensive.

As a result, batsmen today have a wider array of attacking strokes than earlier generations. Because every run counts more in T20 cricket, the standard of fielding has also shot up. And bowlers have also reacted to this by expanding their arsenal of tricks. Everyone has had to lift their game.

In one-day cricket, thus, two things have happened. One, there is better strategic understanding about the value of aggression. Two, batsmen are better equipped to act on the aggressive imperative. The game has continued to evolve.

Bowlers have reacted to this with greater aggression on their part, and this ongoing dialogue has been fascinating. The cricket writer Gideon Haigh once told me on my podcast that the 2015 World Cup featured a battle between T20 batting and Test match bowling.

This England team is the high watermark so far. Their aggression does not come from slogging. They bat with a combination of intent and skills that allows them to coast at 6-an-over, without needing to take too many risks. In normal conditions, thus, they can coast to 300 – any hitting they do beyond that is the bonus that takes them to 350 or 400. It’s a whole new level, illustrated by the fact that at one point a few days ago, they had seven consecutive scores of 300 to their name. Look at their scores over the last few years, in fact, and it is clear that this is the greatest batting side in the history of one-day cricket – by a margin.

There have been stumbles in this World Cup, but in the bigger picture, those are outliers. If England have a bad day in the final and New Zealand play their A-game, England might even lose today. But if Captain Morgan’s men play their A-game, they will coast to victory. New Zealand does not have those gears. No other team in the world does – for now.

But one day, they will all have to learn to play like this.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

Hello,
I'm exploring VManager tool capabilities.

I launched a simulation with xrun, which terminates with a fatal error (`uvm_fatal actually).

Then I imported the flow session, through VManager -> Regression -> Collect Runs, linking the directory with ucm and ucd of just failed run.

VManager imports the test with following attributes:

Total Runs =1

#Passed =1

#Failed =0

What I'm missing here? It should be imported as failed test.

If I right click on flow name and choose Analyze All Runs, VManager brings me to Analysis tab and I can see only a PASSED tag in Runs subwindow.

Thank you for any help

Hi All,

I'm trying to understand checkpoint concept. When I found save and restart concept in cdnshelp, There is just describing about "$save" and "xrun -r "~~~".

and I found also the below link about save restart and it saves your time.

But I can't find any benefits from my experiment from save&restart article( I fully agree..the article)

Ok, So I'v got some experiment  Here.

1. I declared $save and got the below result as I expected within the simple UVM code.

In UVM code...

$display("TEST1");
$display("TEST2");
$save("SAVE_TEST");
$display("TEST3");
$display("TEST4");

And I restart at "SAVE_TEST" point by xrun -r "SAVE_TEST", I've got the below log

xcelium> run
TEST3
TEST4

Ok, It's Good what I expected.(The concept of Save and Restore is simple: instead of re-initializing your simulation every time you want to run a test, only initialize it once. Then you can save the simulation as a “snapshot” and re-run it from that point to avoid hours of initialization times. It used to be inconvenient. I agree..)

2. But The Problem is that I can't restart with modified code. Let's see the below example.

I just modified TEST5 instead of "TEST3"

$display("TEST1");
$display("TEST2");
$save("SAVE_TEST");
$display("TEST5"); //$display("TEST3");
$display("TEST4");

and I rerun with xrun -r "SAVE_TEST", then I've got the same log

xcelium> run
TEST3
TEST4

There is no "TEST5". Actually I expected "TEST5" in the log.From here We know $save can't support partially modified code after $save. 

Actually, through this, we can approach to our goal about saving developing time. 

So I want to know Is there any possible way that instead of re-initializing our simulation every time we want to run a test, only initialize it once and keep developing(debugging) our code ?

If we do, Could you let me know the simple example?

I have a problem connected with my AXI4 coverage.

I enable coverage collection in AXI4 

      set_config_int("axi4_active_slave_agent_0.monitor.coverModel", "burst_started_enable", 1);
      set_config_int("axi4_active_slave_agent_0.monitor.coverModel", "coverageEnable", 1);

but i don't have a result.

I think the problem in Callback, but i try to connect all callback and i don't have positive result.

Can you help me?

Hi all,

         I want to know how to run a regressive test in cadence and merge all ncsim .trn file of each test case into a single file to view all waveform in simvision. I am using Makefile to invoke the test case.

         eg:-

               test0:

                     irun -uvm -sv -access +rwc $(RTL) $(INTER) $(PKG) $(TOP) $(probe) +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test0

             test1:

                   irun -uvm -sv -access +rwc $(RTL) $(INTER) $(PKG) $(TOP) $(probe) +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test1

          I just to call test0 followed by test1 or parallel both test and view the waveform for both tests case.

        I new to this tool and help me with it

Hi,

I found a basic Specman E/Verilog program at http://www.asic-world.com/examples/specman/memory.html and I would like to run it through a vsif file, with vManager.

I'm able to run it, without problems, with this command : xrun -Q -unbuffered '-timescale' '1ns/1ns' '-access' '+rw' memory_tb.v mem_tb_top.e test_write_read_all.e.

I wrote a first vsif which look like this:

---- vm_basic.vsif -----

session vm_basic {
        top_dir : /home/cadence/xrunTest/;
        output_mode: terminal;
};

group basic {
        test test {
                run_script: xrun -Q -unbuffered '-timescale' '1ns/1ns' '-access' '+rw' memory_tb.v mem_tb_top.e test_write_read_all.e
        };
};

----------------------------

This solution didn't work due to the prompt change with xrun, and I have no clue how to manage this issue.

Have you any idea?

Best regards,

Yohan

I am importing sessions which are run by other people to analyse and I would like to remove them from my vManager Regressions tab as they become obsolete. As I am not the original person who run the sims, I cannot "delete" sessions. What are my options? Thanks.

Specman *search* command allows searching in all loaded modules, but only for a string.

Is there a way to search for a regexp or glob?

Alternatively, is there a way to simply get a list of all loaded files somehow? Then I could use either the "shell" command, or real shell together with grep.

Thanks

  A few weeks ago, we talked about template text labels for design-specific information. There, we were focused on labels that are specific to the design as a whole: revision information, dates, authors, etc. Today, we’re looking at a diff...(read more)

No, this isn’t a Hollywood movie. We’re talking about pieces of plane shapes with no connections to them, not an idyllic private oasis in the Caribbean (sorry). Removing shape islands is something you’ve always been able to do in th...(read more)

Molding caps aren’t something we talk about too frequently around here. We all know they exist, and they serve an important purpose of protecting the delicate die from potentially harsh environmental conditions. They impact how well heat can be...(read more)

We have talked about aspects of the in-design symbol edit application mode in the past. This is the environment specific to the Allegro Package Designer layout tools allowing you to work on symbol definitions directly in the context of your layout de...(read more)

Here are two screen capture of Before and After Autorouting my board. Padstacks have all been revised and corrected. The Capture Schematic is correct. All Footprints have been verified after Padstack revision. a new NETLIST generation have been done after some corrections made in Capture. I have imported the new Logic. I revised my Layout Cross Section as such: TOP, GND, VCC, BOTTOM. Both VCC and GND shapes have been assigned to their respective logical GND and VCC Nets (verified). Yet, I still have the Autorouter to systematically use extra vias to make GND and VCC connections to the VCC and GND planes. Where a simple utilisation of the part padstack inner layer would have been indicated. What Im I missing ?

Is anyone else using Constraint Manager within Capture? This is my first time using it. I'm finding that it is occasionally changing some of my constraint values in Allegro. It seems random. 

Picture 1 show a Shape created in Allegro PCB Editor 16.6, file LTshape.ssm      The Shape Origin is dead center of the outline 565X400 mils.    This Shape is utilized in the PadStack Editor to create a special Pin for a custom Footprint.
Picture 2 show the PadStack Editor first page with drill size and offset. File  LTshape16.pad         Picture 3 show the PadStack Editor page 2 with that LTshape utilized as the BEGIN LAYER for copper area. Picture 4 show the actual Package (footprint) finished with Outline, padstacks for pin 1,2,4,5 and that special Pin 3 LTshape. Its origin is also dead center, same as LTshape.ssm

Notice the round dot at the bottom of Pin 3. It only appear in the Package drawing, not in the original Picture 1, the actual LTshape.ssm or LTshape.dra

Picture 5 shows that same Footprint in the final board in PCB Editor. That same dot, now pink, is still there and cannot be selected separately. When using the Find Option and selecting each object separately, the only way to select Pin 3 is when Option > Pin is selected. Then I can hover on the dot near Pin 3 and the whole LTshape lights up as pin 3, but not the pink dot. There is absolutely no way I can select that dot as an object. There is no way to know the existence of that dot except by looking at it. Cannot be deleted, cannot be selected, can only be invisible if I use the Color Visibility manager and disable all 4 layers, TOP GND VCC BOTTOM. If I turn On TOP then the dot becomes pink. With GND On the dot is green, VCC On will get a Red dot, BOTTOM On will not show the dot but Pin 3 turn On since LTshape is the actual Net connected. This Net is not GND nor VCC, it is N357726.

Where is this dot coming from and why is it not a selectable object ? Why can I not delete it ?

Hi, I am in the middle of a design and had no problem going back and forth between schematics and layout. Now I am getting the error message below. I am using Cadence 17.2.

ERROR: Layout database has probably been reverted to an earlier version than that, which was used in the latest flow or the schematic database was synchronized with another board.

The basecopy file generated by the last back-to-front flow not found.

ERROR: Layout database has probably been reverted to an earlier version than that, which was used in the latest flow or the schematic database was synchronized with another board.

The basecopy file generated by the last back-to-front flow not found.

Error: CMFBC-1: The schematic and the layout constraints were not synchronized as the changes done since the last sync up could not be reconciled. Syncing the current version of the schematic or layout databases with a previous version would result in this issue. The  constraint difference report is displayed.

Continuing with "changes-only" processing may result in incorrect constraint updates.

Thanks for your input

Claudia

Hi All,

I've just about to finish my first PCB layout, and I want to understand some 2 issues better:

1. Soldermask layer: when exactly do we want to define for some SMT pad (say at Pad Designer tool), to have soldermask top and when we want to define solermask bottom? 

if it's a TH pad, I guess we always want to define both layers soldermask (top, bottom), because the pads are crossing all the layers. However, if it's a SMT pad, which SM we want?

2. Pastemask layer: is this layer necessary for the gerber files generation, when we have SMT components in our circuit?

And again, when we define for a TH/SMT pads pastemask top, and when Pastemask bottom?

Thanks!