An adjustable refrigerant distribution device and a heat exchanger having same. The heat exchanger comprises: first and second collecting pipes; a heat exchanger core body; and a refrigerant distribution device, the refrigerant distribution device comprises a first distribution pipe, a first inlet pipe and a first drive assembly. The pipe wall of the first distribution pipe is provided with a first distribution hole. The first distribution pipe is inserted into at least one of the first and the second collecting pipes. The first inlet pipe is located outside at least one collecting pipe and is in communication with the first distribution pipe, and the first drive assembly drives the first distribution pipe to move relative to at least one collecting pipe. The distribution pipe of the refrigerant distribution device and the heat exchanger can translate along the axial direction, thereby adjusting refrigerant distribution so as to satisfy different distribution requirements.

Integrated heat spreaders having electromagnetically-formed features, and semiconductor packages incorporating such integrated heat spreaders, are described. In an example, an integrated heat spreader includes a top plate flattened using an electromagnetic forming process. Methods of manufacturing integrated heat spreaders having electromagnetically-formed features are also described.

In a cooled component system, a heat exchanger mounted on a surface of the industrial component is housed in an isolated access compartment adjacent to but separated from the primary compartment containing the industrial component. Housing the heat exchanger in a separately accessible compartment permits access to the heat exchanger for cleaning or other purposes without having to shut down the industrial component being cooled. A means for moving a cooling media over the surface a the heat exchanger might also be included to maximize heat exchange.

An electronic rack includes a housing to contain one or more IT components arranged in a stack, a first rack aisle formed on a first side of the one or more IT components to direct cooler air received from the cooling unit upwardly, and a second rack aisle formed on a second side of the one or more IT components to direct warmer air to the cooling unit downwardly. The electronic rack further includes a cooling unit having one or more cooling units disposed underneath the IT components to receive first liquid from an external chiller system, to exchange heat carried by the warmer air using the first liquid to generate the cooler air, to transform the first liquid into a second liquid with a higher temperature, and to transmit the second liquid carrying the exchanged heat back to the external chiller system.

A rack airflow monitoring system is configured to measure airflow through an equipment rack having a housing and a perforated front door to enable air to flow into an interior of the housing. The system includes a control module, and a plurality of airflow sensors secured to the front door of the equipment rack and coupled to the control module. Each airflow sensor is configured to detect a parameter used to measure airflow and communicate detected parameters to the control module. The control module is configured to obtain temperature, airflow velocity, and airflow directionality from the plurality of airflow sensors at the front door of the equipment rack.

Embodiments of the invention provides a decoder for decoding a signal received through a transmission channel in a communication system, said signal carrying information symbols selected from a given alphabet and being associated with a signal vector, said transmission channel being represented by a channel matrix, wherein said decoder comprises: a sub-block division unit (301) configured to divide the received signal vector into a set of sub-vectors in correspondence with a division of a matrix related to said channel matrix;a candidate set estimation unit (305) for recursively determining candidate estimates of sub-blocks of the transmitted signal corresponding to said sub-vectors, each estimate of a given sub-block being determined from at least one candidate estimate of the previously processed sub-blocks,wherein said candidate set estimation unit is configured to determine a set of candidate estimates for at least one sub-block of the transmitted signal by applying at least one iteration of a decoding algorithm using the estimates determined for the previously processed sub-blocks, the number of candidate estimates determined for said sub-block being strictly inferior to the cardinal of the alphabet and superior or equal to two, the decoder further comprising a signal estimation unit (306) for calculating an estimate of the transmitted signal from said candidate estimates determined for said sub-blocks.

The present invention aims to provide a technology capable of enhancing the effect of reducing differential data in size. A bit shift unit shifts either of old data and new data in a forward direction and a backward direction of its bit string by each of 0, 1, 2, . . . , and n bit(s) to generate a plurality of data. A copy bit string extracting unit extracts information on copy bit strings based on the plurality of data and other non-shifted data. An additional bit string extracting unit excludes copy bit strings from the new data to extract information on additional bit strings. A differential data generating unit creates differential data based on the information on copy bit strings and the information on additional bit strings.

Methods and apparatus to parallelize data decompression are disclosed. An example method adjusting a first one of initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; and merging, by executing an instruction with the processor, first decoded data generated by decoding a first segment of the compressed data bitstream starting from the first adjusted starting position with second decoded data generated by decoding a second segment of the compressed data bitstream, the decoding of the second segment starting from a second position in the compressed data bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the compressed data bitstream.

A switch-scanning circuit includes a chip and switching units. The chip includes pins having an output operation mode and an input operation mode, and a processing unit. The processing unit sets one of the pins as an input pin and the rest of the pins as output pins sequentially according to a clock signal, uses a scan signal to provide different voltages to the output pins, and then determines states of button switches according to a voltage of the input pin. The switching unit includes a power source resistance, switches and resistors. A first terminal and a second terminal of the power source resistance are electrically connected to a power source and a first pin respectively. The resistors have terminals electrically connected the first pin and terminals of the switches. The other terminals of the switches are connected to the pins other than the first pin.

A circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal.

A summing node is provided for summing a first and second differential signals. Each of the first and second differential signals comprise respective direct and inverse signal components. The summing node comprises a first differential transistor pair comprising a first and second input and coupled to a first and second output. The summing node further comprises a second differential transistor pair comprising a third and fourth input and coupled to the first and second output. The first and fourth inputs are respectively coupled to the direct and inverse signal components of the first differential signal and the second and third inputs are respectively coupled to the direct and inverse signal components of the second differential signal.

The pulse width modulator includes a subtraction unit configured to perform subtraction between an m value digital signal and a pulse width modulation signal; a feedforward filter unit configured such that a ΔΣ modulator to which an output signal of the subtraction unit is input and which includes integrators of a second order or higher is in cascade connection, and configured to operate with a sampling frequency FS; a product-sum computing unit configured to operate with a sampling frequency (FS/n) (n: an integer of two or more) to perform product-sum computing of an output signal of each integrator of the feedforward filter unit; and a pulse width modulation unit configured to operate with the sampling frequency (FS/n) to perform pulse width modulation of an output signal of the product-sum computing unit to output a pulse width modulation signal.

A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level.

A method for adaptively regulating a coding mode and a digital correction circuit thereof are provided. The method is for a successive-approximation-register analog-to-digital converter (SAR ADC). In the method, whether to regulate a binary weight corresponding to each of digital bits is determined according to the number of completed comparison cycles to provide a first coding sequence. The first coding sequence is directly compensated according to uncompleted comparison cycles to provide a correct digital output code.

Disclosed are an apparatus and method for compressing continuous data. The apparatus for compressing continuous data may include a data generator configured to calculate differences between adjacent values in original continuous data and generate data based on the calculated differences.

A codeset having function-code combinations is provisioned on a controlling device to control functions of an intended target device. Input is provided to the controlling device which designates a function to be controlled on the intended target device. From a plurality of codes that are each associated with the designated function in a database stored in a memory of the controlling device a first code that is determined to be valid for use in controlling the designated function on the intended target device is selected. When the codeset is then provisioned on the controlling device, the provisioned codeset includes as a function-code combination thereof the designated function and the first code.

An analog to digital converter (ADC) system that includes a first amplifier configured to amplify an analog input signal to produce an amplified direct current (DC) signal, an ADC configured to receive the amplified DC signal and convert the amplified DC signal into a digital DC signal, a digital to analog converter configured to receive the digital DC signal and convert the digital DC signal into an analog DC signal, and a second amplifier configured to receive an analog alternating current (AC) signal comprising the analog DC signal subtracted from the analog input signal and amplify the analog AC signal to produce an amplified AC signal. The ADC is further configured to receive the amplified AC signal and produce a digital AC signal. The second amplifier has a gain greater than a gain of the first amplifier.

A multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.

An encoder for encoding input data (D1) to generate corresponding encoded data (E2) includes data processing hardware which is operable: (a) to determine at least partial reoccurrences of data blocks or data packets within the input data (D1), wherein the data blocks or data packets include a plurality of bytes;(b) to employ at least one reference symbol to relate reoccurrences of mutually similar data blocks or data packets and/or to indicate whether or not there are reoccurrences of mutually similar data blocks or data packets within the input data (D1);(c) to employ a plurality of change symbols, for example a plurality of mask bits, to indicate changed and unchanged data elements of partial reoccurrences of data blocks or data packets within the input data (D1) and a change of data values of changed data elements; and(d) to encode the at least one reference symbol and the plurality of change symbols into the encoded data (E2). There are provided methods of using the encoder to encode input data (D1) to generate the corresponding encoded data (E2). Moreover, there are provided a corresponding decoder, and a corresponding method of decoding the encoded data (E2) to generate corresponding decoded data (D3).

Disclosed are methods and systems for significantly compressing sparse multidimensional ordered series data comprised of indexed data sets, wherein each data set comprises an index, a first variable and a second variable. The methods and systems are particularly suited for compression of data recorded in double precision floating point format.

An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

A semiconductor device configured to perform an A/D conversion of a wide range of signals is provided. A semiconductor device includes: an input voltage detection unit configured to detect an analog input voltage; a reference voltage setting unit configured to set a reference voltage based on the detected input voltage; an amplifier configured to amplify a difference between the input voltage and the reference voltage; an ADC configured to perform an A/D conversion of an amplified signal; and an arithmetic processing unit configured to calculate a digital voltage corresponding to the input voltage based on a result of the A/D conversion and the reference voltage.

A current source device having a current source array includes a plurality of current source units, a plurality of least significant bits, and a plurality of most significant bits. The current source units are arranged along a plurality rows and columns of a current source array. Each of the least significant bits includes a first amount of current source units is placed at the geometric center of the current source array. Each of the most significant bits includes a second amount of current source units. The second amount is the first amount multiplied by a positive integer. The two adjacent bits in the most significant bits are centrally symmetrical to the geometric center.

A converter includes: a terminal that receives code-modulated power that has been generated with a modulation code; and a circuit that intermittently converts the code-modulated power with a conversion code based on the modulation code. The code-modulated power is alternating-current power.

A computer-implemented method, system, and apparatus for storing binary data is disclosed. A processor receives a digital bit stream and transforms the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises a data message encoded by an OCTS-expanded table for storage. The processor stores the encoded digital bit stream on a digital data storage device or system.

Aspects of dynamic data compression selection are presented. In an example method, as uncompressed data chunks of a data stream are compressed, at least one performance factor affecting selection of one of multiple compression algorithms for the uncompressed data chunks of the data stream may be determined. Each of the multiple compression algorithms may facilitate a different expected compression ratio. One of the multiple compression algorithms may be selected separately for each uncompressed data chunk of the data stream based on the at least one performance factor. Each uncompressed data chunk may be compressed using the selected one of the multiple compression algorithms for the uncompressed data chunk.

An electronic apparatus and a method for detecting status of keys thereof are provided. The electronic apparatus comprises a key module, a key control circuit, a conversion circuit with calibration mechanism and a processor. The key control circuit detects whether any of keys in the key module is pressed. If the detection result is affirmative, the press status of each of the keys is scanned by the key control circuit to obtain a coarse scan result. The conversion circuit with calibration mechanism is configured to perform the other system function of the electronic apparatus. When the processor determines that at least one of the keys is not pressed according the coarse scan result, the conversion circuit with calibration mechanism is switched to assist a re-scan operation of the press status of the at least one of the keys.

For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine timing mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology utilizes cross-correlation of each DAC unit elements (UEs) output to the entire modulator output to measure its timing mismatch error respectively. Specifically, the timing mismatch error is estimated using a ratio based on a peak value and a value for the next tap in the cross-correlation function. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine switching mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology forces each DAC unit elements (UEs) to switch a certain amount times and then use the modulator itself to measure the errors caused by those switching activities respectively. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

Typically, complex systems require a separate and expensive equalizer at the output of an analog-to-digital converter (ADC). Rather than providing a separate equalizer, the effective Signal Transfer Function (STF) of a Multi-stAge noise SHaping (MASH) ADC can be modified by leveraging available digital filtering hardware necessary for quantization noise cancellation. The modification can involves adding calculations in the software previously provided for computing digital quantization noise cancellation filter coefficients, where the calculations are added to take into account equalization as well. As a result, the signal transfer function can be modified to meet ADC or system-level signal-chain specifications without additional equalization hardware. The method is especially attractive for high-speed applications where magnitude and phase responses are more challenging to meet.

Modifying a digital data stream that includes immediately consecutive code words of different length by segmenting, based on a certain block grid, the digital data stream. Each block of the block grid includes a fixed number of bits. It is determined whether all bits of the last block associated with the digital data stream are occupied by data of the digital data stream. If not all bits of the last block are occupied, the unoccupied bits of the last block are padded with bits of an end-of-record (EOR) indicator. If all bits of the last block are occupied, attaching an EOR indicator to the digital data stream is skipped.

The present invention relates to a modular photoelectric-switch keyboard key, including modular photoelectric switch, base, keymodule and elastic element, the said modular photoelectric switch is mounted in the said base, the said keymodule is slideably placed in the sliding cavity of the said base and the said elastic element is placed between the said base and the said keymodule; the said modular photoelectric switch comprises transmitting tube, receiving tube and distance piece, the said transmitting tube and the said receiving tube are placed oppositely and are electrically connected with the circuit board; the said distance piece is connected with the said keymodule and located between the said transmitting tube and the said receiving tube.

Continuous-time analog-to-digital converters (ADCs) such as continuous-time delta-sigma ADCs and continuous-time pipeline ADCs, has input resistor structure at the input. The input resistor structure is typically tunable, and the tunability is usually provided by metal-oxide semiconductor field effect transistor (MOSFET) switches. Core MOSFETs, which has a terminal-to-terminal voltage

For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.

A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power.

An analog to digital converter includes an error integration circuit configured to receive an input charge from a detector and to integrate a difference between the input charge and one or more feedback charge pulses to create an error voltage. A quantizer is in operable communication with the error integration circuit and is responsive to the created error voltage. An accumulator having a mantissa component and a radix component is in operable communication with the quantizer. A charge feedback device in operable communication with the quantizer and the radix component of the accumulator. The charge feedback device is configured to generate the one or more feedback charge pulses proportional to the radix component of the accumulator and an output of the quantizer. Digital focal plane read out integrated circuits including the analog to digital converter are also disclosed.

A probabilistic digitizer for extracting information from a Josephson comparator is disclosed. The digitizer uses statistical methods to aggregate over a set of comparator readouts, effectively increasing the sensitivity of the comparator even when an input signal falls within the comparator's gray zone. Among other uses, such a digitizer may be used to discriminate between states of a qubit.

For continuous-time multi-stage noise shaping analog to digital converters (CT MASH ADCs), quantization noise cancellation often requires estimation of transfer functions, e.g., a noise transfer function of the front end modulator. To estimate the noise transfer function, a dither signal can be injected in the front end modulator. However, it is not trivial how the dither signal can be injected, since the dither signal can potentially leak to the back end modulator and cause overall noise degradation. To address some of these issues, the dither signal is injected post the flash analog to digital converter (ADC) of the front end modulator. Furthermore, dummy comparator structures can be used to synchronize the dither with the quantization noise of the targeted flash ADC.

A circuit and a method for converting an analog signal to a digital value representation is disclosed. In one aspect, the circuit includes an incremental sigma-delta analog-to-digital converter (ADC). The circuit further includes a first input line for providing a primary analog signal representing a sensor measurement to the incremental sigma-delta ADC. The circuit further includes a second input line for providing a secondary analog signal to the incremental sigma-delta ADC. The incremental sigma-delta ADC receives the primary and secondary analog signals during a first period (TADC1) and a second period (TADC2), respectively. The circuit further includes a filter configured to weight the digital values in a sequence of digital values output by the incremental sigma-delta ADC, and to output a single digital value representing the sensor measurement.

A remote control for a wireless load control system, the remote control comprising: a housing having a front surface and an outer periphery defined by a length and a width; an actuator provided at the front surface of the housing; a wireless transmitter contained within the housing; and a controller contained within the housing and coupled to the wireless transmitter for causing transmission of a wireless signal in response to an actuation of the actuator, the wireless transmitter and the controller adapted to be powered by a battery contained within the housing; wherein the length and the width of the housing are slightly smaller than a length and a width of a standard opening of a faceplate, respectively, such that the outer periphery of the housing is adapted to be received within the standard opening of the faceplate when the housing and the faceplate are mounted to a vertical surface.

A semiconductor device having an analog/digital conversion circuit converting an analog signal to a digital signal, includes a holding circuit outputting an analog signal having a value according to a value of an analog signal supplied in a first period; and a prediction circuit generating a first digital signal based on bit position information from a prediction table corresponding to the supplied analog signal.

System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

A system of systems to monitor data for carbon flux, for example, at scales capable of managing regional net carbon flux and pricing carbon financial instruments is disclosed. The system of systems can monitor carbon flux in forests, soils, agricultural areas, body of waters, flue gases, and the like. The system includes a means to identify and quantify sources of carbon based on simultaneous measurement of isotopologues of carbon dioxide, for example, industrial, agricultural or natural sources, offering integration of same in time and space. Carbon standards are employed at multiple scales to ensure harmonization of data and carbon financial instruments.

A liquid separator system having a gas phase zone, an aqueous phase zone and a denser liquid zone is used to separate mixtures of fluids. The separator can be used for separating molten sulfur from liquid redox solution or reslurry water. The system includes a vessel with a top part and a bottom part. The vessel has a larger diameter at the top part than at the bottom part. The system also includes an inlet for introducing a redox solution or reslurry water and molten sulfur, which is denser than redox solution or reslurry water, into the vessel. An outlet near the bottom part of the vessel allows a flow of the molten sulfur from the vessel. An interface control structure senses an interface level between the redox solution or reslurry water and the molten sulfur, and the interface control structure controls the flow of molten sulfur from the outlet. The interface control structure is adjusted to optimally alter the vertical height of the interface level within the vessel so that the residence time of the molten sulfur in the vessel does not decrease as the sulfur production throughput decreases, and so that the interface area of the molten sulfur and the redox solution is reduced as the sulfur throughput decreases. A pressure controller monitors the pressure in the vessel and adds or removes gas from a gas phase zone in the vessel to maintain a predetermined pressure regardless of the vertical height of the interface.

A process is provided for recovering sodium chloride crystals and sodium carbonate decahydrate crystals from a concentrated brine that results from a gas mining operation where gas and produced water is recovered and the produced water constitutes a brine. An initial pre-concentration process is carried out where the brine is concentrated and in the process carbon dioxide is removed from the brine and at least some sodium bicarbonate is converted to sodium carbonate. In one process, the concentrated brine is directed to a sodium chloride crystallizer where the brine is heated and further concentrated to form sodium chloride crystals which are separated from the brine to yield a product and wherein the resulting brine is termed a first mother liquor. The first mother liquor is then directed to a sodium carbonate decahydrate crystallizer where the first mother liquor is cooled and concentrated resulting in the formation of sodium carbonate decahydrate crystals and a second mother liquor. The second mother liquor is split into two streams where one stream is directed back to the sodium chloride crystallizer while the other stream is wasted or further treated.

Method for producing a uranium concentrate in the form of solid particles, by precipitation from a uranium-containing solution using a precipitating agent, in a vertical reactor comprising a base, a top, a central part, an upper part, and a lower part, the solid particles of the uranium concentrate forming a fluidized bed under the action of a rising liquid current which circulates from the base towards the top of the reactor successively passing through the lower part, the central part and the upper part of the reactor, and which is created by introducing a liquid recycling current (flow) at the base of the reactor, said liquid recycling current being tapped at a first determined level (A) in the upper part of the reactor and sent back without settling to the base of the reactor, excess liquid being also evacuated via an overflow located at a second determined level (B) in the upper part of the reactor; a method in which the upper limit (C) of the fluidized bed of solid particles is controlled so that it is positioned at a level below the first and second determined levels.

The present invention relates to a process for the wet production of granules from powdered materials, in particular raw materials for the production of glass. The process of the invention comprises the following successive steps: (i) the powdered materials to be granulated are divided into at least two portions: a first portion and a second portion; (ii) a binder liquid is added to the first portion of powdered materials; (iii) the first mixture thus obtained is agglomerated in the granulator in order to obtain granules (a); (iv) the second portion of powdered materials is added to the granulator; and (v) the new mixture obtained is agglomerated in the granulator in order to obtain granules (b). This sequenced granulation process allows granules to be obtained that have a degree of moisture that assures their stability and their ease of handling eliminating the drying step.

The present invention relates to means and methods for producing crystals or crystalline substances. In particular, crystals or crystalline substances which are useful as pharmaceutical ingredients can be manufactured.

A rotating knife is disclosed for disintegrating a crystal bed formed in a washing column for processing suspension of solid particles in a liquid. The rotating knife is provided with a spoke support. The spoke support comprises at least two spokes. The relative angle of the spokes is between approximately 20° and approximately 80°.