A system, method and computer program product for avoiding a processing flaw in a computer processor triggered by a predetermined sequence of hardware events. The system may include a detecting unit and a power-on reset unit. The detecting unit detects that the predetermined sequence of hardware events is going to occur at the computer processor. The power-on reset unit initializes the computer processor to a state stored in computer memory in response to detecting the sequence of hardware events.

An apparatus includes a first memory, a second memory, a processor configured to perform an initialization process including adding data that generates a first error to initialization data and storing the initialization data together with the added data in the first memory to initialize the first memory, and a controller configured to perform an exchanging process including, when a second error occurs in the second memory during reading or writing data from or to the second memory, copying the data stored in the second memory into the first memory and switching, using a selector, a memory for use in writing and reading data from the second memory to the first memory. The processor is configured to read data from the first memory and the second memory and detect a failure of the selector or a failure of the exchanging process depending on whether the first error occurs or not.

In a computer storage system, crash dump files are secured without power fencing in a cluster of a plurality of nodes connected to a storage system. Upon an occurrence of a panic of a crashing node and prior to receiving a panic message of the crashing node by a surviving node loading, in the cluster, a capturing node to become active, prior to a totem token being declared lost by the surviving node, for capturing the crash dump files of the crashing node, while manipulating the surviving node to continue to operate under the assumption the power fencing was performed on the crashing node.

A method to prevent failure on a server computer due to internally and/or externally induced shock and/or vibration. The method includes acquiring, by at least one sensor, analog acceleration data of components in a server computer. The data is then converted to digital format and stored within a motor drive assembly processor memory unit. The processor analyzes the stored data for existence of machine degradation. In response to detecting the existence of machine degradation, the motor drive assembly processor initiates remediation procedures. The remediation procedures include controlling rotating speed of moving devices or performing a complete system shut down.

Embodiments relate to a computer implemented information processing system, method and program product for data access. The information processing system includes a data store having a top tier store and at least another tier store with the top tier store including a counter for each entry of a symbol and another tier store including a representative frequency value defined for the another tier store. A sorter is also provided configured to sort the symbol in the top tier store and the another tier stores according to a value generated in the counter for the assessed symbol. The said sorter is also configured to restore entry of the symbol in the top tier store, in response to a symbol having moved from said top tier store to another tier store, by using the representative frequency value defined for said another store to which said symbol was moved.

Memory devices adapted to repair single unprogrammable cells during a program operation, and to repair columns containing unprogrammable cells during a subsequent erase operation. Programming of such memory devices includes determining that a single cell is unprogrammable and repairing the single cell, and repairing a column containing the single cell responsive to a subsequent erase operation.

A double data rate memory physical interface having self checking loopback logic on-chip is disclosed. Disposed on the chip is a first linear feedback shift register, which is capable of generating a set of test data values that comprise at least two data bits. Also disposed on the chip is a second linear feedback shift register. The second linear feedback shift register is capable of generating a set of expected data values that match the test data values. Further, an internal loopback error check element is disposed on the chip. The internal loopback error check element is used to compare the set of expected data values with the set of test data values.

An apparatus is equipped with a storage device including an error correction circuit. The apparatus performs a test of the storage device according to a predetermined testing procedure, and records a time-point at which error correction of the storage device has been performed by the error correction circuit during performance of the test. The apparatus determines, with predetermined accuracy, a first position within the storage device on which the error correction has been performed, based on a test speed at which the test is performed, a time-period from the time-point to current time, and a second position within the storage device on which the test is being performed at the current time. Then, the apparatus performs the test predetermined times on a range included in the storage device and including the first position, according to a testing procedure that has been used at the time-point.

Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.

A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to one or more Test Wrappers via an interconnect fabric. The Test Wrappers interface with one or more IP test ports to provide test data, control, and/or stimulus signals to the IP blocks to facilitate circuit-level testing of the IP blocks. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. Test wrappers may also be configured to test multiple IP blocks comprising a test partition.

In a wireless communication system, a compact control signaling scheme is provided for signaling the selected retransmission mode and codeword identifier for a codeword retransmission when one of a plurality of codewords being transmitted over two codeword pipes to a receiver fails the transmission and when the base station/transmitter switches from a higher order channel rank to a lower order channel rank, either by including one or more additional signaling bits in the control signal to identify the retransmitted codeword, or by re-using existing control signal information in a way that can be recognized by the subscriber station/receiver to identify the retransmitted codeword. With the compact control signal, the receiver is able to determine which codeword is being retransmitted and to determine the corresponding time-frequency resource allocation for the retransmitted codeword.

A method and user equipment for simultaneous transmission of a first set of information bits and a second set of information bits by a user equipment, either separately encoded utilizing transmit power or rate matching to increase successful decoding of a set of information bits, or jointly encoding using a priori knowledge or bit positioning to increase successful decoding. Also, the use of joint coding where a first set of information bits is encoded first and then encoded with a second set of information bits, and modulation symbol mapping are provided.

Method and apparatus for managing data in a memory. In accordance with some embodiments, a first data object and an associated first ECC data set are generated and stored in a non-volatile (NV) main memory responsive to a first set of data blocks having a selected logical address. A second data object and an associated second ECC data set are generated responsive to receipt of a second set of data blocks having the selected logical address. The second data object and the second ECC data set are subsequently stored in the in the NV main memory responsive to a mismatch between the first ECC data set and the second ECC data set.

Embodiments of the present invention relate to an apparatus, method, and/or sequence for a distributed ECC that may be used in a storage system. In another embodiment of the invention, an apparatus for handling distributed error correction code (ECC) operations, includes: a plurality of ECC engines configured to perform ECC operations in parallel on multiple data parts; the plurality of ECC engines distributed in parallel to receive some of the multiple data parts that are read from storage media devices and to receive some of the other multiple data parts that are to be written to the storage media devices; and the plurality of ECC engines configured to use respective ECC bytes corresponding to respective ones of the multiple data parts.

Within a radio communication network infrastructure transmitting data organized into a sequence of symbols to a receiving device over a plurality of radio links, data to be transmitted is encoded according to an error correction coding scheme in order to produce a set of systematic symbols and a set of corresponding redundancy symbols; the systematic symbols and a first subset of the corresponding redundancy symbols are transmitted, over a first radio link among said plurality of radio links, in broadcast mode, and a second subset of the corresponding redundancy symbols, distinct from the first one, is transmitted over a second radio link among said plurality of radio links.

A method of transmitting data according to a data transmission protocol wherein the data is transmitted as a plurality of data frames and each data frame includes an error checking field comprising at least two sub-fields, the data of the first sub-field being formed by a first error checking method performed on data of the frame and the data of the second sub-field being formed by a second error checking method performed on the said data of the frame, the first and second methods being such that the data of the first sub-field has different error checking properties from those of the data of the second sub-field.

According to one embodiment, a memory controller includes: a first flash encoding unit that performs flash encoding on user data according to a first scheme to generate user data flash codes; an encoding unit that performs an error correction encoding process on the user data flash codes to generate parities; a second flash encoding unit that performs flash encoding on the parities according to a second scheme to generate parity flash codes; and a memory I/F that writes the user data flash codes and the parity flash codes to the nonvolatile memory.

A logical operations functional block for an execution unit of a processor includes a first input data link for a first operand and a second input data link for a second operand. The execution unit includes a register connected to an error correction code detection unit. The logical operations functional block includes a look-up table configured to receive an error correction code syndrome from the error correction code detection unit. The logical operations functional block also includes a multiplexer configured to receive an output signal from the look-up table at a first input and the first operand at a second input, wherein an output of the multiplexer is coupled to the first input data link of a logical functional unit.

Embodiments of apparatus and methods for error detection and correction are described. A codeword may have a data portion and associated check bits. In embodiments, one or more error detection modules may be configured to detect a plurality of error types in the codeword. One or more error correction modules coupled with the one or more error detection modules may be further configured to correct errors of the plurality of error types once they are detected by the one or more error detection modules. Other embodiments may be described and/or claimed.

A nonvolatile memory is configured with blocks as deletion units, each block having several pages that are configured as write units. A controller for the nonvolatile memory includes an error correcting circuit, which detects and corrects an error in data read out of a page in one of the blocks of the nonvolatile memory, the page being referenced by a logical address. The controller also determines an error occurrence when the error cannot be corrected. An error block table is provided to store the logical address where the error occurred, and a physical address corresponding to the logical address.

Data is compressed using content addressable memory without disruption despite error using a plurality of content addressable memories to detect sequentially repeating data elements of the data. Compression information is generated for each sequence of repeating data elements that repeat for at least a compression threshold without any one of the plurality of content addressable memories generating an indication of an error for a matching content addressable memory entry. Individual data elements are output for each of the data elements that do not repeat for the compression threshold. Compression information is generated for each sequence of repeating data elements that repeat for at least the compression threshold and then generating a currently searched data element that matches the repeating data elements when any one of the plurality of content addressable memories generates an indication of an error for a content addressable memory entry that matches the currently searched data element.

A method of operating a memory controller to control a memory device includes reading a read vector from the memory device and correcting one or more errors in the read vector, where a power consumed at the correcting is varied according to the number of errors in the read vector.

A method includes determining a read threshold voltage corresponding to a group of storage elements in a non-volatile memory that includes a three-dimensional (3D) memory of a data storage device. The method also includes determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage. The method includes comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event.

A memory device includes a memory chip that stores data, and an external controller that controls the memory chip. The memory chip includes multiple memory cells configured to store data of two or more bits; and an internal controller that executes a program operation for page data including a lower and an upper page program operation, and executes a read operation for page data including a lower and an upper page read operation. The external controller includes an error correction unit that performs error correction encoding on data to be programmed into the memory cell array and performs error correction decoding on data. The internal controller outputs the read page data from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation.

Methods and systems for in-place updating original content stored in a non-volatile storage device and for yielding updated content. Some of the described embodiments illustrate the possibilities for reduction in storage operations, storage blocks, and/or update package size. Some of the described embodiments include the writing of error recovery result(s) such as XOR result(s) which enable the recovery of data in case of an interruption of the update process. In some of the described embodiments, there is re-usage of a protection buffer containing content which is required in the update process.

Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for decoding codewords using a side channel. In various embodiments, a memory controller may be configured to determine that m of n die of non-volatile memory (“NVM”) have failed iterative decoding. In various embodiments, the memory controller may be further configured to generate a side channel from n-m non-failed die and the m failed die other than a first failed die. In various embodiments, the memory controller may be further configured to reconstruct, using iterative decoding, a codeword stored on the first failed die of the m failed die based on the generated side channel and on soft input to an attempt to iteratively decode data stored on the first failed die. In various embodiments, the iterative decoding may include low-density parity-check decoding. Other embodiments may be described and/or claimed.

A packet transmission/reception apparatus and method is provided. The packet transmission method of the present invention includes acquiring a source payload including partial source symbols from a source block, generating a source packet including the source payload and an identifier (ID) of the source payload, generating a repair packet including a repair payload corresponding to the source payload and an ID of the repair payload, generating a Forward Error Correction (FEC) packet block including the source and repair packets, and transmitting the FEC packet block. The source payload ID includes a source payload sequence number incrementing by 1 per source packet. The packet transmission/reception method of the present invention is advantageous in improving error correction capability and network resource utilization efficiency.

A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism.

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate coding in a data processing system.

The present invention discloses a method and apparatus for processing and error correction of a GFP-T superblock, where the 64 bytes of payload data of a first superblock are buffered in the first page of a two-page buffer. The flag byte is buffered in a separate buffer, and a CRC operation is performed in a separate logic element. The result of the CRC operation is checked against a single syndrome table which may indicate single- or multi-bit errors. As the payload data of the first superblock is processed and read out of the first page of the two-page buffer, the payload data of a second superblock is written into the second page of the two-page buffer to be processed and corrected.

A method for decoding and checking a tail-biting convolutional code is provided. The method fully utilizes structural features of the tail-biting convolutional code to re-sort Log-Likelihood Ratio (LLR) values input into a decoder, and by reconstructing a derivative generator polynomial of a convolutional code, allows the decoder to output in serial according to a normal ordering of information bits during backtracking, that is, a first bit of an information sequence is first decoded successfully. Thus, CRC checking may be activated as soon as possible, so that part of the backtracking process and the CRC checking may be performed in parallel, thereby achieving the objective of reducing a processing time delay in decoding and checking the tail-biting convolutional code.

A method is provided for receiving a signal. The method includes receiving a signal transmitted in a radio frequency (RF) band including at least one RF channel, demodulating the received signal, parsing a preamble of a signal frame including layer-1 information from the demodulated signal, deinterleaving bits of the layer-1 information, decoding the deinterleaved bits using an error correction decoding scheme including a shortening scheme and a puncturing scheme and obtaining physical layer pipes (PLPs) from the signal frame using the error-correction-decoded layer-1 information.

Generating error data associated with decoding data is disclosed, including: processing an input sequence of samples associated with data stored on media using a detector and a decoder during a global iteration; and generating one or more error values based at least in part on one or more decision bits output by the detector or the decoder and the input sequence of samples.

A method begins by a processing module obtaining common storage name information regarding data that is stored in storage units of a distributed storage network (DSN) as a set of data slices. Each data slice of the set of data slices has a unique storage name, where each of the unique storage names for the set of data slices has common naming information regarding the data. The method continues where the processing module interprets the common storage name information to determine whether a difference exists between the common naming information of a data slice of the set of data slices and the common naming information of other data slices of the set of data slices. When the difference exists, the method continues where the processing module indicates a potential storage error of the data slice and implements a storage error process regarding the potential storage error of the data slice.

The present disclosure relates to a method for detecting a parity error in a sequence of DQPSK symbols of a digital transmission system, comprising determining a first demodulated symbol r1; determining a second demodulated symbol r2; determining a first parity symbol p1; determining a second parity symbol p2; determining a super-parity symbol q1; and detecting a parity error in the sequence of DQPSK symbols by comparing a combination of the first parity symbol p1 and the second parity symbol p2 against the super-parity symbol q1, wherein a parity between two DQPSK symbols describes a phase difference between the two DQPSK symbols.

An error control encoding system produces a codeword from a data word, where the resulting codeword includes the data word and three or more parity segments produced using the data word. The system includes a first encoder to encode the data word in two or more first data segments in order to produce two or more first parity segments, where each of the two or more first data segments includes a respective sequential portion of the data word. The system includes a second encoder to encode the data word in one or more second data segments in order to produce a corresponding one or more second parity segments, where each of the one or more second data segments includes a respective sequential portion of the data word, and each of the one or more second data segments also includes a sequential portion of the data included in a plurality of the two or more first data segments. Further, the system includes a controller configured to provide the two or more first data segments of the data word to the first encoder for encoding and to provide the one or more second data segments of the data word to the second encoder for encoding.

A wireless communication system including a sender apparatus having a plurality of transmitting antennas that performs MIMO transmission of a plurality of data blocks; and a receiver apparatus that receives the plurality of data blocks. The sender apparatus transmits a process number via a control channel different from a data channel to the receiver apparatus, and wherein when the MIMO diversity transmission is performed, the receiver apparatus performs HARQ processing in the received data blocks based on not a process number which prevents the data blocks from competing but the received process number from the sender apparatus.

It is provided a computer comprising a nonvolatile memory for storing data, a control processor for controlling the saving of data into the nonvolatile memory, and a battery for supplying power to the computer in case of a failure of an external power supply, wherein the control processor checks a charge amount stored in the battery, calculates an amount of data which can be saved in the nonvolatile memory by the battery in case of a failure of the external power supply based on the checked charge amount, and saves data excluding the amount of data that can be saved, out of data which should be saved into the nonvolatile memory, into the nonvolatile memory in advance.

Example embodiments relate to a bad area managing method of a nonvolatile memory device. The nonvolatile memory device may include a plurality of memory blocks and each block may contain memory layers stacked on a substrate. According to example embodiments, a method includes accessing one of the memory blocks, judging whether the accessed memory block includes at least one memory layer containing a bad memory cell. If a bad memory cell is detected, the method may further include configuring the memory device to treat the at least one memory layer of the accessed memory block as a bad area.

The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more methods can include, for example: receiving a number of sectors of data to be written to a number of memory devices; appending first metadata corresponding to the number of sectors and including first integrity data to the number of sectors, the first metadata has a particular format; generating second integrity data to be provided in second metadata, the second integrity data corresponding to at least one of the number of sectors (wherein the second metadata has a second format); and generating third integrity data to be provided in the second metadata, the third integrity data including error data corresponding to the second integrity data and the at least one of the number of sectors.

The present invention relates to a method for the degradation of pollutants in water and/or soil. More specific, the present invention relates to a method for the on-site decontamination or re-mediation of water and/or soil which are contaminated with organic compounds. Moreover, the invention relates to a method for forming a barrier against the spreading of a contamination with pollutants within the water and/or soil, especially within groundwater (aquifer). Further, the invention relates to means for use in these methods, and to the production of such means.

The invention relates to a hardenable dental composition comprising component (A) comprising a cationically hardenable compound, component (B) comprising an initiator being able to initiate the hardening reaction of the cationically hardenable compound, and component (C) comprising a filler, wherein the filler comprises a filler body and a filler surface, the filler surface comprising side groups with polar moieties. The invention also relates to a process of producing the dental composition, to the use of the dental composition as dental impression material and to a method of taking an impression of dental tissue.

The invention relates to the treatment of carbonaceous radioactive waste, comprising the delivery of waste to one or more radioactive isotope separation stations isotopes, said isotopes being among at least carbon 14, chlorine 36, and tritium. Advantageously, the delivery to each of the stations occurs in wet form, with water being a common medium for conveying the waste to each of the separation stations.

Containment systems and methods safely and permanently encapsulate a sharp portion of a sharp medical instrument (e.g. a hypodermic needle). The containment system includes a cap or other container formed of a durable and flexible material having a rim defining an open end configured to receive a sharp portion therein, an interior surface, wherein at least a portion of the interior surface comprises a puncturing element, and a bladder contained within the cap proximate the puncturing element, the bladder containing a first component of a liquid hardenable solution. Opposing sides of the cap can be deformed under external pressure to cause the puncturing element to puncture the bladder so as to release the first component of the liquid hardenable solution from the bladder such that the first component contacts the sharp portion and the sharp portion is substantially permanently retained inside the cap by the liquid hardenable solution.

Containment systems and methods safely and permanently encapsulate a sharp portion of a sharp medical instrument (e.g. a hypodermic needle). The containment system includes a cap or other container formed of a durable and flexible material and having a rim defining an open end configured to receive the sharp portion therein and an adhesive disposed on an interior surface of the container. The method of use includes inserting the sharp medical instrument into the container, and compressing the sides of the container to permanently encapsulate the sharp portion of the medical instrument within the adhesive. The adhesive may be an adhesive tape and may be protected before use by a covering, which may be removed at the time of use by pulling a pull tab extending from an opening in the container.

A method of disposing nuclear waste in underground rock formations is presented. The method includes the steps of selecting a land area having a rock formation positioned there-below of a depth able to prevent radioactive material placed therein from reaching the surface and drilling a vertical wellbore from the surface, to a depth ranging between 5,000 feet and 25,000 feet, into the underground rock formation or repository. A plurality of horizontal laterals or horizontal wellbores, ranging in length from 500 feet to 40,000 feet, are drilled from the vertical wellbore into the underground rock formation or repository. Nuclear waste to be stored within these laterals is encapsulated in a special waste canister and these nuclear waste canisters are positioned within the horizontal laterals wherein they are sealed to prevent loss and leakage. Means are also provided by which these canisters are adapted to allow retrievability of the canisters from the wellbore at a later date and to return the waste to the surface for use after retrieval.

Certain exemplary embodiments can provide a system, machine, device, manufacture, circuit, composition, and/or user interface adapted for and/or resulting from, and/or a method and/or machine-readable medium comprising machine-implementable instructions for, activities that can comprise and/or relate to, in a treatment zone, reacting an oxygen-comprising gas, one or more selected ferric/ferrous chelates, one or more selected nitrates and/or nitrites, and/or anaerobic wastewater.

A process for the conversion of biomass to hydrocarbon products such as transportation fuels, kerosene, diesel oil, fuel oil, chemical and refinery plant feeds. The instant process uses a hydrocarbon or synthesis gas co-feed and hot pressurized water to convert the biomass in a manner commonly referred to as hydrothermal liquefaction.

Method of extracting syngas between the zone in a furnace where oxygen-starved combustion of biomass occurs and the zone in the furnace where secondary air is added to complete combustion, conditioning and cleaning the extracted syngas, and delivering it in a metered amount to the oxidizer or upstream of the oxidizer to reduce or eliminate the need for additional fossil fuels once the oxidizer has achieved its operating temperature. The gasifier or furnace burns solid waste and produces a syngas containing relatively high levels of CO, which is extracted from the furnace, conditioned, and introduced into an RTO as a fuel source. In certain embodiments, no extraction of syngas from the furnace takes place; the furnace conditions are manipulated so that normally undesirable levels of CO and other VOC's remain in the process stream. The heat from the furnace is used as intended (e.g., to heat a dryer), the stream is conditioned, and ultimately proceeds to a downstream RTO. Since the gas stream remains rich in CO and VOC's, its fuel value in the RTO is substantially higher than otherwise would be the case.

An environmentally beneficial process for utilizing waste drill cuttings from oil and gas exploration. The waste drill cuttings (20) are used as a filler and combined with plastic to provide a plastic based product (26) in the plastics industry. In an embodiment the cuttings are thermally treated and formed into pellets. In a further embodiment the cuttings are treated and mixed with recycled plastic to be formed into pellets. The pellets are then used in the manufacture of rigid plastic products such as bollards, planters, benches and decking.