Disclosed herein is a method of controlling drainage of wash water remaining in a washing machine. The method includes draining wash water from a tub to an outside of the washing machine, supplying wash water into the washing machine after the draining wash water, and re-draining the wash water to the outside of the washing machine after the supplying wash water.

A washing machine and a control method thereof to achieve washing performance using bubbles without damage to fiber structures of functional clothes. When a washing course of functional clothes is selected, a motor is frequently rotated at a period of a predetermined time or less, causing the clothes to uniformly adsorb the water. Thereafter, bubbles are generated and applied to the clothes. A drive operation rate of the motor is raised stepwise to wash the clothes to which the bubbles have been applied, so as to effectively remove sweat, contaminants, or the like contained in the clothes.

Provided is a method for washing laundry in a washing machine, wherein the washing machine includes a tub and a drum disposed inside the tub, the method comprising: supplying wash water into the tub; rotating the drum such that the laundry is attached the drum and spraying the wash water changed to whirling water into the drum; and draining the wash water from the tub.

A process obtains an aged or faded effect on garments made of protein fibers such as wool, cashmere and silk. Granules of inert materials, which are particularly light in order not to damage very fine fibers, are introduced into a tumbler. The garments were previously treated with a chemical product commonly referred to as “dye retardant” for inhibiting dyeing of the fabric. The tumbler is pre-arranged so that the chemical product does not migrate through holes or openings. Raw confectioned garments that are to be treated, such as jerseys or outerwear, are introduced into the tumbler. The garments are extracted from the tumbler at the end of migration of the chemical product for inhibiting dyeing of the outer surface of the garments by the granules and steamed in an autoclave to fix the chemical process of the product for inhibiting dyeing of the outer surface of the garments. The garments are then dyed with a specific selection of dyes that must be defined each time according to the desired result.

The invention relates to a selective dyeing method used for dyeing a substrate (10), selectively within a first exposed surface portion (S1) of said substrate. For this purpose, the substrate consists of a material (2) that is impervious to a dye with the exception of the first portion of the exposed surface. In particular, the impervious material can form a layer which covers a base portion (3) of the substrate in a second portion (S2) of the exposed surface. The substrate is heated such that the dye (C) penetrates a pervious material (1) which constitutes the first portion of the exposed surface. The method is particularly useful for eliminating light diffused by the walls of a multilayer structure which is supported by means of ocular glass.

A DTS system resistant to radiation induced attenuation losses during the service life of an installation at both low and high temperatures using matched multi-wavelength distributed temperature sensing automatic calibration technology in combination with designed Pure Silica Core (PSC) optical fibers and an in process photo bleaching method provided by the light sources of the distributed temperature sensing system.

Disclosed is a drum type washing machine having a touch up function and a method for touching up thereof. The drum type washing machine having the touch up function is provided with a touch up button for removing wrinkles on laundry left in the drum type washing machine and a method for touching up. Accordingly, it is not required for a user to additionally execute rinsing and dehydrating processes, or ironing so as to remove wrinkles on the laundry, thus it is convenient. And, since it is not required to additionally execute the rinsing and dehydrating processes, it is capable of preventing unwanted consumption of water and electricity.

Appliances having a detergent dispenser that may be flushed with a water flow for removal of residual treating chemistry while reducing sudsing are disclosed. An example dispenser includes a cup with a bottom wall, a siphon tube projecting upwardly from the bottom wall, a cover for the siphon tube, an opening configured to introduce a liquid stream into the cup from a position above and beyond a periphery of the cover, wherein substantially all of the liquid stream flows downwardly along a trajectory defined by the opening and terminating below and within the periphery of the cover, and wherein the liquid stream directly impinges a portion of at least one of the cup or the siphon tube below the cover.

The invention provides a method and formulation for cleaning a soiled substrate, the method comprising the treatment of the moistened substrate with a formulation comprising a multiplicity of polymeric particles, wherein the formulation is free of organic solvents. Preferably, the substrate is wetted so as to achieve a substrate to water ratio of between 1:0.1 to 1:5 w/w. Optionally, the formulation additionally comprises at least one cleaning material and, in this embodiment, it is preferred that the polymeric particles are coated with the at least one cleaning material. Preferably, the cleaning material comprises a surfactant, which most preferably has detergent properties. Most preferably, the substrate comprises a textile fiber. Typically, the polymeric particles comprise particles of nylon, most preferably in the form of nylon chips. The results obtained are very much in line with those observed when carrying out conventional dry cleaning processes and the method provides the significant advantage that the use of solvents, with all the attendant drawbacks in terms of cost and environmental considerations, can be avoided.

The present disclosure therefore relates to a method for lightening keratin materials, in which the following are used: (a) a direct emulsion (A) comprising at least one fatty substance in an amount greater than 25% by weight, such as greater than 50%, at least one surfactant; at least one alkaline agent and an amount of water greater than 5% by weight, of the total weight of the emulsion, (b) a composition (B) comprising at least one oxidizing agent. It also relates to a multi-compartment device comprising, in one compartment, an emulsion (A), in another compartment a composition (B) comprising at least one oxidizing agent.

A photoresist composition includes a binder resin combined with a black dye, a monomer, a photo-polymerization initiator and a remainder of a solvent.

Novel compounds based on distyryl-biphenyl are provided. The compounds conform to the general structure The compounds are useful as optical brighteners. Compositions, such as laundry care compositions, containing such compounds are also provided.

As associative thickener obtainable by free radical polymerization, the preparation thereof and the use thereof in paper coating slips are described. The associative thickener is formed from (a) acid monomers selected from ethylenically unsaturated C3- to C8-carboxylic acids, (b) associative monomers of the general formula H2C═CR1—COO-(EO)n—(PO)m—R2, in which R1 is hydrogen or methyl, n is a number of at least two, m is a number from zero to 50, EO is an ethylene oxide group, PO is a propylene oxide group and R2 is a C8-C30-alkyl group or a C8-C30-alkaryl group, and (c) nonionic, copolymerizable monomers differing from a) and b), the reaction product having been reacted, after the polymerization, with initiators forming nonionic radicals.

The present invention provides dye mixtures containing at least one dye of formula (I) and at least one dye of formula (II) where T1, T2, R1 to R9 and n are each as defined in claim 1, processes for their preparation and their use.

The present invention relates to new azo dyes, a process for their preparation, and their use for dyeing or printing fibrous materials, to produce materials with brownish shades.

A bluing composition concentrate comprises an aqueous medium and at least one colorant that exhibits a blue or violet shade when deposited onto a textile material. The concentrate can be used to produce a bluing composition, and the bluing composition can be used to treat textile materials in such a way as to decrease the visually-perceived yellow coloration of textile articles that can occur with repeated use and laundering.

The present invention relates to a cosmetic composition for dyeing keratin fibers, in particular human keratin fibers such as the hair, comprising: a) one or more fatty substances; b) one or more surfactants; c) one or more oxidation bases; d) one or more couplers based on 2-hydroxynaphthalene derivatives or particular phenol derivatives, acylaminophenol derivatives or quinoline derivatives; f) one or more basifying agents; e) optionally one or more chemical oxidizing agents; and the fatty substance content representing in total at least 25% by weight relative to the total weight of the formulation. The present invention also relates to a process using this composition, and to a multi-compartment device that is suitable for performing the said process.

The present invention relates to a hair dye composition, and more particularly, to a foam-type hair dye composition comprising: a first agent including a dye and an alkaline agent and a second agent including an oxidant; and a nonionic viscosity increasing agent of a PEG-aliphatic acid ester or a PPG-aliphatic acid ester in one or both of the first agent and the second agent, thereby largely improving dyeing properties without dripping after the composition is coated on hair.

The present application provides preparations for changing the color of keratinic fibers, containing in a cosmetically acceptable carrier, at least one color-changing agent, at least one soap, at least one non-ionic surfactant of formula (I), in which R1 denotes an alkyl or alkenyl residue having 5 to 21 carbon atoms, R2 denotes a C2-C4 monohydroxyalkyl residue, and R3 denotes hydrogen, a C1-C4 alkyl residue or a C2-C4 monohydroxyalkyl residue, and at least one propellant wherein the preparation is in the form of a foam, and a proportion of gas in the foam is at least 50% by volume.

Concentrated cleaning formulations for removing debris from hard surfaces and textile surfaces. An exemplary formulation includes a mixture of the following chemical components, in specified proportions: glycerin;monopropylene glycol;triethylene glycol methyl ether;a non-ionic surfactant;an emulsifier;soya methyl ester or canola methyl ester, or both; andhydroxypropyl sulfonate; The formulation is free of water other than insignificant amounts present in the chemical components combined to make the mixture. Combining the formulation with water causes a temperature of the combination to increase above the temperatures of the water and the formulation before combining.

A control method of a laundry machine is disclosed. The control method of a laundry machine comprising a balancer includes an unbalance sensing step, wherein the unbalance sensing step recognizes an unbalancemaximum value and an unbalanceminimum value of an unbalance wave and the unbalance sensing step determines an average value of the two unbalance maximumvalue and unbalanceminimum value to be of the unbalance generated in a drum provided in the laundry machine.

A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.

A charge pump circuit includes a capacitor, a first switch between the capacitor and a power supply terminal, a second switch between the capacitor and an output terminal, a third switch between the output terminal and the capacitor, a fourth switch between the capacitor and a ground terminal, and a control unit configured to generate control signals for the switches. The control signals include first signals generated during a first period that cause first and third switches to be in an ON state and second and fourth switches to be in an OFF state, second signals generated during a second period that cause first and third switches to be in an OFF state and second and fourth switches to be in an ON state, and third signals generated between the first and second periods, that cause the ON/OFF state of each of the switches to be switched at different times.

A control switch is connected to a power supply voltage and turns on based on a control signal to output a current. A clamp circuit is connected to a load and performs clamp control of the output voltage of the control switch. A current control element conducts or shuts off a current based on the output voltage to be clamp-controlled. A selector switch group includes switches, and performs switching based on a voltage varying with the current control by the current control element, thereby switching between paths for generating an internal power supply. The switch circuit connects or disconnects the coupling between the clamp circuit and the selector switch group.

An electrical circuit includes: at least one inductor, at least one varactor, and at least two transistors, all of which electrically arranged to form a voltage controlled oscillator (VCO) having an oscillation frequency; wherein the at least two transistors includes a first transistor and a second transistor; wherein the first transistor has a first bulk terminal and a first parasitic diode disposed between the first bulk terminal and the first transistor; wherein the second transistor has a second bulk terminal and a second parasitic diode disposed between the second bulk terminal and the second transistor; wherein application of a first control voltage to the first bulk terminal, application of a second control voltage to the second bulk terminal, or application of first and second control voltages to the first and second bulk terminals, respectively, is effective to change the oscillation frequency of the VCO.

An active filter device and a circuit arrangement comprising an active filter device are disclosed. In an embodiment the active filter device includes sensor terminals for applying a sensor signal depending on a sensed noise signal, an output terminal for providing a correction signal that is suitable for reducing the noise signal, a signal source adapted for generating a correction signal and a high-pass filter coupled between the sensor terminals and the signal source, wherein the correction signal is generated with a dependence on a high-pass filtered sensor signal.

An SR latch circuit with single gate delay is provided. The circuit has an an enable input and an SR latch. There is first input stage having an input for receiving a set input and having an output for producing a first component of the SR latch circuit output, the first input stage having only one transistor that receives the enable input, the first input stage becoming transparent while enabled, the first input stage having a single gate delay between the input of the first input stage and the output of the first input stage. There is a second input stage having an input for receiving a reset input and having an output for producing a second component of the SR latch circuit output, the second input stage having only one transistor that receives the enable input, the second input stage becoming transparent while enabled, the second input stage having a single gate delay between the input of the second input stage and the output of the second input stage.

A semiconductor device includes a first transistor and a clamping circuit. The first transistor is arranged to generate an output signal according to a control signal. The clamping circuit is arranged to generate the control signal according to an input signal, and to clamp the control signal to a predetermined signal level when the input signal exceeds the predetermined signal level.

A system includes a voltage-controlled oscillator (VCO) to generate an output signal based on an input voltage and a multi-stage delay network to receive the output signal from the VCO. Each stage of the delay network produces a phase-shifted output signal. The system includes a multi-stage digital-to-analog converter (DAC) network, where each stage of the DAC network is associated with a corresponding stage of the delay network. Each stage of the DAC network receives the phase-shifted output signal from its corresponding stage of the delay network and generates a weighted output signal based on the received phase-shifted output signal. The DAC network combines the weighted output signal of each stage. A weighting factor for each stage of the DAC network is selected to reduce harmonic content of the combination of weighted output signals.

The present disclosure relates to a delay control circuit arranged for adding delay to a signal. The delay control circuit includes a driver circuit arranged to receive a first signal and to output a second signal. The driver circuit includes a variable load arranged for outputting the second signal by adding delay to the first signal. The delay control circuit also includes a control circuit arranged to receive the first signal and to control the variable load of the driver circuit based on a current state of the first signal and on a control signal indicative of an amount of delay to be added to the first signal in the current state.

A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.

A load-driving circuit for receiving a supply of power from a power source and driving a load, wherein the load-driving circuit is provided with: a high-side switching element; a low-side switching element; a high-side current detection circuit connected in parallel to the high-side switching element, the high-side current detection circuit detecting a high-side driving current; and a fault detection circuit for detecting the fault state of the load-driving circuit from the output result of the high-side current detection circuit. The high-side current detection circuit is provided with a high-side sense switching circuit operating in response to a gate signal that is different from the high-side switching element, the high-side sense switching circuit comprising a device of the same type as the high-side switching element. The output result of the high-side current detection circuit, the gate signal of the high-side switching element, and the gate signal of the high-side sense switching element are input and the fault states are detected apart from each other when the connection terminal between the load-driving circuit and the load is in a state of short circuit with the positive electrode side of the power source or in a state of short circuit with the negative electrode side of the power source.

A track and hold circuit comprises an input buffer amplifier, a unit gain amplifier module, a sampling switch, a drive triode and a sampling capacitor. The input buffer amplifier receives an input signal. In a track phase, the sampling switch is electrically connected to an emitter electrode of the drive triode; the input signal charges the sampling capacitor after being buffered by the input buffer amplifier, amplified without distortion by the unit gain amplifier module and driven by the drive triode. In a hold phase, the sampling switch is electrically connected to a base electrode of the drive triode; the base voltage of the drive triode is pulled down until the drive triode is cut off; electrical charges on the sampling capacitor are thereby held, causing the signal to be held on the sampling capacitor.

A high-voltage electronic switch includes first and second transistors defining a current flow path between an input and output of the switch. The transistors have a common point of the current flow path and a common control terminal. A control circuit includes a voltage line receiving a limit operating voltage and first and second branches coupled between the voltage line and the common point and common control terminal, respectively. Further transistors are activated, upon turning-off of the first and second transistors, for coupling the branches to the voltage line. The branches include a parallel connected resistor, diode, and string of diodes with opposite polarities. The diode of the first branch plus string of diodes of the second branch and diode of the second branch plus string of diodes of the first branch provide coupling paths between the voltage line and, respectively, the common point and common control terminal.

Capacitors connected between gate terminals of a plurality of parallel-connected power transistors are charged and discharged in each switching cycle to provide a plurality of power transistor control waveforms from a single gate driver waveform that equalize power losses/temperatures or steady-state currents among the plurality of power transistors. The capacitors are charged to different voltages by diverting current from one transistor driver by disabling another power transistor driver at different respective times in response to measured transient or steady state current or temperature or other operational parameter.

An integrated circuit includes a drive circuit with a first inverter circuit with a first transistor of a first conductivity type and a second transistor of a second conductivity type. The drains of the first and second transistors are connected. An output circuit is provided having a third transistor of the second conductivity with a gate connected to the drains of the first and second transistors. A capacitor is connected between the gate and a drain of the third transistor and has a capacitance greater than 0.5 pF and less than or equal to 3.0 pF. A gate width of the first transistor when divided by a gate width of the third transistor has a value of less than 1/100. The output circuit is configured to output a transmission signal from the drain of the third transistor.

A solid state power control apparatus includes: (a) at least one IGBT and at least one FET, for supplying current to a load, and (b) a current controller for shutting off the IGBT and FET. The current controller is arranged to start shut off of the IGBT before it starts shut off of the FET. Further, the current controller is arranged to reduce current flow prior to start of the turn off of the IGBT and FET.

A signal transfer circuit may include a pass gate coupled between first and second nodes; and a control unit suitable for controlling the pass gate to prevent a current flowing from the second node to the first node during turn-on of the pass gate.

A sampling circuit for sampling an input voltage and generating an output voltage, comprising six switches, a capacitor and a voltage buffer. The first switch has a control terminal and makes the output voltage equal to the input voltage when switching on. The second switch is coupled to a first terminal of the capacitor and a first level. The third switch is coupled to a second terminal of the capacitor and a second level. The fourth switch is coupled to the first terminal of the capacitor and the control terminal. The fifth switch is coupled to the control terminal and the second level. The voltage buffer has large input impedance, and has an input receiving the input voltage, an output providing a voltage equal or close to the input voltage. The sixth switch is coupled to the second terminal of the capacitor and the output of the voltage buffer.

A duty cycle correction circuit may include: a phase mixing section capable of mixing a first integrated signal generated by integrating a positive clock signal, with a first compensation signal generated by differentiating and integrating the positive clock signal and a negative clock signal, respectively, to generate a first phase-mixed signal, and mixing a second integrated signal generated by integrating the negative clock signal, with a second compensation signal generated by integrating and differentiating the positive clock signal and the negative clock signal, respectively, to generate a second phase-mixed signal; and a noise removal section capable of receiving and removing a common mode noise between the first phase-mixed signal and the second phase-mixed signal by adjusting a cross-point therebetween, and outputting first and second duty-corrected clock signals.

One example discloses an apparatus for power management, including: a circuit having a first power-domain and a second power-domain; wherein the first and second power-domains include a set of operating parameter values; a circuit controller configured to incrementally sweep at least one of the operating parameter values of the first power-domain; a circuit profiler configured to derive a total power consumption profile of the circuit based on the circuit's response to the swept operating parameter value; wherein the circuit controller sets the operating parameter values for the first and second power-domains based on the total power consumption profile of the circuit.

Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a correction code generator configured to generate a reference correction code according to a duty detection signal based on a phase difference between the pair of first reference clocks, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.

In some embodiments, a phase-locked loop (PLL) system comprises a phase-frequency detector (PFD) configured to compare a phase-frequency reference signal and a feedback signal, a charge pump (CP) electrically coupled to the PFD and configured to produce a first tuning signal based on an output of the PFD, multiple integrator cells electrically coupled to the CP and configured to output multiple second tuning signals based on a voltage of the first tuning signal relative to a voltage reference signal, and a voltage-controlled oscillator (VCO) electrically coupled to the CP and to the multiple integrator cells and configured to adjust a capacitance value of the VCO based on the multiple second tuning signals. The capacitance value and the first tuning signal affect a frequency of the feedback signal.

A loop filter with an active discrete-level loop filter capacitor can be used in a VCO (such as for CDR). A loop filter capacitor function is simulated by sensing input loop filter current (such as with a current mirror and source follower in the input leg), and forcing back a loop filter (VCO) control voltage. Loop filter voltage control is provided using a VDAC with a discrete-level VDAC feedback voltage, incremented/decremented based on the sensed loop filter current. In one embodiment, the VDAC voltage is provided as the non-inverting input to an amplifier, with the inverting input providing the control voltage, forced to the VDAC feedback voltage. The VDAC feedback voltage can be provided by increment/decrement comparators based on a voltage deviation on a C2 capacitor (from a reference voltage) that receives the sensed loop filter current (effectively multiplying the C2 capacitance to provide a simulated loop filter capacitance).

A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider, a phase error processing circuit, a phase frequency detector and a phase alignment circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit generates a charge pump output in a calibration mode. The type II loop filter generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider performs frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit outputs an adjusting signal by comparing a reference signal with the feedback signal. The phase frequency detector generates a detection signal by comparing the feedback signal and the reference signal. The phase alignment circuit generates a second control signal in the calibration mode.

The present disclosure is directed to multichannel transducer devices and methods of operation thereof. One example device includes at least two acquisition modules that have different sensitives and a signal processing stage that generates a blended signal representative of a lower gain signal mapped onto a higher gain signal. One example method of operation includes receiving a first signal from a first sensor having a first sensitivity, receiving a second signal from a second sensor having a second sensitivity that is different from the first sensitivity, generating a blended signal by mapping the second signal to the first signal, outputting the first signal while the first signal is below a first threshold and above a second threshold, and outputting the blended signal when the first signal is above the first threshold and when the first signal is below the second threshold.

An apparatus includes an integrated circuit (IC). The IC includes a power controller, which includes a regulator and a controller. The regulator receives a plurality of input voltages and provides a regulated output voltage. The controller controls the regulator to generate the regulated output voltage from the plurality of input voltages. The power controller provides power to a load integrated in the IC from a set of arbitrary input voltages. The set of arbitrary input voltages includes the plurality of input voltages.

The present invention is directed to an electronic switch device, the device including a housing assembly including a front cover assembly having a user accessible surface, a back body assembly, terminals configured to be coupled to an AC power source and the load; an antenna assembly including an antenna substrate disposed inside the housing assembly adjacent a portion of the front cover assembly, an antenna being disposed on the antenna substrate having a conductive grid structure; and a circuit assembly disposed inside the housing assembly coupled to the terminals, the circuit assembly comprising a printed circuit board, the printed circuit board including a ground plane, the circuit assembly being electrically connected to the antenna assembly via a conductor, the printed circuit board being separated from the antenna assembly by a predetermined distance, the circuit assembly including a relay switch having at least one solenoid winding connected to the circuit assembly and a set of contacts.

A power conversion system may include a plurality of power devices and a sensor operably coupled to at least one of the plurality of power devices and configured to detect a voltage, current, or electromagnetic signature signal associated with the plurality of power devices. The power converter may also include circuitry operably coupled to the plurality of power devices and the sensor. The circuitry may send a respective gate signal to each respective power device of the plurality of power devices, such that each respective gate signal is delayed by a respective compensation delay that is determined for the respective power device based on a respective time delay of the respective power device and a maximum time delay of the plurality of power devices.