A heat transfer system includes a substrate having a heat exchange region including a surface having an enhancement region including alternating regions of selectively placed plurality of nucleation sites and regions lacking selectively placed nucleation sites, such that bubble formation and departure during boiling of a liquid in contact with the enhancement region induces liquid motion over the surface of the regions lacking selectively placed nucleation sites sufficient to enhance both critical heat flux and heat transfer coefficient at the critical heat flux in the enhancement region of the system.

Coatings for enhancing performance of materials surfaces, methods of producing the coating and coated substrates, and coated condensers are disclosed herein. More particularly, exemplary embodiments provide chemical coating materials useful for coating condenser components.

A formable structure comprises a first material having a first level of viscosity and a second material having a second level of viscosity, wherein the second material is formed to hold at least a portion of the first material in a particular position or a particular shape. The first material can be configured to function as a thermal interface between two or more hardware components. The second material can be configured to have a higher viscosity than the first material. In one illustrative example, the second material can include a light-activated resin that is configured to harden when exposed to one or more treatments. By the use of the first material and second material, the techniques disclosed herein are adaptable to gaps having a wide range of sizes, which is difficult to do with traditional thermal interface materials. The second material can also function as an EMI shield.

Generally discussed herein are devices and methods for thermal management of a component. An apparatus can include a phase change material substantially at a phase transition temperature of the phase change material, a component near, on, or at least partially in the phase change material, and a heat removal device to transfer heat energy away from the phase change material and maintain the phase change material substantially at the phase transition temperature.

Provided are a heat recovery apparatus based on a fuel cell and an operating method thereof. In the fuel cell-based heat recovery apparatus and the operating method thereof, hot water and steam may be generated by using heat generated while a molten carbonate fuel cell (MCFC) operates to supply the generated hot water or steam to buildings, thereby reducing a rate of operation in cooling/heating equipment using electricity so as to reduce air-conditioning costs.

A cooling plate with a structural plate and a cover plate, wherein the structural plate has a channel-like recess which is enclosed by a raised edge region. The cover plate rests on the raised edge region and covers the channel-like recess in order to form a channel. Openings with connection elements arranged at the openings are provided in the structural plate and/or in the cover plate in order to let a fluid into the channel and to let a fluid out of the channel. A first mounting opening, which is in the form of a round hole, and a second mounting opening, which is in the form of an elongate hole, are provided in both the structural plate and in the cover plate, the respective first and second mounting openings being aligned with one another in order to receive a pin for fixing the two plates during a soldering process.

A swing structure of a heat dissipating device includes an elongated blade and a magnetic actuation disposed on the blade. The blade has a loading segment and a heat dissipating segment, two opposite end portions of the loading segment are respectively defined as a mounting end portion and a connecting end portion, and two opposite end portions of the heat dissipating segment are respectively defined as a positioning end portion and a free end portion. The connecting end portion is connected to the positioning end portion. A thickness of the loading segment is greater than that of the heat dissipating segment. When the magnetic actuation is driven by a magnetic field to swing the blade, a swing angle of the free end portion of the heat dissipating segment is greater than that of the connecting end portion of the loading segment.

A liquid-cooling heat sink has a heat-conductive tube and multiple heat-conductive units arranged adjacent to the heat-conductive tube. The heat-conductive tube has a first tube and a second tube. An isolation member having an isolation channel is located between the first tube and the second tube. The isolation member obstructs the heat exchange between the first tube and the second tube. A first delivery tube and a second delivery tube of each one of the heat-conductive bodies respectively connect to the first tube and the second tube of the heat-conductive tube, thereby integrating the first tube and the second tube and obstructing the heat exchange between the cooling liquids with different temperatures. Each of the heat-conductive units distributes the cooling liquids with different temperatures by the heat-conductive tube, thereby simplifying the pipeline setting and reducing the volume of the liquid-cooling heat sink.

A Rack Information Handling System (RIHS) has a liquid cooling subsystem that provides cooling liquid to liquid cooled (LC) nodes received in chassis-receiving bays of a rack. Leak collection structures are positioned to receive cooling liquid that leaks from the liquid cooling subsystem. Liquid sensors detect a presence of leaked cooling liquid in the leak collection structures. A leak detection subsystem responds to a detected presence of liquid by providing a leak indication. In one or more embodiments, the liquid cooling subsystem has a liquid rail formed by more than one rack interconnections vertically aligned in a rear section of the rack that are connected by modular rail conduits for node-to-node fluid transfer. The leak collection structures include a pipe cover received over at least one modular rail conduit. A liquid cavity of each pipe cover spills over into another lower pipe cover at a rate that can be correlated to severity of the leak.

There is disclosed a vehicle air conditioner which is capable of enlarging an effective range of a dehumidifying and heating mode to environmental conditions and smoothly dehumidifying and heating a vehicle interior. A vehicle air conditioner 1 executes a dehumidifying and heating mode in which a controller lets a refrigerant discharged from a compressor 2 radiate heat in a radiator 4, and decompresses the refrigerant by which heat has been radiated and then lets the refrigerant absorb heat in a heat absorber 9 and an outdoor heat exchanger 7, the controller decreases an outdoor blower voltage FANVout of an outdoor blower 15 and decreases an air volume into the outdoor blower 15 in a case where a temperature Te of the heat absorber 9 is high even when the controller adjusts a valve position of an outdoor expansion valve 6 into a lower limit of controlling in a situation in which a temperature TCI of the radiator 4 is satisfactory.

An air conditioning system of a motor vehicle with a refrigerant circuit for operation in a refrigerator mode and a heat pump mode. The refrigerant circuit includes a primary circuit with a compressor, a heat exchanger for heat transfer between the refrigerant and the surroundings, an expansion element and a heat exchanger for heat transfer from the intake air being conditioned for the passenger compartment to the refrigerant, and a first flow path. The flow path extends from a branching point between the compressor and the heat exchanger to an opening and includes a heat exchanger for heat transfer from the refrigerant to the intake air being conditioned for the passenger compartment. The heat exchanger is situated in a flow direction of intake air of the passenger compartment after the heat exchanger.

Disclosed is a heat exchanger including: a heat exchanger body; a gas inlet for introducing exhaust gas into the heat exchanger body; a coolant inlet for introducing a coolant into the heat exchanger body; a gas outlet for discharging the exhaust gas that is cooled by heat exchange with the coolant; and a coolant outlet for discharging the coolant that completes heat exchange with the exhaust gas. In this case, the heat exchanger body includes: a laminated tube core formed by laminating a plurality of gas channels side by side; a housing formed so as to enclose the laminated tube core except for opposite ends thereof; and a wave fin plate integrally provided with a plurality of wave fins and arranged within each of the gas channels, wherein each of the wave fins includes a fixed pitch section, and a variable pitch section.

An integratable movement device for ventilating equipment includes an electric machine such as a motor and a fan wheel connected with the electric machine. The movement device further includes a housing, wherein the electric machine and the fan wheel are installed in an inner lower portion of the housing. An upper portion of the housing integrally forms one or more venting outlets. A plurality of venting outlet units is provided at the venting outlets respectively. A chamber provided between the venting outlets and the fan wheel in the housing defines a venting channel. The housing having the venting outlets and the venting channel, along with the venting outlet units, the electric machine and the fan wheel configure the integratable movement device that is able to be directly assembled into the ventilating equipment.

What is disclosed is a heat exchanger including: a core including a plurality of core plates, first and second passages, and a vertical passage; a base plate including a passage port; and a distance plate; wherein the first vertical passage and the passage port are arranged apart from each other in a direction orthogonal to a stacking direction of the core plates, and wherein the distance plate includes a bottom wall part and a swelling part, the bottom wall part being a thin plate-shaped and being joined to an upper surface of the base plate, the swelling part swelling up in the stacking direction from the bottom wall part so as to surround a circumference of a communication passage which communicates the first vertical passage with the passage port and being joined to a lowermost surface of the core in a flange part of a tip of the swelling part.

A high-efficiency plate type heat exchanger increases a heat-exchanging efficiency with an exhaust gas by connecting unit fluidized beds formed with stacked heat exchanging plates to each other in up and down directions, and elongating a flow path of circulating water to be greater than or equal to two passes (2-PASS). The heat exchanger retrieves heat of an exhaust gas by increasing a flow amount of circulating water of a portion close to a burner while a circulation path is elongated as described above. In addition, the high-efficiency plate type heat exchanger increases efficiency thereof by inserting a baffle plate having distribution holes between unit fluidized beds, controlling a flow of an exhaust gas while reducing an exhaust speed of the exhaust gas using heat exchanging fins of the baffle plate, absorbing heat of the exhaust gas, and effectively using a heat transfer area.

A heat exchange device includes a housing, a heat exchange module, and a piezoelectric module. Isolated inner and outer circulation chambers are formed in the housing. The heat exchange module in the housing includes a stack of separated plates parallel to each other. An inner channel communicated with the inner circulation chamber and an outer channel communicated with the outer circulation chamber are defined respectively by both sides of one of the plates and the other adjacent plates. The piezoelectric module in the housing includes a piezoelectric chip, and first and second heat exchange sides thermally coupled to the piezoelectric chip. The first heat exchange side is located in the inner circulation chamber and the second heat exchange side is located in the outer circulation chamber, so that heat can be transferred between the inner and outer circulation chambers via the piezoelectric chip.

Various methods and systems are provided for cryogenic heat transfer by nanoporous surfaces. In one embodiment, among others, a system includes a cryogenic fluid in a flow path of the system; and a system component in the flow path that includes a nanoporous surface layer in contact with the cryogenic fluid. In another embodiment, a method includes providing a cryogenic fluid; and initiating chilldown of a cryogenic system by directing the cryogenic fluid across a nanoporous surface layer disposed on a surface of a system component.

An adjustable refrigerant distribution device and a heat exchanger having same. The heat exchanger comprises: first and second collecting pipes; a heat exchanger core body; and a refrigerant distribution device, the refrigerant distribution device comprises a first distribution pipe, a first inlet pipe and a first drive assembly. The pipe wall of the first distribution pipe is provided with a first distribution hole. The first distribution pipe is inserted into at least one of the first and the second collecting pipes. The first inlet pipe is located outside at least one collecting pipe and is in communication with the first distribution pipe, and the first drive assembly drives the first distribution pipe to move relative to at least one collecting pipe. The distribution pipe of the refrigerant distribution device and the heat exchanger can translate along the axial direction, thereby adjusting refrigerant distribution so as to satisfy different distribution requirements.

In order to enhance heat reception from a cooling target object by a heat sink to efficiently cool a device, the cooling target object, a cooling device including a heat sink and a fluid path is provided. Further, the heat sink includes a heat receiving face. The fluid path is formed so as to allow a predetermined fluid to pass therethrough. The heat exchange portion includes a first path arranged approximately in parallel to the heat receiving face of the heat sink.

Integrated heat spreaders having electromagnetically-formed features, and semiconductor packages incorporating such integrated heat spreaders, are described. In an example, an integrated heat spreader includes a top plate flattened using an electromagnetic forming process. Methods of manufacturing integrated heat spreaders having electromagnetically-formed features are also described.

In a cooled component system, a heat exchanger mounted on a surface of the industrial component is housed in an isolated access compartment adjacent to but separated from the primary compartment containing the industrial component. Housing the heat exchanger in a separately accessible compartment permits access to the heat exchanger for cleaning or other purposes without having to shut down the industrial component being cooled. A means for moving a cooling media over the surface a the heat exchanger might also be included to maximize heat exchange.

An electronic rack includes a housing to contain one or more IT components arranged in a stack, a first rack aisle formed on a first side of the one or more IT components to direct cooler air received from the cooling unit upwardly, and a second rack aisle formed on a second side of the one or more IT components to direct warmer air to the cooling unit downwardly. The electronic rack further includes a cooling unit having one or more cooling units disposed underneath the IT components to receive first liquid from an external chiller system, to exchange heat carried by the warmer air using the first liquid to generate the cooler air, to transform the first liquid into a second liquid with a higher temperature, and to transmit the second liquid carrying the exchanged heat back to the external chiller system.

A rack airflow monitoring system is configured to measure airflow through an equipment rack having a housing and a perforated front door to enable air to flow into an interior of the housing. The system includes a control module, and a plurality of airflow sensors secured to the front door of the equipment rack and coupled to the control module. Each airflow sensor is configured to detect a parameter used to measure airflow and communicate detected parameters to the control module. The control module is configured to obtain temperature, airflow velocity, and airflow directionality from the plurality of airflow sensors at the front door of the equipment rack.

A digital down converter with an equalizer translates an ADC output signal to a low frequency spectral region, followed by decimation. All operations of correction of the processed signal are carried out with a reduced sampling rate compared with sampling rates of the prior art. Equalization is performed only in a frequency pass band of the down converter. The achieved reduction of the required computation resources is sufficient to enable the down converter with equalization to operate in a real time mode.

Embodiments of the invention provides a decoder for decoding a signal received through a transmission channel in a communication system, said signal carrying information symbols selected from a given alphabet and being associated with a signal vector, said transmission channel being represented by a channel matrix, wherein said decoder comprises: a sub-block division unit (301) configured to divide the received signal vector into a set of sub-vectors in correspondence with a division of a matrix related to said channel matrix;a candidate set estimation unit (305) for recursively determining candidate estimates of sub-blocks of the transmitted signal corresponding to said sub-vectors, each estimate of a given sub-block being determined from at least one candidate estimate of the previously processed sub-blocks,wherein said candidate set estimation unit is configured to determine a set of candidate estimates for at least one sub-block of the transmitted signal by applying at least one iteration of a decoding algorithm using the estimates determined for the previously processed sub-blocks, the number of candidate estimates determined for said sub-block being strictly inferior to the cardinal of the alphabet and superior or equal to two, the decoder further comprising a signal estimation unit (306) for calculating an estimate of the transmitted signal from said candidate estimates determined for said sub-blocks.

The present invention aims to provide a technology capable of enhancing the effect of reducing differential data in size. A bit shift unit shifts either of old data and new data in a forward direction and a backward direction of its bit string by each of 0, 1, 2, . . . , and n bit(s) to generate a plurality of data. A copy bit string extracting unit extracts information on copy bit strings based on the plurality of data and other non-shifted data. An additional bit string extracting unit excludes copy bit strings from the new data to extract information on additional bit strings. A differential data generating unit creates differential data based on the information on copy bit strings and the information on additional bit strings.

Methods and apparatus to parallelize data decompression are disclosed. An example method adjusting a first one of initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; and merging, by executing an instruction with the processor, first decoded data generated by decoding a first segment of the compressed data bitstream starting from the first adjusted starting position with second decoded data generated by decoding a second segment of the compressed data bitstream, the decoding of the second segment starting from a second position in the compressed data bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the compressed data bitstream.

A switch-scanning circuit includes a chip and switching units. The chip includes pins having an output operation mode and an input operation mode, and a processing unit. The processing unit sets one of the pins as an input pin and the rest of the pins as output pins sequentially according to a clock signal, uses a scan signal to provide different voltages to the output pins, and then determines states of button switches according to a voltage of the input pin. The switching unit includes a power source resistance, switches and resistors. A first terminal and a second terminal of the power source resistance are electrically connected to a power source and a first pin respectively. The resistors have terminals electrically connected the first pin and terminals of the switches. The other terminals of the switches are connected to the pins other than the first pin.

A circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal.

Input device adhesive techniques are described. A pressure sensitive key includes a sensor substrate having one or more conductors, a spacer layer, and a flexible contact layer. The spacer layer is disposed proximal to the sensor substrate and has at least one opening. The flexible contact layer is spaced apart from the sensor substrate by the spacer layer and configured to flex through the opening in response to an applied pressure to initiate an input. The flexible contact layer is secured to the spacer layer such that at first edge, the flexible contact layer is secured to the spacer layer at an approximate midpoint of the first edge and is not secured to the spacer along another portion of the first edge and at a second edge, the flexible contact layer is not secured to the spacer layer along an approximate midpoint of the second edge.

The pulse width modulator includes a subtraction unit configured to perform subtraction between an m value digital signal and a pulse width modulation signal; a feedforward filter unit configured such that a ΔΣ modulator to which an output signal of the subtraction unit is input and which includes integrators of a second order or higher is in cascade connection, and configured to operate with a sampling frequency FS; a product-sum computing unit configured to operate with a sampling frequency (FS/n) (n: an integer of two or more) to perform product-sum computing of an output signal of each integrator of the feedforward filter unit; and a pulse width modulation unit configured to operate with the sampling frequency (FS/n) to perform pulse width modulation of an output signal of the product-sum computing unit to output a pulse width modulation signal.

A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level.

A method for adaptively regulating a coding mode and a digital correction circuit thereof are provided. The method is for a successive-approximation-register analog-to-digital converter (SAR ADC). In the method, whether to regulate a binary weight corresponding to each of digital bits is determined according to the number of completed comparison cycles to provide a first coding sequence. The first coding sequence is directly compensated according to uncompleted comparison cycles to provide a correct digital output code.

The invention relates to an encoder and a decoder and methods therein for supporting split gain shape vector encoding and decoding. The method performed by an encoder, where the encoding of each vector segment is subjected to a constraint related to a maximum number of bits, BMAX, allowed for encoding a vector segment. The method comprises, determining an initial number, Np—init, of segments for a target vector x; and further determining an average number of bits per segment, BAVG, based on a vector bit budget and Np—init. The method further comprises determining a final number of segments to be used, for the vector x, in the gain shape vector encoding, based on energies of the Np—init segments and a difference between BMAX and BAVG. The performing of the method enables an efficient allocation of the bits of the bit budget over the target vector.

A system, method and computer program product for encoding an input string of binary characters representing alphanumeric characters. A system includes: a character writing engine for writing a binary character to an empty cell of a multi-dimensional shape beginning with a starting empty cell; a next cell determination engine for determining a next empty cell by traversing neighboring cells in the multi-dimensional shape until an empty cell is located; a loop facilitator for looping back to the character writing engine and the next cell determining engine until no more data characters or a next empty cell is not determined; and a serialization engine for serializing the cells into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.

Disclosed are an apparatus and method for compressing continuous data. The apparatus for compressing continuous data may include a data generator configured to calculate differences between adjacent values in original continuous data and generate data based on the calculated differences.

A codeset having function-code combinations is provisioned on a controlling device to control functions of an intended target device. Input is provided to the controlling device which designates a function to be controlled on the intended target device. From a plurality of codes that are each associated with the designated function in a database stored in a memory of the controlling device a first code that is determined to be valid for use in controlling the designated function on the intended target device is selected. When the codeset is then provisioned on the controlling device, the provisioned codeset includes as a function-code combination thereof the designated function and the first code.

An analog to digital converter (ADC) system that includes a first amplifier configured to amplify an analog input signal to produce an amplified direct current (DC) signal, an ADC configured to receive the amplified DC signal and convert the amplified DC signal into a digital DC signal, a digital to analog converter configured to receive the digital DC signal and convert the digital DC signal into an analog DC signal, and a second amplifier configured to receive an analog alternating current (AC) signal comprising the analog DC signal subtracted from the analog input signal and amplify the analog AC signal to produce an amplified AC signal. The ADC is further configured to receive the amplified AC signal and produce a digital AC signal. The second amplifier has a gain greater than a gain of the first amplifier.

An input buffer for an ADC is provided. The input buffer includes a receiving circuit and an impedance circuit. The receiving circuit is coupled between a power supply and a sample-and-hold circuit of the ADC, and receives an analog input signal and generating an analog signal. The impedance circuit is coupled to the receiving circuit, and selectively provides a variable impedance. When the sample-and-hold circuit of the ADC is operated in a first phase, the impedance circuit provides a small impedance, and when the sample-and-hold circuit of the ADC is operated in a second phase, the impedance circuit provides a large impedance.

A multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.

An encoder for encoding input data (D1) to generate corresponding encoded data (E2) includes data processing hardware which is operable: (a) to determine at least partial reoccurrences of data blocks or data packets within the input data (D1), wherein the data blocks or data packets include a plurality of bytes;(b) to employ at least one reference symbol to relate reoccurrences of mutually similar data blocks or data packets and/or to indicate whether or not there are reoccurrences of mutually similar data blocks or data packets within the input data (D1);(c) to employ a plurality of change symbols, for example a plurality of mask bits, to indicate changed and unchanged data elements of partial reoccurrences of data blocks or data packets within the input data (D1) and a change of data values of changed data elements; and(d) to encode the at least one reference symbol and the plurality of change symbols into the encoded data (E2). There are provided methods of using the encoder to encode input data (D1) to generate the corresponding encoded data (E2). Moreover, there are provided a corresponding decoder, and a corresponding method of decoding the encoded data (E2) to generate corresponding decoded data (D3).

Disclosed are methods and systems for significantly compressing sparse multidimensional ordered series data comprised of indexed data sets, wherein each data set comprises an index, a first variable and a second variable. The methods and systems are particularly suited for compression of data recorded in double precision floating point format.

A digital-to-analog converter (DAC) and a high-voltage tolerance circuit are provided. The DAC includes a high-voltage tolerance circuit. The high-voltage tolerance circuit is configured to generate a reference voltage, and select the reference voltage or a first power-source voltage to control the node voltage of each branch of an operational amplifier circuit of the high-voltage tolerance circuit according the logical signal level of an input signal.

An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

A semiconductor device configured to perform an A/D conversion of a wide range of signals is provided. A semiconductor device includes: an input voltage detection unit configured to detect an analog input voltage; a reference voltage setting unit configured to set a reference voltage based on the detected input voltage; an amplifier configured to amplify a difference between the input voltage and the reference voltage; an ADC configured to perform an A/D conversion of an amplified signal; and an arithmetic processing unit configured to calculate a digital voltage corresponding to the input voltage based on a result of the A/D conversion and the reference voltage.

A hybrid SAR-ADC that uses a combination of voltage-based signal processing and time-based signal processing to convert an analog input signal to a digital output signal is disclosed. In some embodiments, the hybrid SAR-ADC has a voltage-based signal processing element configured to convert an analog input signal to a first digital signal having a plurality of MSBs and to generate a residue voltage from an input voltage and the first digital signal. A voltage-to-time conversion element is configured to convert the residue voltage to a time domain representation. A time-based signal processing element is configured to convert the time domain representation to a second digital signal comprising a plurality of LSBs. By determining the plurality of MSBs using voltage-based signal processing and determining the plurality of LSBs using time-based signal processing, the hybrid SAR-ADC is able to achieve low power and compact area.

A current source device having a current source array includes a plurality of current source units, a plurality of least significant bits, and a plurality of most significant bits. The current source units are arranged along a plurality rows and columns of a current source array. Each of the least significant bits includes a first amount of current source units is placed at the geometric center of the current source array. Each of the most significant bits includes a second amount of current source units. The second amount is the first amount multiplied by a positive integer. The two adjacent bits in the most significant bits are centrally symmetrical to the geometric center.

A converter includes: a terminal that receives code-modulated power that has been generated with a modulation code; and a circuit that intermittently converts the code-modulated power with a conversion code based on the modulation code. The code-modulated power is alternating-current power.

Methods and apparatus are described. A method, implemented in a decoder, includes receiving two or more signals from an encoder over two or more respective wires. At least one of the two or more signals includes at least one code that was recoded by the encoder. The decoder receives a recoding table. The recoding table provides a mapping indicating the recoding for each code that was recoded by the encoder in the received two or more signals. The decoder decodes the two or more received signals using the received recoding table.