Hello All,

starting with version 8.1 the contents of the ce_tools directory will no longer
be shipped with Specman. The directory contains some unsupported AE/R&D
ware and has not been updated for several releases (i.e. most of those old
packages don't work with the latest release).
 
Attached is the contents of this directory. Please read the README before
using any of the packages.


Regards,
-hannes

Question for forum:

I’m currently working on a code to automatically add CLP files to DRA files and then add two classes called “APPROVED” and “CLP”. To do this manually you have to open a DRA file, click file import subdrawing and choose the clp file with the same name as dra. (path already set). You then set the clp to position x 0 0. And then click on Set Up > Subclasses > Package geometry and type in “Approved” and “Clp.”

So far we’ve recorded the macros in Allegro for all of these actions. The macros correspond to one specific file name and we want to apply this to numerous files. To do this we created a python program that locates all of the specified CLP and DRA files, and if they have a matching name, runs a for loop that puts each file name into a stored variable that runs a loop for each file. We converted this script into batch and then added a function that we thought would run Allegro macros from batch.

In order to get the script working, we need to have an allegro batch command that will run the script without opening the Allegro start popup, or closing the popup when it appears.  We need to do this to run any script from starting Allegro.

I’ve done another similar program in batch where I made a for loop for each dra file and within the loop there was a batch a2dxf command that converted all dra files to dxf files. Is there a similar batch command for adding clp files to position 0 0 and/ or adding classes? If anyone has done something similar please let me know!

Thank you very much for the help.

Jen

Hello,

I am trying to import multiple verilog modules defined in a single file with "`define" directive in the top using Verilog In. The code below is an example of what my file contains.

When I use the settings below to import the modules into a library, it imports it correctly but completely ignores all `define directive; hence when I simulate using any of the modules below the simulator errors out requesting these variables.

My question: Is there a way to make Verilog In consider `define directives in every module cell created? 

Code to be imported by Cadence Verilog In:

--------------------------------------------------------

`timescale 1ns/1ps
`define PROP_DELAY 1.1
`define INVALID_DELAY 1.3

`define PERIOD 1.1
`define WIDTH 1.6
`define SETUP_TIME 2.0
`define HOLD_TIME 0.5
`define RECOVERY_TIME 3.0
`define REMOVAL_TIME 0.5
`define WIDTH_THD 0.0

`celldefine
module MY_FF (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF
`endcelldefine

`timescale 1ns/1ps
`celldefine
module MY_FF2 (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF2
`endcelldefine

--------------------------------------------------------

I am using the following Cadence versions:

MMSIM Version: 13.1.1.660.isr18

Virtuoso Version: IC6.1.8-64b.500.1

irun Version: 14.10-s039

Spectre Version: 18.1.0.421.isr9

Hi,

I tried to open my layout by Library Manager, but the Virtuoso CIW window sometimes pops up the follow WARNING messages( as picture depicts). Thus, layout can't open.

Sometimes, I try to reconfigure ICADV12.3 by the iscape and restart my VM and then it incredibly works! But, often not!

So, If anyone knows what it is going on. Please let me know! Thanks!

Appreciated so much   

Hello,

I am using ultrasim Version 18.1.0.314.isr5  64bit 03/26/2019 06:33 (csvcm20c-2).

When I run my netlist, ultrasim is blocked in the first DC stage and takes forever. Then it will fail or never progress. I am using a 22nm BSIMBULK model. I tried to tune different accuracy and convergence aids options but noting works.

 When I run the same netlist with spectre it works fine with no problem.

Also, If I use another model (not BULKSIM), ultrasim will work and converge with no problem.

My first feeling is that ultrasim has a problem with using BSIMBULK model.

Could you please advice,

Thank you,

Kotb

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