ul Montgomery inverse calculation device and method of calculating montgomery inverse using the same By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal. Full Article
ul Multiply and accumulate feedback By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT A method and apparatus may be used to evaluate a polynomial by initializing a multiply and accumulate feedback apparatus (260) comprising a multiplier stage (264) having an output coupled to an input of an accumulator stage (267) having an accumulator feedback output (269) selectively coupled to an input of the multiplier stage over a plurality of clock cycles; iteratively calculating a final working loop variable z over an additional plurality of clock cycles; multiplying the final working loop variable z and a complex input vector x to compute a final multiplier value; and adding a least significant complex polynomial coefficient to the final multiplier value using the multiplier stage of the multiply and accumulate feedback apparatus to yield a result of the polynomial evaluation. Full Article
ul Ultra fast process for the preparation of polymer nanoparticles By www.freepatentsonline.com Published On :: Tue, 30 Dec 2014 08:00:00 EST A process for the preparation of polymer lattices comprising polymer nanoparticles by a photo-initiated heterophase polymerization includes preparing a heterophase medium comprising a dispersed phase and a continuous phase and at least one of at least one surfactant, at least one photoinitiator, and at least one polymerizable monomer. The at least one polymerizable monomer is polymerized by irradiating the heterophase medium with electromagnetic radiation so as to induce a generation of radicals. The at least one photoinitiator is selected from compounds comprising at least one phosphorous oxide group (P═O) or at least one phosphorous sulfide (P═S) group. The irradiating of the heterophase medium is effected so that a ratio of an irradiated surface of the heterophase medium to a volume of the heterophase medium is at least 200 m−1. Full Article
ul Process for the modification of polymers, in particular polymer nanoparticles By www.freepatentsonline.com Published On :: Tue, 30 Dec 2014 08:00:00 EST A process for the preparation of modified polymers by a photo-initiated polymerization includes preparing a polymerization medium comprising at least one photoinitiator comprising at least one phosphorous oxide (P═O) group or at least one phosphorous sulfide (P═S) group, and at least one polymerizable monomer. The at least one polymerizable monomer is polymerized by irradiating the polymerization medium with electromagnetic radiation so as to induce a generation of radicals so as to obtain a polymer. The polymer is modified by irradiating the polymer with electromagnetic radiation so as to induce a generation of radicals from the polymer in a presence of at least one modifying agent. Full Article
ul Multipass programming in buffers implemented in non-volatile data storage systems By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT The various implementations described herein include systems, methods and/or devices used to enable multipass programming in buffers implemented in non-volatile data storage systems (e.g., using one or more flash memory devices). In one aspect, a portion of memory (e.g., a page in a block of a flash memory device) may be programmed many (e.g., 1000) times before an erase is required. Some embodiments include systems, methods and/or devices to integrate Bloom filter functionality in a non-volatile data storage system, where a portion of memory storing one or more bits of a Bloom filter array may be programmed many (e.g., 1000) times before the contents of the portion of memory need to be moved to an unused location in the memory. Full Article
ul Interrupt control method and multicore processor system By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT In an interrupt control method of a multicore processor system including cores, a cache coherency mechanism, and a device, a first core detecting an interrupt signal from the device writes into an area prescribing an interrupt flag in the cache memory of the first core, first data indicating detection of the interrupt signal, and notifies the other cores of an execution request for interrupt processing corresponding to the interrupt signal, consequent to the cache coherency mechanism establishing coherency among at least cache memories of the other cores when the first data is written; and a second core different from the first core, maintaining the first data written as the interrupt flag, and notified of the execution request executes the interrupt processing, and writes over the area prescribing the interrupt flag written in the cache memory of the second core, with second data indicating no-detection of the interrupt signal. Full Article
ul Handling interrupts in a multi-processor system By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request. Full Article
ul System and method for a workload management and scheduling module to manage access to a compute environment according to local and non-local user identity information By www.freepatentsonline.com Published On :: Tue, 19 May 2015 08:00:00 EDT A system, method and computer-readable media for managing a compute environment are disclosed. The method includes importing identity information from an identity manager into a module performs workload management and scheduling for a compute environment and, unless a conflict exists, modifying the behavior of the workload management and scheduling module to incorporate the imported identity information such that access to and use of the compute environment occurs according to the imported identity information. The compute environment may be a cluster or a grid wherein multiple compute environments communicate with multiple identity managers. Full Article
ul End to end modular information technology system By www.freepatentsonline.com Published On :: Tue, 19 May 2015 08:00:00 EDT Embodiments of the invention are directed to a system, method, or computer program product for providing an information technology build service for building a platform in response to a service request. The invention receives a service request for the platform build from a requester, receives a plurality of platform parameters from the requester, determines whether the service request requires one or more physical machines or one or more virtual machines, and if the service request requires one or more virtual machines, initiates build of the one or more virtual machines. The invention also provisions physical and virtual storage based on received parameters, provisions physical and virtual processing power based on received parameters, and manages power of resources during the build, the managing comprising managing power ups, power downs, standbys, idles and reboots of one or more physical components being used for the build. Full Article
ul Apparatus and methods for adaptive thread scheduling on asymmetric multiprocessor By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described. Full Article
ul 1,4-fullerene addends in photovoltaic cells By www.freepatentsonline.com Published On :: Tue, 10 Feb 2015 08:00:00 EST 1,4 fullerene deriatives useful for solar cells are provided, where their structures allow for straightforward functionalizations to tune their properties in terms of solubility and LUMO energy levels. Full Article
ul Process for the preparation of dichlorofulvene By www.freepatentsonline.com Published On :: Tue, 21 Apr 2015 08:00:00 EDT The invention relates to a process for the preparation of formula (I) which process comprises pyrolyzing a compound of formula (II) wherein X is chloro or bromo, and to compounds which may be used as intermediates for the manufacture of the compound of formula I and to the preparation of said intermediates. Full Article
ul Reactor and agitator useful in a process for making 1-chloro-3,3,3-trifluoropropene By www.freepatentsonline.com Published On :: Tue, 28 Apr 2015 08:00:00 EDT Disclosed is a reactor and agitator useful in a high pressure process for making 1-chloro-3,3,3-trifluoropropene (1233zd) from the reaction of 1,1,1,3,3-pentachloropropane (240fa) and HF, wherein the agitator includes one or more of the following design improvements: (a) double mechanical seals with an inert barrier fluid or a single seal;(b) ceramics on the rotating faces of the seal;(c) ceramics on the static faces of seal;(d) wetted o-rings constructed of spring-energized Teflon and PTFE wedge or dynamic o-ring designs; and(e) wetted metal surfaces of the agitator constructed of a corrosion resistant alloy. Full Article
ul Recovery and separation of crude oil and water from emulsions By www.freepatentsonline.com Published On :: Tue, 16 Dec 2014 08:00:00 EST A composition and method demulsify a produced emulsion from anionic surfactants and polymer (SP) and alkali, surfactants, and polymer (ASP). The produced emulsion is demulsified into oil and water. In one embodiment, the composition includes a surfactant. The surfactant comprises a cationic surfactant, an amphoteric surfactant, or any combinations thereof. Full Article
ul Stabilized formulations of fatty acids By www.freepatentsonline.com Published On :: Tue, 06 Jan 2015 08:00:00 EST Disclosed herein are stabilized powder and aqueous formulations comprising a substantially water insoluble lipophilic bioactive compound and a micelle-forming surfactant. In one embodiment, the formulation further comprises a water soluble reducing agent, and/or a water insoluble reducing agent, and/or a metal chelator, and/or a metal bisulfite reducing agent, or combinations thereof, wherein the formulation remains substantially clear and stable when stored at or below room temperature for a period of at least 6 months or at least 12 months; and methods for preparing these formulations. Full Article
ul Emulsions of heat transfer fluids including nanodroplets to enhance thermal conductivities of the fluids By www.freepatentsonline.com Published On :: Tue, 27 Jan 2015 08:00:00 EST A heat transfer fluid emulsion includes a heat transfer fluid, and liquid droplets dispersed within the heat transfer fluid, where the liquid droplets are substantially immiscible with respect to the heat transfer fluid and have dimensions that are no greater than about 100 nanometers. In addition, the thermal conductivity of the heat transfer fluid emulsion is greater than the thermal conductivity of the heat transfer fluid. Full Article
ul Polymers as additives for the separation of oil and water phases in emulsions and dispersions By www.freepatentsonline.com Published On :: Tue, 17 Feb 2015 08:00:00 EST Oil-water dispersions and emulsions derived from petroleum industry operations are demulsified and clarified using anionic polymers. Formation of such oil-water dispersion and emulsions is inhibited and mitigated using the anionic polymers. The anionic polymers comprise: A) 2-80% by weight of at least one C3-C8 α,β-ethylenically unsaturated carboxylic acid monomer; B) 15-80% by weight of at least one nonionic, copolymerizable α,β-ethylenically unsaturated monomer; C) 1-50% by weight of one or more of the following monomers: C1) at least one nonionic vinyl surfactant ester; or C2) at least one nonionic, copolymerizable α,β-ethylenically unsaturated monomer having longer polymer chains than monomer B), or C3) at least one nonionic urethane monomer; and, optionally, D) 0-5% by weight of at least one crosslinker. Full Article
ul Ultrastable particle-stabilized foams and emulsions By www.freepatentsonline.com Published On :: Tue, 10 Mar 2015 08:00:00 EDT Described is a method to prepare wet foams exhibiting long-term stability wherein colloidal particles are used to stabilize the gas-liquid interface, said particles being initially inherently partially lyophobic particles or partially lyophobized particles having mean particle sizes from 1 nm to 20 μm. In one aspect, the partially lyophobized particles are prepared in-situ by treating initially hydrophilic particles with amphiphilic molecules of specific solubility in the liquid phase of the suspension. Full Article
ul Method for producing emulsion and thereby obtained emulsion By www.freepatentsonline.com Published On :: Tue, 17 Mar 2015 08:00:00 EDT A method for producing an emulsion is provided. At least a fluid to be processed that forms continuous phase and a fluid to be processed that forms dispersed phase are mixed in a thin film fluid formed between processing surfaces arranged to be opposite to each other so as to be able to approach to and separate from each other, at least one of which rotates relative to the other, whereby the emulsion having variation coefficient of 0.3 to 30% in a particle size distribution is obtained. Full Article
ul Bi-modal emulsions By www.freepatentsonline.com Published On :: Tue, 17 Mar 2015 08:00:00 EDT A process for preparing bi-modal water emulsions is disclosed comprising: I) forming a mixture comprising; A) 100 parts by weight of a hydrophobic oil, B) 1 to 1000 part by weight of a water continuous emulsion having at least one surfactant, II) admixing additional quantities of the water continuous emulsion and/or water to the mixture from step I) to form a bi-modal emulsion. Full Article
ul Aqueous epoxy and organo-substituted branched organopolysiloxane emulsions By www.freepatentsonline.com Published On :: Tue, 31 Mar 2015 08:00:00 EDT Aqueous emulsions of epoxy- and organo-substituted, branched organopolysiloxanes are prepared by emulsifying the latter in water with the aid of a dispersing agent. The emulsions are storage stable and are useful in multi-component coating, adhesive, and binder systems. Full Article
ul Method of synthesizing bulk transition metal carbide, nitride and phosphide catalysts By www.freepatentsonline.com Published On :: Tue, 21 Apr 2015 08:00:00 EDT A method for synthesizing catalyst beads of bulk transmission metal carbides, nitrides and phosphides is provided. The method includes providing an aqueous suspension of transition metal oxide particles in a gel forming base, dropping the suspension into an aqueous solution to form a gel bead matrix, heating the bead to remove the binder, and carburizing, nitriding or phosphiding the bead to form a transition metal carbide, nitride, or phosphide catalyst bead. The method can be tuned for control of porosity, mechanical strength, and dopant content of the beads. The produced catalyst beads are catalytically active, mechanically robust, and suitable for packed-bed reactor applications. The produced catalyst beads are suitable for biomass conversion, petrochemistry, petroleum refining, electrocatalysis, and other applications. Full Article
ul Oil-in-water silicone emulsion composition By www.freepatentsonline.com Published On :: Tue, 12 May 2015 08:00:00 EDT Provided is an oil-in-water silicone emulsion composition that has a low silicone oligomer content, and that can form, even without the use of an organotin compound as a curing catalyst, a cured film that exhibits satisfactory strength and satisfactory adherence to a substrate, through the removal of water fraction. An oil-in-water silicone emulsion composition comprising (A) 100 mass parts of a polyorganosiloxane that contains in each molecule at least two groups selected from the group consisting of a silicon-bonded hydroxyl group, alkoxy group, and alkoxyalkoxy group, (B) 0.1 to 200 mass parts of a colloidal silica, (C) 0.1 to 100 mass parts of an aminoxy group-containing organosilicon compound that has in each molecule an average of two silicon-bonded aminoxy groups, (D) 1 to 100 mass parts of an ionic emulsifying agent, (E) 0.1 to 50 mass parts of a non-ionic emulsifying agent, and (F) 10 to 500 mass parts of water. Full Article
ul Implementation of multi-tasking on a digital signal processor with a hardware stack By www.freepatentsonline.com Published On :: Tue, 28 Apr 2015 08:00:00 EDT The disclosure relates to the implementation of multi-tasking on a digital signal processor. Blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which instead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. Whilst the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided. Full Article
ul System and method for Controlling restarting of instruction fetching using speculative address computations By www.freepatentsonline.com Published On :: Tue, 28 Apr 2015 08:00:00 EDT A system and method for controlling restarting of instruction fetching using speculative address computations in a processor are provided. The system includes a predicted target queue to hold branch prediction logic (BPL) generated target address values. The system also includes target selection logic including a recycle queue. The target selection logic selects a saved branch target value between a previously speculatively calculated branch target value from the recycle queue and an address value from the predicted target queue. The system further includes a compare block to identify a wrong target in response to a mismatch between the saved branch target value and a current calculated branch target, where instruction fetching is restarted in response to the wrong target. Full Article
ul Issue policy control within a multi-threaded in-order superscalar processor By www.freepatentsonline.com Published On :: Tue, 12 May 2015 08:00:00 EDT A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behavior of the processor 2. Full Article
ul Recovering from an error in a fault tolerant computer system By www.freepatentsonline.com Published On :: Tue, 12 May 2015 08:00:00 EDT A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread and the trailing thread preferably being assigned to two different cores. At this time, the leading thread and the trailing thread are simultaneously executed, performing a buffering operation on a thread local area without performing a write operation on a shared memory. When the respective execution results of the two threads match each other, the content buffered to the thread local area is committed and written to the shared memory. When the respective execution results of the two threads do not match each other, the leading thread and the trailing thread are rolled back to a preceding commit point and re-executed. Full Article
ul Multiprocessor system, multiprocessor control method, and multiprocessor integrated circuit By www.freepatentsonline.com Published On :: Tue, 12 May 2015 08:00:00 EDT In a multiprocessor system, in general, a processor assigned with a larger amount of tasks is apt to perform a larger amount of communication with other processors assigned with tasks, than a processor assigned with a smaller amount of tasks. Thus in order for each processor to be able to perform the routing process efficiently, tasks are assigned such that, when there are a first processor and a second processor, the number of processors each assigned with one or more tasks and directly connected with the second processor being smaller than the number of processors each assigned with one or more tasks and directly connected with the first processor, the amount of tasks assigned to the first processor is equal to or larger than the amount of tasks assigned to the second processor. Full Article
ul Data accessing method for flash memory storage device having data perturbation module, and storage system and controller using the same By www.freepatentsonline.com Published On :: Tue, 19 May 2015 08:00:00 EDT A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module. Full Article
ul Multiprocessor messaging system By www.freepatentsonline.com Published On :: Tue, 19 May 2015 08:00:00 EDT A multiprocessor system includes a first microprocessor and a second microprocessor. A first signaling pathway is configured to send message transmission coordination signals from the first microprocessor to the second microprocessor. The first signaling pathway may be coupled to at least two flag registers associated with the second microprocessor. A second signaling pathway is configured to send message transmission coordination signals from the second microprocessor to the first microprocessor. The second signaling pathway may be coupled to at least two flag registers associated with the first microprocessor. The first signaling pathway is independent of the second signaling pathway. Full Article
ul Data mover moving data to accelerator for processing and returning result data based on instruction received from a processor utilizing software and hardware interrupts By www.freepatentsonline.com Published On :: Tue, 19 May 2015 08:00:00 EDT Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt. Full Article
ul Debug in a multicore architecture By www.freepatentsonline.com Published On :: Tue, 19 May 2015 08:00:00 EDT A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison. Full Article
ul Storing in other queue when reservation station instruction queue reserved for immediate source operand instruction execution unit is full By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing apparatus also includes another execution unit which performs computation on two operand inputs, one of which is selectable between read data from a register and an immediate value, and the other of which is an immediate value. A control unit determines, based on a received instruction specifying a computation on two operands, whether each of the two operands specifies read data from a register or an immediate value. Depending on the determination result, the control unit causes one of the execution units to execute the computation specified by the received instruction. Full Article
ul Dynamic energy savings for digital signal processor modules using plural energy savings states By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT In an example embodiment, there is described herein an apparatus comprising an interface for communicating with a plurality of digital signal processors and logic operable to send and receive data via the interface. The logic is configured to determine a first set of digital signal processors to be maintained in a ready state, a second set of digital signal processors to be maintained in a first energy saving state, and a third set of digital signal processors to be maintained in a second energy saving state. Full Article
ul Automatic WSDL download of client emulation for a testing tool By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT A method is disclosed which may include analyzing communication requests in a business process between a client and a server offering a service application to be tested. The method may further include identifying a call to a web service in the analyzed communication. The method may also include determining a location of a Web Service Description Language (WSDL) file relating to the web service on a remote server and downloading the WSDL file from the determined location. A computer readable medium having stored thereon instructions for performing the method and a computer system are also disclosed. Full Article
ul Framework for facilitating implementation of multi-tenant SaaS architecture By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT A framework for implementing multitenant architecture is provided. The framework comprises a framework services module which is configured to provide framework services that facilitate abstraction of Software-as-a-Service (SaaS) services and crosscutting services for a Greenfield application and a non SaaS based web application. Further the abstraction results in a SaaS based multitenant web application. The framework further comprises a runtime module configured to automatically integrate and consume the framework services and APIs to facilitate monitoring and controlling of features associated with the SaaS based multitenant web application. The framework further comprises a metadata services module configured to provide a plurality of metadata services to facilitate abstraction of storage structure of metadata associated with the framework and act as APIs for managing the metadata. The framework further comprises a role based administration module that facilitates management of the metadata through a tenant administrator and a product administrator. Full Article
ul Enhanced instruction scheduling during compilation of high level source code for improved executable code By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT Systems and methods for static code scheduling are disclosed. A method can include receiving an intermediate representation of source code, building a directed acyclic graph (DAG) for the intermediate representation, and creating chains of dependent instructions from the DAG for cluster formation. The chains are merged into clusters and each node in the DAG is marked with an identifier of a cluster it is part of to generate a marked instruction DAG. Instruction DAG scheduling is then performed using information about the clusters to generate an ordered intermediate representation of the source code. Full Article
ul System for generating readable and meaningful descriptions of stream processing source code By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT An information processing system, computer readable storage medium, and method for automatically generating human readable and meaningful documentation for one or more source code files. A processor of the information processing system receives one or more source code files containing source code artifacts (SCA) and infers semantics therefrom based on predefined rules. The processor, based on the inferred semantics, extracts documentation from another source code file. The extracted documentation and the inferred semantics are used to generate new human readable and meaningful documentation for the SCA, such new documentation being previously missing from the SCA. The generated new documentation is included with the SCA in one or more source code files. Full Article
ul System and method for generating software unit tests simultaneously with API documentation By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT A system and method may generate unit tests for source code concurrently with API documentation. The system may receive a source code file including several comments sections. Each comments section may include a description of a source code unit such as a class, method, member variable, etc. The description may also correspond to input and output parameters the source code unit. The system and method may parsing the source code file to determine a source code function type corresponding to the unit description and copy the unit description to a unit test stub corresponding to the function type. A developer or another module may then complete the unit test stub to transform each stub into a complete unit test corresponding to the source code unit. Additionally, the system and method may execute the unit test and generate a test result indication for each unit test. Full Article
ul Fault localization using condition modeling and return value modeling By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT Disclosed is a novel computer implemented system, on demand service, computer program product and a method that leverages combined concrete and symbolic execution and several fault-localization techniques to automatically detects failures and localizes faults in PHP Hypertext Preprocessor (“PHP”) Web applications. Full Article
ul Simultaneously targeting multiple homogeneous and heterogeneous runtime environments By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT A single software project in an integrated development environment (IDE) may be built for multiple target environments in a single build episode. Multiple different output artifacts may be generated by the build process for each of the target environments. The output artifacts are then deployed to the target environments, which may be homogeneous or heterogeneous environments. The same source project may be used to generate multiple output artifacts for the same target environment. Full Article
ul Release management system for a multi-node application By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT A deployment system provides the ability to deploy a multi-node distributed application, such as a cloud computing platform application that has a plurality of interconnected nodes performing specialized jobs. The deployment system includes a release management system that builds and manages versioned releases of application services and/or software modules that are executed by the plurality of nodes of the cloud computing platform application. The release management system utilizes specification files to define a jobs and application packages and configurations needed to perform the jobs. The jobs and application packages are assembled into a self-contained release bundle that may be provided to the deployment system. The deployment system unwraps the release bundle and provides each job to deployment agents executing on VMs. The deployment agents apply the jobs to their respective VM (e.g., launching applications), thereby deploying the cloud computing platform application. Full Article
ul Optimization of loops and data flow sections in multi-core processor environment By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions. Full Article
ul Program module applicability analyzer for software development and testing for multi-processor environments By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution. Full Article
ul Software modification methods to provide master-slave execution for multi-processing and/or distributed parallel processing By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT In one embodiment of the invention, a method is disclosed for modifying a pre-existing application program for multi-processing and/or distributed parallel processing. The method includes searching an application program for a computational loop; analyzing the computational loop to determine independence of the computational transactions of the computational loop; and replacing the computational loop with master code and slave code to provide master-slave execution of the computational loop in response to analyzing the computational loop to determine independence of the computational transactions of the computational loop. Multiple instances of the modified application program are executed to provide multi-processing and/or distributed parallel processing. Full Article
ul Adjustment of threads for execution based on over-utilization of a domain in a multi-processor system by destroying parallizable group of threads in sub-domains By www.freepatentsonline.com Published On :: Tue, 26 May 2015 08:00:00 EDT Embodiments provide various techniques for dynamic adjustment of a number of threads for execution in any domain based on domain utilizations. In a multiprocessor system, the utilization for each domain is monitored. If a utilization of any of these domains changes, then the number of threads for each of the domains determined for execution may also be adjusted to adapt to the change. Full Article
ul Methods and systems to identify and reproduce concurrency violations in multi-threaded programs using expressions By www.freepatentsonline.com Published On :: Tue, 15 Sep 2015 08:00:00 EDT Methods and systems to identify and reproduce concurrency bugs in multi-threaded programs are disclosed. An example method disclosed herein includes defining a data type. The data type includes a first predicate associated with a first thread of a multi-threaded program that is associated with a first condition, a second predicate that is associated with a second thread of the multi-threaded program, the second predicate being associated with a second condition, and an expression that defines a relationship between the first predicate and the second predicate. The relationship, when satisfied, causes the concurrency bug to be detected. A concurrency bug detector conforming to the data type is used to detect the concurrency bug in the multi-threaded program. Full Article
ul Microcapsules and uses thereof By www.freepatentsonline.com Published On :: Tue, 15 Jul 2014 08:00:00 EDT The present invention relates to a process for producing perfume-containing microcapsules having both an aqueous inner phase and an oily inner phase, which can be used in home or personal care products, as well as to the process for producing these microcapsules and the consumer products containing them. Full Article
ul Microcapsules, their use and processes for their manufacture By www.freepatentsonline.com Published On :: Tue, 22 Jul 2014 08:00:00 EDT A microcapsule comprising A) a core containing a hydrophobic liquid or wax, B) a polymeric shell comprising a) a polymer formed from a monomer mixture containing: i) 1 to 95% by weight of a hydrophobic mono functional ethylenically unsaturated monomer, ii) 5 to 99% by weight of a polyfunctional ethylenically unsaturated monomer, and iii) 0 to 60% by weight of other mono functional monomer, and b) a further hydrophobic polymer which is insoluble in the hydrophobic liquid or wax. The invention includes a process for the manufacture of particles and the use of particles in articles, such as fabrics, and coating compositions, especially for textiles. Full Article
ul 1-hydroxy-octahydroazulenes as fragrances By www.freepatentsonline.com Published On :: Tue, 11 Nov 2014 08:00:00 EST (3S,5R)-3,8-dimethyl-5-(prop-1-en-2-yl)-octahydroazulen-1-ols, their use as flavor or fragrance ingredient, and a process of their production by oxidation in the presence of laccase. Full Article