A negotiable instrument such as a check includes a unique microprint identifier that allows for authentication while preventing unauthorized reproduction and alternation. A printing system generates the identifier after receiving a customer order for printing a plurality of negotiable instruments, to allow inclusion of information that is specific to the customer order and/or the printing process. In various embodiments, the identifier is unique to each or each subset of the plurality of negotiable instruments and facilitates authentication of each of the negotiable instruments when needed.

An electronic transaction verification system for use with transaction tokens such as checks, credit cards, debit cards, and smart cards that gathers and transmits information about the transaction token and biometric data. Customers can be enrolled in the system by receiving customer information that includes at least a biometric datum, associating the received customer information with a transaction instrument issued to the customers and storing the received customer information and the issued transaction instrument information in a database for future reference.

Embodiments of the present disclosure can include devices for storing and exchanging color space encoded images. The encoded images can store input data into high capacity multi-colored composite two-dimensional pictures having different symbols organized in specific order using sets in a color space. The encoding can include performing two-level error correction and generating frames based on the color space for formatting and calibrating the encoded images during decoding. The decoding can use the frames to perform color restoration and distortion correction. The decoding can be based on a pseudo-Euclidean distance between a distorted color and a color in a color calibration cells. In some embodiments, an encoded image can be further divided into sub-images during encoding for simplified distortion correction.

An illuminating, indicia-reading device includes a hand-held indicia reader and a charging-and-communication base. The charging-and-communication base's communication button places the hand-held indicia reader in presentation mode when the hand-held indicia reader is seated in the charging-and-communication base, thereby facilitating hands-free scanning and providing work lamp functionality via activation of the hand-held indicia reader's light source. When the hand-held indicia reader is not seated, the communication button pages the hand-held-indicia reader.

Disclosed is an apparatus for protecting an analog input module from overvoltage, the apparatus including an analog input module and a stabilization unit. The analog input module converts one of a plurality of positive/negative analog signals inputted from the outside thereof into a digital signal and insulates the converted digital signal. The stabilization unit supplies voltages of the positive/negative analog signals to the analog input module when the voltage levels of the plurality of positive/negative analog signals are higher than the levels of positive/negative operating voltages in the analog input module.

A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor.

System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

A reference voltage generating circuit has more than two first wells each having a first impurity concentration and more than two second wells each having a second impurity concentration different from the first impurity concentration. A first group of MOS transistors has more than two MOS transistors formed in respective ones of the first wells. A second group of MOS transistors has More than two MOS transistors formed in respective ones of the second wells.

A method for operating a brushless electric motor, the windings being energized by an inverter with the aid of six switches. A detection unit for detecting defective switches, a unit for measuring voltage at the outputs of the inverter, and a microcontroller for controlling the switch and for generating a pulse width modulated voltage supply for the windings are provided. A short-circuited switch causes a torque in the electric motor opposite the actuating direction of the electric motor. The method proposes that after detecting a short-circuited switch, the windings (U. V. W) are energized to generate a motor torque that is, on the whole, positive. An actuating period of the electric motor is divided into a plurality of sectors, wherein, in accordance with the defective switch, individual sectors are deactivated for the actuation of the windings (U, V, W), while other sectors are used to actuate the windings (V, W).

The present disclosure provides methods and devices for testing a connection between speakers and a power amplifier. The disclosed methods and devices solve a problem that, upon a connection test for a power amplifier which has a booster power source, when a midpoint potential of the power amplifier and the voltage of the speaker connection terminal are compared, and it is determined that short-circuiting occurs on a ground side when the potential of the speaker connection terminal is lower than the midpoint potential, a wrong test is conducted if a midpoint potential is higher than a battery voltage.

A quantum information processing system includes a waveguide having an aperture, a non-linear quantum circuit disposed in the waveguide and an electromagnetic control signal source coupled to the aperture.

The disclosure relates generally to sequential state elements (SSEs), triple-mode redundant state machines (TMRSMs), and methods and systems for testing triple-mode redundant pipeline stages (TMRPSs) within the TMRSMs using triple-mode redundant SSEs (TMRSSEs). The SSEs, TMRSMs, TMRPSs, and TMRSSEs may be formed as integrated circuits on a semiconductor substrate. Of particular focus in this disclosure are SSEs used to sample and hold bit states. Embodiments of the SSEs have a self-correcting mechanism to protect against radiation-induced soft errors. The SSE may be provided in a pipeline circuit of a TMRSM to receive and store a bit state of a bit signal generated by combinational circuits within the pipeline circuit. More specifically, the SSEs may be provided in a TMRSSE configured to perform self-correction. Also disclosed are methods for using the TMRSSE to test redundant pipeline stages of the TMRSM.

A system on chip (SOC) includes a clock generator to provide one or more on-chip reference clocks to a number of physical medium attachments (PMAs) across a common clock bus. The clock generator receives one or more external, off-chip clock lines, from which it generates the on-chip reference clocks. Each of the PMAs may operate data input/output (I/O) channels under a variety of different communications protocols, which can have common or distinct reference clock frequencies. Accordingly, the on-chip reference clocks are generated to provide the required reference clocks to each of the PMAs.

A control device for influencing a flow of energy in a load circuit between an electrical voltage source and an electrical load, having a semiconductor switch including a conductive section which is formed between an input connection and an output connection, can be looped into the load circuit, and has an electrical resistance adjustable by means of an electrical potential which can be applied to a control connection associated with the semiconductor switch, and having a control circuit which is coupled to the control connection and includes a freewheeling means connected in parallel to the load. The control circuit is designed to supply a control current at the control connection which is proportional to a voltage via the freewheeling means.

An electronic component comprising a half bridge adapted for operation with an electrical load having an operating frequency is described. The half bridge comprises a first switch and a second switch each having a switching frequency, the first switch and the second switch each including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first switch and the second terminal of the second switch are both electrically connected to a node. The electronic component further includes a filter having a 3 dB roll-off frequency, the 3 dB roll-off frequency being less than the switching frequency of the switches but greater than the operating frequency of the electrical load. The first terminal of the filter is electrically coupled to the node, and the 3 dB roll-off frequency of the filter is greater than 5 kHz.

To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance control circuits for controlling the unit buffers, and a control circuit unit for controlling the impedance control circuits. The impedance control circuits and the control circuit unit operate by mutually-different power supplies, the control circuit unit supplies pull-up data and pull-down data in mutually reverse phase to the impedance control circuits, and the impedance control circuits convert the pull-up data and the pull-down data from reverse phase to in-phase and supply the same to the unit buffers. Thereby, a noise is difficult to occur in a power supply VDD used for the control circuit unit.

A switching device driving apparatus for preventing arm short circuit is provided, including: a first switching device driving unit for receiving a control signal for controlling a first switching device and a second switching device so that they will not turn ON at the same time and outputting an ON/OFF drive signal to the first switching device; and a second switching device driving unit for receiving the control signal and outputting an ON/OFF drive signal to the second switching device, in which the first switching device driving unit outputs a drive signal for increasing the delay of the ON timing of the first switching device with respect to the OFF timing of the second switching device with increase in ambient temperature.

An output buffer comprises a series connection of a first field effect transistor and a second field effect transistor, wherein the first field effect transistor is connected to a first supply potential terminal and the second field effect transistor is connected to a second supply potential terminal. An output terminal is connected to a common connection of the first transistor and the second transistor. The output buffer has a series connection of a resistive element and a capacitive element, wherein the capacitive element is connected to the output terminal, and a control circuit, to which an input signal is provided. The control circuit controls the transistors in such a way that turning off of a transistor is performed immediately, while turning on of a transistor is performed depending on the charging or discharging of the capacitive element, thus achieving a defined slew rate of the output signal at the output terminal.

A circuit includes a first power node at a first voltage level, a second power node at a second voltage level, a first voltage driver, a first current driver, and a control unit. The first voltage driver is configured to electrically couple a first output node to the first power node when a first input signal at the first input node is at a first logic state, and electrically couple a first output node to the second power node when the first input signal is at a second logic state. The first current driver is configured to inject or extract a first adjustment current into or out of a first output node. The control unit is configured to generate a measurement result of the first voltage level, and to set the first adjustment current according to the measurement result.

A frequency tripler device is disclosed. The frequency tripler device includes a first graphene based field effect transistor (FET) of a first dopant type, having a gate, a drain, and a source, and a second graphene based FET of a second dopant type, having a gate, a drain, and a source, the gate of the first FET coupled to the gate of the second FET and coupled to an input signal having an alternating current (AC) signal of a first frequency, the combination of the first and second FETs generates an output signal with a dominant AC signal of a frequency of about three times the first frequency.

A sequence circuit includes first through third signal terminals, first through ninth resistors, and first through fifth electronic switches. The sequence circuit receives a first signal through the first signal terminal. The sequence circuit receives a second signal through the second signal terminal. The sequence circuit outputs a third signal through the third signal terminal. The sequence circuit is used to ensure the sequence of the first through third signals.

A semiconductor device including an integrator circuit, in which electric discharge from a capacitor can be reduced to shorten time required for charging the capacitor in the case where supply of power supply voltage is stopped and restarted, and a method for driving the semiconductor device are provided. One embodiment has a structure in which a transistor with small off-state current is electrically connected in series to a capacitor in an integrator circuit. Further, in one embodiment of the present invention, a transistor with small off-state current is electrically connected in series to a capacitor in an integrator circuit; the transistor is on in a period during which power supply voltage is supplied; and the transistor is off in a period during which supply of the power supply voltage is stopped.

A digital phase locked loop (DPLL), a method of operating the same, and a device including the same are provided. The DPLL includes a digitally-controlled oscillator configured to change a frequency and a phase of an output oscillation signal in response to a digital control code; a main divider configured to divide the frequency of the output oscillation signal and generate a first feedback signal based on the divided frequency; and a phase-to-digital converter configured to subdivide the phase of the output oscillation signal and to generate a quantized code by converting a phase difference between a reference signal and the first feedback signal using a phase-subdivided signal resulting from the subdivision. The digital control code is generated based on the quantized code.

Methods, systems, and apparatuses are described for compensating for an undesired fractional spur due to a PLL in a communication system. The communication system includes a time-to-digital converter (TDC) that is configured to execute in parallel to the PLL. The TDC is configured to determine a phase difference between a reference frequency and an output oscillation signal provided by the PLL. The phase difference is received by a processor to estimate particular characteristics of the undesired fractional spur, and the estimate of the characteristics is used to construct an estimate of the undesired fractional spur.

A system and method are disclosed to accomplish power savings in an electronic device, such as a memory chip, by performing selective frequency locking and subsequent instantaneous frequency switching in the DLL (delay locked loop) used for clock synchronization in the electronic device. By locking the DLL at a slow clock frequency, the operational frequency may be substantially instantaneously switched to an integer-multiplied frequency of the initial locking frequency without losing the DLL lock point. This DLL locking methodology allows for faster frequency changes from higher (during normal operation) to lower (during a power saving mode) clock frequencies without resorting to gradual frequency slewing to conserve power and maintain DLL locking. Hence, a large power reduction may be accomplished substantially instantaneously without adding complexity to the system clock generator. Because of the rules governing abstracts, this abstract should not be used in construing the claims.

A receiver circuit includes a first amplification unit, a second amplification unit, a first equalizing unit, and a second equalizing unit. The first amplification unit is configured to differentially amplify an input signal and a reference signal and generate a first intermediate output signal and a second intermediate output signal. The second amplification unit is configured to differentially amplify the first and second intermediate output signals and generate an output signal. The first equalizing unit is configured to control the level of the second intermediate output signal in response to the output signal. And the second equalizing unit is configured to control the level of the first intermediate output signal in response to the output signal.

Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.

A semiconductor storage device which stops and resumes the supply of power supply voltage without the necessity of saving and returning a data signal between a volatile storage device and a nonvolatile storage device is provided. In the nonvolatile semiconductor storage device, the volatile storage device and the nonvolatile storage device are provided without separation. Specifically, in the semiconductor storage device, data is held in a data holding portion connected to a transistor including a semiconductor layer containing an oxide semiconductor and a capacitor. The potential of the data held in the data holding portion is controlled by a data potential holding circuit and a data potential control circuit. The data potential holding circuit can output data without leaking electric charge, and the data potential control circuit can control the potential of the data held in the data holding portion without leaking electric charge by capacitive coupling through the capacitor.

A storage cell having a pulse generator and a storage element is proposed. The storage element input is connected to receive a data input signal. The storage element output is connected to provide a data output signal. The storage element is operable in one of a data retention state and a data transfer state in response to a storage control signal received from the pulse generator. The pulse generator is connected to receive a clock signal with rising and falling clock signal edges and is adapted to provide control pulses in the storage control signal. Each control pulse has a leading edge and a trailing edge. The control pulses have a polarity suited to invoke the data transfer state on their leading edges. The novel feature is that the pulse generator is adapted to initiate a rising-edge control pulse when receiving a rising clock signal edge and to initiate a falling-edge control pulse when receiving a falling clock signal edge. In this way, a dual-edge-triggered flip-flop may be made using only combinatorial logic circuitry and one level- or single-edge-triggered storage element. The storage cell has low power consumption, facilitates scan testing and can be used by existing design tools and test equipment.

A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.

A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.

Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed.

A noise resistant switch control circuit is provided. The circuit includes a low pass filter configured to couple to a first terminal of a switch and a first voltage clamp coupled to the low pass filter. The first voltage clamp is configured to couple to a control terminal of the switch and limit a voltage of the control terminal relative to the first terminal to within a first clamping range. The circuit includes a second voltage clamp coupled to an input terminal of the switch control circuit. The second voltage clamp is configured to couple to the control terminal of the switch. The second voltage clamp is further configured to reduce a level of a control voltage coupled to the second voltage clamp. The circuit includes a bias device configured to couple to the control terminal of the switch and to impress a biasing voltage to the control terminal.

A semiconductor device prevents recognition failure in mutual recognition between a host and a device compliant with USB Specifications. The semiconductor device includes: an interterminal opening/closing section having a plurality of first conductivity type MOS transistors, the respective sources or drains of which are cascaded, in which the source or drain of a first-stage MOS transistor among the cascaded MOS transistors is used as a first terminal, the source or drain of a final-stage MOS transistor among the cascaded MOS transistors is used as a second terminal, and the respective gates of the cascaded MOS transistors receive a control signal for controlling the opening or short-circuiting between the first and second terminals; and a current bypass section that reduces a current flowing into either one connection node coupling the respective sources or drains of the cascaded MOS transistors.

A transistor being one of an IGBT and a MOSFET and arranged near a gate control circuit applies a gate control signal from the gate control circuit to the gate of a transistor arranged far from the gate control circuit. A gate control signal is applied via a resistive element to the transistor arranged near the gate control circuit.

An apparatus includes a biquad filter having first and second lossy integrators and multiple input networks. Each lossy integrator includes an amplifier, and each input network is coupled to an input of the amplifier in one of the lossy integrators. Each input network includes multiple resistors and a capacitor arranged in a T-structure. In a single-ended configuration, each input network includes a grounded capacitor. In a fully-differential configuration, each input network includes one of: a grounded capacitor and a floating capacitor coupled to another input network. The amplifiers and resistors could form a portion of an integrated circuit chip, which also includes multiple input/output pins. A single grounded capacitor could be coupled to a single input/output pin of the integrated circuit chip for an input network. A single floating capacitor could be coupled to two input/output pins of the integrated circuit chip for a pair of input networks.

Operation of a charge pump is controlled to optimize power conversion efficiency by using an adiabatic mode with some operating characteristics and a non-adiabatic mode with other characteristics. The control is implemented by controlling a configurable circuit at the output of the charge pump.

A power package is provided comprising a packaged transistor and a driving unit connected to the transistor and adapted to drive the transistor. A control terminal of the transistor is connected to a middle terminal pin of the housing of the transistor and outer terminal pins of the housing are connected to the driving unit and to a voltage level, respectively, wherein the connections are crossing free.

A phase locked loop (PLL) includes a first loop, a second loop, and a lock detector. The first loop locks a feedback signal having a frequency equal to a fraction of a frequency of an output signal to a reference signal in phase. The first loop has a first bandwidth. The second loop locks the feedback signal to the reference signal in frequency and has a second bandwidth. The first bandwidth is higher than the second bandwidth. The lock detector is coupled to the second loop and increases the second bandwidth in response to detecting that the feedback signal is not locked to the reference signal.

A method of controlling an integrated circuit chip including first and second clock sources, the first clock source being more thermally stable and having a higher power consumption, the integrated circuit chip being operable in a first mode in which the first clock source is inactive and the second clock source active and in a second mode in which the first and second clock sources are active, the method including operating the integrated circuit chip in the first mode; taking a measurement indicative of temperature; if the measurement indicates that the temperature is outside of a temperature band: activating the first clock source so as to operate the integrated circuit chip in the second mode; recalibrating the second clock source against the first clock source; and following the recalibration, deactivating the first clock source so as to return the integrated circuit chip to the first mode.

A power management device of a touchable control system includes a boost circuit, a storage circuit, a detection circuit and a loading circuit. The boost circuit has an output terminal and generates an output voltage. The storage circuit electrically connects to the output terminal of the boost circuit and stores the output voltage. The detection circuit electrically connects to the storage circuit so as to detect the output voltage. The loading circuit electrically connects or disconnects to the output terminal of the boost circuit according to a predetermined value of the output voltage.

An integrated circuit includes a circuit block to utilize a load current at a load voltage from a power input and two or more charge pump arrays. The outputs of the charge pump arrays are coupled to the power input of the circuit block. The integrated circuit includes one or more modifiable elements to disable one or more of the two or more charge pump arrays.

The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.

A semiconductor structure including a device configured to receive an input data-word. The device including a logic structure configured to generate an encrypted data-word by encrypting the input data-word through an encrypting operation. The device further including an eFuse storage device configured to store the encrypted data-word as eFuse data by blowing fuses in accordance with the encrypted data-word.

Methods, systems, and computer readable media for wideband frequency and bandwidth tunable filtering are disclosed. According to one aspect, the subject matter described herein includes a wideband frequency and bandwidth tunable filter that splits a filter input signal into first and second input signals, modifies the first input signal to produce a first output signal, modifies the second input signal to produce a second output signal having an intermediate frequency response, and combines the first and second output signals while adjusting their relative phases and/or amplitudes to produce a filter output signal with the target frequency response. Adjustment includes splitting the second input signal into third and fourth input signals, which are modified and then combined to produce the second output signal having the intermediate frequency response.

A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.

In one example implementation, the present disclosure provides a direct current (DC) restoration circuit for restoring the DC component of a synchronization signal provided over an alternating current (AC) coupled link from a transmitting circuit to a receiving circuit. During a period of inactivity in the synchronization signal, the synchronization signal may experience a drift towards the common mode, and may affect the ability for the synchronization signal to properly trigger the receiving circuit. The DC restoration circuit is configured to hold the synchronization signal steady during the period of inactivity, and allow the AC component of the synchronization signal pass through to the receiving circuit during the period of activity to alleviate the problem of baseline drift in the synchronization signal.

Apparatus and methods for ultrasound transmit switching are provided. In certain implementations, a transmit switch includes a bias polarity control circuit, a bias circuit, a first high voltage field effect transistor (HVFET), and a second HVFET. The sources of the first and second HVFETs are connected to one another at a source node, the gates of the first and second HVFETs are connected to one another at a gate node, and the drains of the first and second HVFETs are connected to an input terminal and an output terminal, respectively. The bias circuit and the bias polarity control circuit are each electrically connected between the source node and the gate node. The bias polarity control circuit can turn on or off the HVFETs by controlling a polarity of a bias voltage across the bias circuit, such as by controlling a direction of current flow through the bias circuit.

This invention concerns a creepage control system for locomotives that optimizes adhesion while minimizing wasted energy, rail/wheel wear and shock loading on the drive train. The basis of the invention is to always maintain a small but positive value of the slope of the wheel-rail adhesion creep curve (or differential of adhesion versus creep) for all traction axles of the locomotive through microprocessor control. The value of the differential of adhesion versus creep is used to define an operating window for control and operation of motors continually in the optimum domain when high adhesion is demanded. When, due to a sudden increase in rail contamination, the value of the control function becomes negative, the microprocessor control reduces the generator excitation in stages until the function becomes positive and inside the operating window again. The microprocessor controls a rail cleaning system which is turned on or off depending on the cleanliness of the rail. It also controls a rail sanding system which is turned on or off depending on the magnitude of wheel creep.

A sand dispensing device designed to be carried in the trunk of a vehicle includes a housing having a partition forming two interior compartments. A supply of sand is stored in a first compartment and an electric air compressor is situated in a second compartment. A remote switch is operatively connected to a relay in the second compartment for energizing the compressor. An induction nozzle has a sand inlet extending through an aperture in the partition into the first compartment and is connected to an air supply tube connected to an output of the air compressor. An outlet tube in the second compartment has a first end connection to an outlet of the induction nozzle and a second end extending through a side wall of the housing. A pair of discharge tubes are connected by a quick release fitting to a second end of the outlet tube and a pair of discharge nozzles are provided on the discharge tubes for spraying a sand and air mixture adjacent drive wheels of the vehicle, to enhance traction on icy road surfaces. The device is conveniently removable from the vehicle trunk for replenishing the sand supply or for transferring between vehicles.