A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.

A charge pump circuit includes a capacitor, a first switch between the capacitor and a power supply terminal, a second switch between the capacitor and an output terminal, a third switch between the output terminal and the capacitor, a fourth switch between the capacitor and a ground terminal, and a control unit configured to generate control signals for the switches. The control signals include first signals generated during a first period that cause first and third switches to be in an ON state and second and fourth switches to be in an OFF state, second signals generated during a second period that cause first and third switches to be in an OFF state and second and fourth switches to be in an ON state, and third signals generated between the first and second periods, that cause the ON/OFF state of each of the switches to be switched at different times.

A control switch is connected to a power supply voltage and turns on based on a control signal to output a current. A clamp circuit is connected to a load and performs clamp control of the output voltage of the control switch. A current control element conducts or shuts off a current based on the output voltage to be clamp-controlled. A selector switch group includes switches, and performs switching based on a voltage varying with the current control by the current control element, thereby switching between paths for generating an internal power supply. The switch circuit connects or disconnects the coupling between the clamp circuit and the selector switch group.

An electrical circuit includes: at least one inductor, at least one varactor, and at least two transistors, all of which electrically arranged to form a voltage controlled oscillator (VCO) having an oscillation frequency; wherein the at least two transistors includes a first transistor and a second transistor; wherein the first transistor has a first bulk terminal and a first parasitic diode disposed between the first bulk terminal and the first transistor; wherein the second transistor has a second bulk terminal and a second parasitic diode disposed between the second bulk terminal and the second transistor; wherein application of a first control voltage to the first bulk terminal, application of a second control voltage to the second bulk terminal, or application of first and second control voltages to the first and second bulk terminals, respectively, is effective to change the oscillation frequency of the VCO.

An active filter device and a circuit arrangement comprising an active filter device are disclosed. In an embodiment the active filter device includes sensor terminals for applying a sensor signal depending on a sensed noise signal, an output terminal for providing a correction signal that is suitable for reducing the noise signal, a signal source adapted for generating a correction signal and a high-pass filter coupled between the sensor terminals and the signal source, wherein the correction signal is generated with a dependence on a high-pass filtered sensor signal.

An SR latch circuit with single gate delay is provided. The circuit has an an enable input and an SR latch. There is first input stage having an input for receiving a set input and having an output for producing a first component of the SR latch circuit output, the first input stage having only one transistor that receives the enable input, the first input stage becoming transparent while enabled, the first input stage having a single gate delay between the input of the first input stage and the output of the first input stage. There is a second input stage having an input for receiving a reset input and having an output for producing a second component of the SR latch circuit output, the second input stage having only one transistor that receives the enable input, the second input stage becoming transparent while enabled, the second input stage having a single gate delay between the input of the second input stage and the output of the second input stage.

A semiconductor device includes a first transistor and a clamping circuit. The first transistor is arranged to generate an output signal according to a control signal. The clamping circuit is arranged to generate the control signal according to an input signal, and to clamp the control signal to a predetermined signal level when the input signal exceeds the predetermined signal level.

A system includes a voltage-controlled oscillator (VCO) to generate an output signal based on an input voltage and a multi-stage delay network to receive the output signal from the VCO. Each stage of the delay network produces a phase-shifted output signal. The system includes a multi-stage digital-to-analog converter (DAC) network, where each stage of the DAC network is associated with a corresponding stage of the delay network. Each stage of the DAC network receives the phase-shifted output signal from its corresponding stage of the delay network and generates a weighted output signal based on the received phase-shifted output signal. The DAC network combines the weighted output signal of each stage. A weighting factor for each stage of the DAC network is selected to reduce harmonic content of the combination of weighted output signals.

The present disclosure relates to a delay control circuit arranged for adding delay to a signal. The delay control circuit includes a driver circuit arranged to receive a first signal and to output a second signal. The driver circuit includes a variable load arranged for outputting the second signal by adding delay to the first signal. The delay control circuit also includes a control circuit arranged to receive the first signal and to control the variable load of the driver circuit based on a current state of the first signal and on a control signal indicative of an amount of delay to be added to the first signal in the current state.

A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.

A load-driving circuit for receiving a supply of power from a power source and driving a load, wherein the load-driving circuit is provided with: a high-side switching element; a low-side switching element; a high-side current detection circuit connected in parallel to the high-side switching element, the high-side current detection circuit detecting a high-side driving current; and a fault detection circuit for detecting the fault state of the load-driving circuit from the output result of the high-side current detection circuit. The high-side current detection circuit is provided with a high-side sense switching circuit operating in response to a gate signal that is different from the high-side switching element, the high-side sense switching circuit comprising a device of the same type as the high-side switching element. The output result of the high-side current detection circuit, the gate signal of the high-side switching element, and the gate signal of the high-side sense switching element are input and the fault states are detected apart from each other when the connection terminal between the load-driving circuit and the load is in a state of short circuit with the positive electrode side of the power source or in a state of short circuit with the negative electrode side of the power source.

A track and hold circuit comprises an input buffer amplifier, a unit gain amplifier module, a sampling switch, a drive triode and a sampling capacitor. The input buffer amplifier receives an input signal. In a track phase, the sampling switch is electrically connected to an emitter electrode of the drive triode; the input signal charges the sampling capacitor after being buffered by the input buffer amplifier, amplified without distortion by the unit gain amplifier module and driven by the drive triode. In a hold phase, the sampling switch is electrically connected to a base electrode of the drive triode; the base voltage of the drive triode is pulled down until the drive triode is cut off; electrical charges on the sampling capacitor are thereby held, causing the signal to be held on the sampling capacitor.

A voltage-resistant switch is described. The switch comprises a signal input, a first FET transistor with a first channel with an extended drain and a first gate connector and a second FET transistor with a first channel with an extended drain and a second gate connector. A control signal connector is connected with the first gate connector and with the second gate connector via a second node and with the first channel and the second channel via a second resistor, and a signal connector is connected with the second channel. The voltage-resistant switch can be switched on and off.

A transmission circuit includes: a first transistor, a first current source, a third transistor. The first transistor has a source terminal coupled to a first reference voltage terminal of the transmission circuit and a drain terminal coupled to a first output terminal of the transmission circuit. The first current source is coupled between a gate terminal of the first transistor and a second reference voltage terminal of the transmission circuit. The third transistor has a drain terminal coupled to the first output terminal of the transmission circuit, a source terminal coupled to the second reference voltage terminal of the transmission circuit, and a gate terminal for receiving a first input signal. The first transistor is of a first conducting type, and the second transistor is of a second conducting type different from the first conducting type.

A high-voltage electronic switch includes first and second transistors defining a current flow path between an input and output of the switch. The transistors have a common point of the current flow path and a common control terminal. A control circuit includes a voltage line receiving a limit operating voltage and first and second branches coupled between the voltage line and the common point and common control terminal, respectively. Further transistors are activated, upon turning-off of the first and second transistors, for coupling the branches to the voltage line. The branches include a parallel connected resistor, diode, and string of diodes with opposite polarities. The diode of the first branch plus string of diodes of the second branch and diode of the second branch plus string of diodes of the first branch provide coupling paths between the voltage line and, respectively, the common point and common control terminal.

Capacitors connected between gate terminals of a plurality of parallel-connected power transistors are charged and discharged in each switching cycle to provide a plurality of power transistor control waveforms from a single gate driver waveform that equalize power losses/temperatures or steady-state currents among the plurality of power transistors. The capacitors are charged to different voltages by diverting current from one transistor driver by disabling another power transistor driver at different respective times in response to measured transient or steady state current or temperature or other operational parameter.

An integrated circuit includes a drive circuit with a first inverter circuit with a first transistor of a first conductivity type and a second transistor of a second conductivity type. The drains of the first and second transistors are connected. An output circuit is provided having a third transistor of the second conductivity with a gate connected to the drains of the first and second transistors. A capacitor is connected between the gate and a drain of the third transistor and has a capacitance greater than 0.5 pF and less than or equal to 3.0 pF. A gate width of the first transistor when divided by a gate width of the third transistor has a value of less than 1/100. The output circuit is configured to output a transmission signal from the drain of the third transistor.

A solid state power control apparatus includes: (a) at least one IGBT and at least one FET, for supplying current to a load, and (b) a current controller for shutting off the IGBT and FET. The current controller is arranged to start shut off of the IGBT before it starts shut off of the FET. Further, the current controller is arranged to reduce current flow prior to start of the turn off of the IGBT and FET.

A signal transfer circuit may include a pass gate coupled between first and second nodes; and a control unit suitable for controlling the pass gate to prevent a current flowing from the second node to the first node during turn-on of the pass gate.

A sampling circuit for sampling an input voltage and generating an output voltage, comprising six switches, a capacitor and a voltage buffer. The first switch has a control terminal and makes the output voltage equal to the input voltage when switching on. The second switch is coupled to a first terminal of the capacitor and a first level. The third switch is coupled to a second terminal of the capacitor and a second level. The fourth switch is coupled to the first terminal of the capacitor and the control terminal. The fifth switch is coupled to the control terminal and the second level. The voltage buffer has large input impedance, and has an input receiving the input voltage, an output providing a voltage equal or close to the input voltage. The sixth switch is coupled to the second terminal of the capacitor and the output of the voltage buffer.

A transmitter includes: a main pull-up driver suitable for pull-up driving an output node; and an auxiliary pull-up driver suitable for pull-up driving the output node based on a voltage of the output node, wherein the auxiliary pull-up driver compensates for non-linear driving current characteristics of the main pull-up driver.

A duty cycle correction circuit may include: a phase mixing section capable of mixing a first integrated signal generated by integrating a positive clock signal, with a first compensation signal generated by differentiating and integrating the positive clock signal and a negative clock signal, respectively, to generate a first phase-mixed signal, and mixing a second integrated signal generated by integrating the negative clock signal, with a second compensation signal generated by integrating and differentiating the positive clock signal and the negative clock signal, respectively, to generate a second phase-mixed signal; and a noise removal section capable of receiving and removing a common mode noise between the first phase-mixed signal and the second phase-mixed signal by adjusting a cross-point therebetween, and outputting first and second duty-corrected clock signals.

One example discloses an apparatus for power management, including: a circuit having a first power-domain and a second power-domain; wherein the first and second power-domains include a set of operating parameter values; a circuit controller configured to incrementally sweep at least one of the operating parameter values of the first power-domain; a circuit profiler configured to derive a total power consumption profile of the circuit based on the circuit's response to the swept operating parameter value; wherein the circuit controller sets the operating parameter values for the first and second power-domains based on the total power consumption profile of the circuit.

A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a correction code generator configured to generate a reference correction code according to a duty detection signal based on a phase difference between the pair of first reference clocks, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.

In some embodiments, a phase-locked loop (PLL) system comprises a phase-frequency detector (PFD) configured to compare a phase-frequency reference signal and a feedback signal, a charge pump (CP) electrically coupled to the PFD and configured to produce a first tuning signal based on an output of the PFD, multiple integrator cells electrically coupled to the CP and configured to output multiple second tuning signals based on a voltage of the first tuning signal relative to a voltage reference signal, and a voltage-controlled oscillator (VCO) electrically coupled to the CP and to the multiple integrator cells and configured to adjust a capacitance value of the VCO based on the multiple second tuning signals. The capacitance value and the first tuning signal affect a frequency of the feedback signal.

A loop filter with an active discrete-level loop filter capacitor can be used in a VCO (such as for CDR). A loop filter capacitor function is simulated by sensing input loop filter current (such as with a current mirror and source follower in the input leg), and forcing back a loop filter (VCO) control voltage. Loop filter voltage control is provided using a VDAC with a discrete-level VDAC feedback voltage, incremented/decremented based on the sensed loop filter current. In one embodiment, the VDAC voltage is provided as the non-inverting input to an amplifier, with the inverting input providing the control voltage, forced to the VDAC feedback voltage. The VDAC feedback voltage can be provided by increment/decrement comparators based on a voltage deviation on a C2 capacitor (from a reference voltage) that receives the sensed loop filter current (effectively multiplying the C2 capacitance to provide a simulated loop filter capacitance).

A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider, a phase error processing circuit, a phase frequency detector and a phase alignment circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit generates a charge pump output in a calibration mode. The type II loop filter generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider performs frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit outputs an adjusting signal by comparing a reference signal with the feedback signal. The phase frequency detector generates a detection signal by comparing the feedback signal and the reference signal. The phase alignment circuit generates a second control signal in the calibration mode.

The present disclosure is directed to multichannel transducer devices and methods of operation thereof. One example device includes at least two acquisition modules that have different sensitives and a signal processing stage that generates a blended signal representative of a lower gain signal mapped onto a higher gain signal. One example method of operation includes receiving a first signal from a first sensor having a first sensitivity, receiving a second signal from a second sensor having a second sensitivity that is different from the first sensitivity, generating a blended signal by mapping the second signal to the first signal, outputting the first signal while the first signal is below a first threshold and above a second threshold, and outputting the blended signal when the first signal is above the first threshold and when the first signal is below the second threshold.

An apparatus includes an integrated circuit (IC). The IC includes a power controller, which includes a regulator and a controller. The regulator receives a plurality of input voltages and provides a regulated output voltage. The controller controls the regulator to generate the regulated output voltage from the plurality of input voltages. The power controller provides power to a load integrated in the IC from a set of arbitrary input voltages. The set of arbitrary input voltages includes the plurality of input voltages.

The present invention is directed to an electronic switch device, the device including a housing assembly including a front cover assembly having a user accessible surface, a back body assembly, terminals configured to be coupled to an AC power source and the load; an antenna assembly including an antenna substrate disposed inside the housing assembly adjacent a portion of the front cover assembly, an antenna being disposed on the antenna substrate having a conductive grid structure; and a circuit assembly disposed inside the housing assembly coupled to the terminals, the circuit assembly comprising a printed circuit board, the printed circuit board including a ground plane, the circuit assembly being electrically connected to the antenna assembly via a conductor, the printed circuit board being separated from the antenna assembly by a predetermined distance, the circuit assembly including a relay switch having at least one solenoid winding connected to the circuit assembly and a set of contacts.

A power conversion system may include a plurality of power devices and a sensor operably coupled to at least one of the plurality of power devices and configured to detect a voltage, current, or electromagnetic signature signal associated with the plurality of power devices. The power converter may also include circuitry operably coupled to the plurality of power devices and the sensor. The circuitry may send a respective gate signal to each respective power device of the plurality of power devices, such that each respective gate signal is delayed by a respective compensation delay that is determined for the respective power device based on a respective time delay of the respective power device and a maximum time delay of the plurality of power devices.

An example circuit includes: a slew rate driver configured to provide an output voltage; a first voltage provider configured to provide a first input voltage to the slew rate driver in response to the output voltage being within a first range; and a second voltage provider configured to provide a second input voltage to the slew rate driver in response to the output voltage being within a second range. The slew rate driver is further configured to change the output voltage based at least in part on the first input voltage or the second input voltage.

A circuit suitable for data backup of a logic circuit is provided. The circuit includes first to fourth nodes, a capacitor, first to third transistors, and first and second circuits. Data can be loaded and stored between the circuit and the logic circuit. The first node is electrically connected to a data output terminal of the logic circuit. The second node is electrically connected to a data input terminal of the logic circuit. The capacitor is electrically connected to the third node. The first transistor controls electrical continuity between the first node and the third node. The second transistor controls electrical continuity between the second node and the third node. The third transistor controls electrical continuity between the second node and the fourth node. The first and second circuits have functions of raising gate voltage of the first transistor and raising gate voltage of the second transistor, respectively.

Devices are provided in which a metastable state can be detected in a memory device by means of a metastability detector. Corresponding information can be conveyed to a further device which, in dependence thereon, can process data from the memory device.

To provide a clock selection circuit capable of reducing clock omission generated when switching from a state of being synchronized with a first clock to a second clock. The clock selection circuit is equipped with a clock detection circuit which detects a first clock to output a detected signal, a switch which outputs the first clock when the detected signal is at a first level and outputs a second clock when the detected signal is at a second level different from the first level, and a one-shot circuit which outputs a one-shot pulse in response to switching of the detected signal from the first level to the second level. The output of the switch and the output of the one-shot circuit are added to be outputted as an output clock.

A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.

A clock-signal generator circuit, for generating an output clock signal starting from an input clock signal, includes: a monostable stage having a clock input configured to receive the input clock signal, a control input configured to receive a control signal, and an output configured to supply the output clock signal having a duty cycle variable as a function of the control signal; and a feedback loop, operatively coupled to the monostable stage for generating the control signal as a function of a detected value, and of a desired value, of the duty cycle of the output clock signal.

A double frequency-shift keying modulating device includes a modulation module. The modulation module receives an oscillating signal and a digital signal, and generates a modulation output signal that has a first frequency. The first frequency is associated with a frequency of the oscillating signal and varies periodically at a second frequency. The second frequency is associated with the digital signal and the frequency of the oscillating signal.

A device (442) for producing a dynamic reference signal (UREF) for a control circuit for a power semiconductor switch comprises a reference signal generator (442) for providing a dynamic reference signal (UREF), which has a stationary signal level after elapse of a predefined time following a switching process of the power semiconductor switch, a passive charging circuit (450) which is configured to increase a signal level of the dynamic reference signal in reaction to a switching of a control signal of the power semiconductor switch from an OFF state to ON state for at least one part of the predefined time above the stationary signal level, in order to produce the dynamic reference signal and an output (A) for tapping the dynamic reference signal (UREF).

In accordance with an embodiment, an adjustable capacitance circuit comprising a first branch comprising plurality of transistors having load paths coupled in series with a first capacitor. A method of operating the adjustable capacitance circuit includes programming a capacitance by selectively turning-on and turning-off ones of the plurality of transistors, wherein the load path of each transistor of the plurality of transistors is resistive when the transistor is on and is capacitive when the transistor is off.

A system includes a SiC semiconductor power device; a power supply board that is configured to provide power to a first gate driver board via a connector; the first gate driver board that is coupled and configured to provide current to the SiC semiconductor power device, wherein the first gate driver board is coupled to the power supply board via the connector, and wherein the first gate driver board is separated from the power supply board; and an interconnect board that is coupled to the first gate driver board, wherein the interconnect board is configured to couple the first gate driver board a second gate driver board.

A semiconductor apparatus may include a noise determination circuit, a strobe signal control circuit, and a reception circuit. The noise determination circuit may sense and determine noise of a reference voltage, and generate an up control signal and a down control signal. The strobe signal control circuit may adjust a transition timing of a strobe signal in response to the up control signal and the down control signal, and output a control strobe signal. The reception circuit may generate internal data signal in response to external data signal, the reference voltage, and the control strobe signal.

A half-bridge circuit comprises a high supply contact and a low supply contact. A half-bridge output contact is connectable to drive a load and has a high-side between the high supply contact and the half-bridge output contact and a low-side between the half-bridge output contact and the low supply contact. A high-side bidirectional vertical power transistor at the high-side has a source connected to the high supply contact, and a low-side bidirectional vertical power transistor at the low-side, transistor has a source connected to the low supply contact. The high-side bidirectional vertical power transistor and low-side bidirectional vertical power transistor are connected in cascode and share a common drain connected to the half-bridge output contact, and are controllable to alternatingly allow a current flow from the high supply contact to the half-bridge output contact or from the half-bridge output contact to the low supply contact.

A device for controlling a first control gate transistor, including: a second transistor and a third transistor series-connected between a first and a second terminals of application of a power supply voltage, the junction point of these transistors being connected to the gate of the first transistor; a terminal of application of a digital control signal; a circuit for generating an analog signal according to variations of the power supply voltage; and for each of the second and third transistors, a circuit of selection of a control signal of the first transistor representative of said digital signal or of said analog signal.

A driving circuit includes a first switching element operating in a turned-on state or a turned-off state depending on a control voltage; a second switching element operating complementarily to the first switching element depending on the control voltage; a constant voltage circuit unit turning on depending on a source-gate voltage of the first switching element to maintain a constant voltage; a current adjusting circuit operating in a turned-on state or a turned-off state depending on the control voltage, and adjusting an operating current flowing to a ground depending on a current control signal in the turned-on state of the current adjusting circuit; a current control circuit controlling the operating current by providing the current control signal to the current adjusting circuit in a turned-on state of the constant voltage circuit unit; and a signal transfer circuit providing the control voltage to a gate of the second switching element.

A radio-frequency (RF) switch includes a field-effect transistor (FET) disposed between a first node and a second node, the FET having a source, a drain, a gate, and a body. The RF switch further includes a coupling circuit including a first path and a second path, the first path being connected between the gate and one of the source or the drain via a first resistor in series with a first capacitor, the second path being connected between the body and the one of the source or the drain via a second resistor in series with a second capacitor, the coupling circuit configured to allow discharge of interface charge from either or both of the gate and body.

Methods and systems include constructing and operating a semiconductor device with a mid-band dopant layer. In various implementations, carriers that are optically excited in a mid-band dopant region may provide injection currents that may reduce transition times and increase achievable operating frequency in a bipolar junction transistor (BJT). In various implementations, carriers that are optically excited in a mid-band dopant region within a thyristor may improve closure transition time, effective current spreading velocity, and maximum rate of current rise.

A separator for a rechargeable battery and a rechargeable lithium battery, the separator including a porous substrate; and a heat-resistant porous layer on at least one surface of the porous substrate, wherein the heat-resistant porous layer includes a filler and a copolymer including a structural unit of vinylidenefluoride, a structural unit of hexafluoropropylene, and a structural unit of a carboxyl-containing monomer, the structural unit of hexafluoropropylene is present in an amount of about 4 wt % to about 10 wt %, based on a total weight of the copolymer, and the structural unit of a carboxyl-containing monomer is present in an amount of about 1 wt % to about 7 wt %, based on the total weight of the copolymer.

The present invention relates to processes that may be used singly or in combination to prevent lithium (or alkali metal) plating or dendrite buildup on bare substrate areas or edges of electrode rolls during alkaliation of a battery or electrochemical cell anode composed of a conductive substrate and coatings, in which the electrode rolls may be coated on one or both sides and may have exposed substrate on edges, or on continuous or discontinuous portions of either or both substrate surfaces.

The object of the present invention is to provide a positive electrode active material usable for a lithium ion battery capable of high charge/discharge cycle performance and high discharge capacity. The positive electrode active material for a lithium secondary battery has a layered structure and comprises at least nickel, cobalt and manganese. Further, the positive electrode active material satisfies requirements (1) to (3) below: (1) a primary particle size of 0.1 μm to 1 μm, and a 50% cumulative particle size D50 of 1 μm to 10 μm, (2) a ratio (D90/D10) of volume-based 90% cumulative particle size D50 to volume-based 10% cumulative particle size D10 of 2 to 6, and (3) a lithium carbonate content in a residual alkali on particle surfaces of 0.1% by mass to 0.8% by mass as measured by neutralization titration.