A method for forming a V-NAND device is disclosed. Specifically, the method involves deposition of at least one of semiconductive material, conductive material, or dielectric material to form a channel for the V-NAND device. In addition, the method may involve a pretreatment step where ALD, CVD, or other cyclical deposition processes may be used to improve adhesion of the material in the channel.

A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

Embodiments of the inventive concepts provide a method for manufacturing a semiconductor device. The method includes forming a stack structure including insulating layers and sacrificial layers which are alternately and repeatedly stacked on a substrate. A first photoresist pattern is formed on the stack structure. A first part of the stack structure is etched to form a stepwise structure using the first photoresist pattern as an etch mask. The first photoresist pattern includes a copolymer including a plurality of units represented by at least one of the following chemical formulas 1 to 3, wherein “R1”, “R2”, “R3”, “p”, “q” and “r” are the same as defined in the description.

A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.

A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.

Embodiments of the inventive concept provide a method for manufacturing a semiconductor device. The method includes forming a stack structure by alternately and repeatedly stacking insulating layers and sacrificial layers on a substrate, sequentially forming a first lower layer and a first photoresist pattern on the stack structure, etching the first lower layer using the first photoresist pattern as an etch mask to form a first lower pattern. A first part of the stack structure is etched to form a stepwise structure using the first lower pattern as an etch mask. The first lower layer includes a novolac-based organic polymer, and the first photoresist pattern includes a polymer including silicon.

The present invention provides a method for manufacturing the N-type TFT, which includes subjecting a light shielding layer to a grating like patternization treatment for controlling different zones of a poly-silicon layer to induce difference of crystallization so as to have different zones of the poly-silicon layer forming crystalline grains having different sizes, whereby through just one operation of ion doping, different zones of the poly-silicon layer have differences in electrical resistivity due to difference of grain size generated under the condition of identical doping concentration to provide an effect equivalent to an LDD structure for providing the TFT with a relatively low leakage current and improved reliability. Further, since only one operation of ion injection is involved, the manufacturing time and manufacturing cost can be saved, damages of the poly-silicon layer can be reduced, the activation time can be shortened, thereby facilitating the manufacture of flexible display devices.

A method of manufacturing a thin film transistor is disclosed. The method of manufacturing the thin film transistor includes: manufacturing a substrate; forming an oxide semiconductor layer on the substrate; forming a pattern including an active layer through a patterning process; forming a source and drain metal layer on the active layer; and forming a pattern including a source electrode and a drain electrode through a patterning process, an opening being formed between the source electrode and the drain electrode at a position corresponding to a region of the active layer used as a channel, wherein the step of forming the pattern including the source electrode and the drain electrode through a patterning process includes: removing a portion of the source and drain metal layer corresponding to the position of the opening through dry etching. The method may also be used to manufacturing a thin film transistor.

A method of forming image sensor packages may include performing a molding process. Mold material may be formed either on a transparent substrate in between image sensor dies, or on a removable panel in between transparent substrates attached to image sensor dies. Redistribution layers may be formed before or after the molding process. Mold material may be formed after forming redistribution layers so that the mold material covers the redistribution layers. In these cases, holes may be formed in the mold material to expose solder pads on the redistribution layers. Alternatively, redistribution layers may be formed after the molding process and the redistribution layers may extend over the mold material. Image sensor dies may be attached to a glass or notched glass substrate with dam structures. The methods of forming image sensor packages may result in hermetic image sensor packages that prevent exterior materials from reaching the image sensor.

A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.

A TFT and manufacturing method thereof, an array substrate and manufacturing method thereof, an X-ray detector and a display device are disclosed. The manufacturing method includes: forming a gate-insulating-layer thin film (3'), a semiconductor-layer thin film (4') and a passivation-shielding-layer thin film (5') successively; forming a pattern (5') that includes a passivation shielding layer through one patterning process, so that a portion, sheltered by the passivation shielding layer, of the semiconductor-layer thin film forms a pattern of an active layer (4a'); and performing an ion doping process to a portion, not sheltered by the passivation shielding layer, of the semiconductor-layer thin film to form a pattern comprising a source electrode (4c') and a drain electrode (4b'). The source electrode (4c') and the drain electrode (4b') are disposed on two sides of the active layer (4a') respectively and in a same layer as the active layer (4a'). The manufacturing method can reduce the number of patterning processes and improve the performance of the thin film transistor in the array substrate.

Manufacturing methods of JFET-type compact three-dimensional memory (3D-MC) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A JFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.

A method of forming a semiconductor device is provided such that a trench is formed in a semiconductor body at a first surface of the semiconductor body. Dopants are introduced into a first region at a bottom side of the trench by ion implantation. A filling material is formed in the trench. Dopants are introduced into a second region at a top side of the filling material. Thermal processing of the semiconductor body is carried out and is configured to intermix dopants from the first and the second regions by a diffusion process along a vertical direction perpendicular to the first surface.

A semiconductor device is provided that includes an n-type field effect transistor including a plurality of vertically stacked silicon-containing nanowires located in one region of a semiconductor substrate, and a p-type field effect transistor including a plurality of vertically stacked silicon germanium alloy nanowires located in another region of a semiconductor substrate. Each vertically stacked silicon-containing nanowire of the n-type field effect transistor has a different shape than the shape of each vertically stacked silicon germanium alloy nanowire of the p-type field effect transistor.

To provide a semiconductor device having improved reliability. After formation of an n+ type semiconductor region for source/drain, a first insulating film is formed on a semiconductor substrate so as to cover a gate electrode and a sidewall spacer. After heat treatment, a second insulating film is formed on the first insulating film and a resist pattern is formed on the second insulating film. Then, these insulating films are etched with the resist pattern as an etching mask. The resist pattern is removed, followed by wet washing treatment. A metal silicide layer is then formed by the salicide process.

A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.

A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.

A method for manufacturing an LDMOS device includes: providing a semiconductor substrate (200), forming a drift region (201) in the semiconductor substrate (200), forming a gate material layer on the semiconductor substrate (200), and forming a negative photoresist layer (204) on the gate material layer; patterning the negative photoresist layer (204), and etching the gate material layer by using the patterned negative photoresist layer (204) as a mask so as to form a gate (203); forming a photoresist layer having an opening on the semiconductor substrate (200) and the patterned negative photoresist layer (204), the opening corresponding to a predetermined position for forming a body region (206); and injecting the body region (206) by using the gate (203) and the negative photoresist layer (204) located above the gate (203) as a self-alignment layer, so as to form a channel region.

In some embodiments, a field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.

A method for producing an integrated power transistor circuit includes forming at least one transistor cell in a cell array, each transistor cell having a doped region formed in a semiconductor substrate and adjoining a first surface of the semiconductor substrate on a first side of the semiconductor substrate, depositing a contact layer on the first side, structuring the contact layer to form a contact structure from the contact layer, the contact structure having, in a projection of the cell array orthogonal to the first surface, a first section and, outside the cell array, a second section which connects the first section to an interface structure, and forming an electrode structure on and in direct contact with the first section in the orthogonal projection of the cell array, the electrode structure being absent outside the cell array.

A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.

Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.

Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.

A method is provided for making smooth crystalline semiconductor thin-films and hole and electron transport films for solar cells and other electronic devices. Such semiconductor films have an average roughness of 3.4 nm thus allowing for effective deposition of additional semiconductor film layers such as perovskites for tandem solar cell structures which require extremely smooth surfaces for high quality device fabrication.

Provided are superconducting circuits and, more specifically, methods of forming such circuits. A method may involve forming a silicon-containing low loss dielectric (LLD) layer over a metal electrode such that metal carbides at the interface of the LLD layer and electrode. The LLD layer may be formed using chemical vapor deposition (CVD) at a temperature of less than about 500° C. At such a low temperature, metal silicides may not form even though silicon containing precursors may come in contact with metal of the electrode. Silicon containing precursors having silane molecules in which two silicon atoms bonded to each other (e.g., di-silane and tri-silane) may be used at these low temperatures. The LLD layer may include amorphous silicon, silicon oxide, or silicon nitride, and this layer may directly interface one or more metal electrodes. The thickness of LLD layer may be between about 1,000 Angstroms and 10,000 Angstroms.

A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.

An organic layer deposition assembly for depositing a deposition material on a substrate includes a deposition source configured to spray the deposition material, a deposition source nozzle arranged in one side of the deposition source and including deposition source nozzles arranged in a first direction, a patterning slit sheet arranged to face the deposition source nozzle and having patterning slits in a second direction that crosses the first direction, and a correction sheet arranged between the deposition source nozzle and the patterning slit sheet and configured to block at least a part of the deposition material sprayed from the deposition source.

The invention relates to encapsulation structures for OLED displays, wherein the structure provides sufficient barrier properties against oxygen and moisture as well as anti-reflection properties. The structure includes a layer comprising a photo-aligned substance which in a synergistic manner controls both barrier and anti-reflection properties.

A method of forming microelectronic systems on a flexible substrate includes depositing a plurality of layers on one side of the flexible substrate. Each of the plurality of layers is deposited from one of a plurality of sources. A vertical projection of a perimeter of each one of the plurality of sources does not intersect the flexible substrate. The flexible substrate is in motion during the depositing the plurality of layers via a roll to roll feed and retrieval system.

An array substrate of organic light-emitting diodes and a method for fabricating the same are provided to narrow an edge frame of product device of organic light-emitting diodes, to shorten the package process time, and to improve the substrate utilization and the production efficiency. The array substrate of organic light-emitting diodes includes a plurality of display panels disposed in an array of rows and columns, wherein at least two adjacent display panels are connected through a frame adhesive, and there is no cutting headroom between at least one side of the at least two adjacent display panels.

One embodiment is a wide stripe semiconductor waveguide, which is cleaved at a Talbot length thereof, the wide stripe semiconductor waveguide having facets with mirror coatings. A system provides for selective pumping the wide stripe semiconductor waveguide to create and support a Talbot mode. In embodiments according to the present method and apparatus the gain is patterned so that a single unique pattern actually has the highest gain and hence it is the distribution that oscillates.

A side release buckle includes: a plug; and a socket, the plug including: a base; a pair of legs; and engaging portions, the socket including: a body; an insertion opening; a housing space; engaged portions; and a pair of guide surfaces. The guide surfaces, which are formed on an inner surface of the housing space and extend in an insertion direction of the legs while being opposed to each other, each include: a squeezing portion formed continuously with corresponding one of the engaged portions; and a guiding portion formed between the squeezing portion and the insertion opening. An interval between the guiding portions near the engaged portions is wider than an interval between the squeezing portions near the engaged portions. An inclination angle of each guiding portion to an insertion direction of the plug is smaller than an inclination angle of each of the squeezing portion to the insertion direction.

A tensioning device comprises an elongate member, preferably a band, and a frame having first and second sides. The band has a first end that is attachable to the first side of the frame and a second end that is releasably securable to the second side of the frame. A movable clamping member on the frame secures the second end of the band to the second side of the frame by cinching the second end of the band between an engagement surface on the band and a mating engagement surface on the second side of the frame. A restraining member is provided for restraining the clamping member to a first position spaced from the mating locking surface on the second side of the frame, when the restraining member is in a restraining orientation. The restraining member is movable out of the restraining orientation after the band is tensioned to a predetermined level using the second end. The band is tensioned to the aforementioned predetermined level and is secured to the second side of the frame, so that the band establishes a path of tension along its length that extends linearly between the two ends of the band.

An apparatus and method for carrying and storing a portion of rope is claimed. A portion of rope is braided and wound about two complementary loops. Attached to one complementary loop is a flexible fastener. The flexible fastener can be passed through the second complementary loop and attached to itself. The apparatus can then be worn as a bracelet. When the rope is needed, the person can unwind the rope. After using the rope, the rope can be rewound and then bound with the flexible fastener.

An elastic zip tie is integrally molded from foam rubber, and includes a long strip of strap, a head located at a front end of the strap, and a plurality of flexible grips axially spaced on an upper and a lower surface of the strap. At least one holding space is defined by between any two adjacent axially-spaced flexible grips. The head has a thickness defined between two lateral sides thereof and is substantially larger than a longitudinal length of the holding space, i.e., a distance between two adjacent flexible grips. When a tail end of the strap is extended through the head for the latter to rest on the strap in a selected holding space, the flexible grips located immediately before and behind the holding space are elastically pressed against the two opposite lateral sides of the head to thereby firmly hold the latter in the holding space.

Flash grip system is used to securely retain a USB flash drive or thumb drive and provide a comfortable, gripping surface. Further, the flash grip system may use an article-fastener such that the USB flash drive may be removably attached to a variety of articles (such as a keychain, a belt loop, a bag strap, etc). The holding surface may further include decorative indicia for decorating the USB flash drive.

A mountable cable tie with fine adjustment with an elongated strap having a first strap end and a second strap end, the elongated strap having one or more rows of teeth or cross-bars formed crosswise on the elongated strap, and a plurality of holes positioned linear along the median between the one or more rows of teeth, at least one locking buckle positioned proximate the second strap end, the at least one locking buckle having at least one channel and at least one locking tang or pawl positioned within the locking buckle, wherein increased insertion of the first strap end into the locking head decreases the size of the loop of the elongated strap to secure the bundle.

Substrates such as sheet metal components may be kept spaced apart from each other using a molded polymeric spacing device. The spacing device has a main body with a thickness corresponding to the desired minimum spacing between the substrates and, extending from the main body or a base connected to said main body, an attachment member capable of being inserted into an opening in one of the substrates, but resistant to being easily withdrawn from such opening. Noise and vibration that might otherwise be generated or propagated by closely proximate substrates are reduced through the use of such molded polymeric spacing devices, which may be integrally fashioned from a rubber.

Flexible retaining structures for body jewelry and method for their use.

The present invention provides an improvement in an article of jewelry of the type in which the ornamental portion of the article is secured or released selectively from the support portion of the article. The removable jewelry setting provides a simplified construction which is used readily by the wearer of jewelry to assemble a particular combination of ornament and support selected from a wide variety of such combinations made available by the improvement. The construction also enhances the ability to tailor a jewelry article to a particular style of dress without unduly multiplying the number of expensive ornaments required to provide a wide range of ornamented articles. The construction enables ease of interchange of the ornamental portion of an article of jewelry.

A watch comprising a watch case with opposite arranged connecting parts in form of two parallel branches for the mounting of a watch strap or cord between said branches, where said watch further comprises at least one generally T-shaped strap or cord connector comprising a spring loaded sliding bar suited for engaging in holes provided in a surface of each branch facing each other, said T-shaped strap or cord connector further comprises a cord receiving opening being arranged opposite to the spring loaded sliding bar and being an opening adapted to receive a cord having generally round or polygonal cross section, said cord at a first end and a second end being provided with interacting locking parts.

Self adjusting and/or locking buckle tongue assemblies for use with occupant restraint systems in vehicles are described herein. In one embodiment, a buckle tongue assembly includes a plate having a tongue portion configured to cooperatively engage a corresponding buckle assembly. The buckle tongue assembly of this embodiment can further include first and second web gripping portions carried by the plate. The second web gripping portion is configured to move relative to the first web gripping portion between a first position in which the web gripping portions are spaced apart to permit movement of a web therebetween, and a second position in which the web gripping portions are engaged or interlocked to clamp the web therebetween.

A copper-zinc alloy product of the invention contains zinc in an amount of higher than 35% by weight and 43% by weight or less and has a two-phase structure of an α-phase and a β-phase. Further, the ratio of the β-phase in the copper-zinc alloy is controlled to be higher than 10% and less than 40% and the crystal grains of the α-phase and the β-phase are crushed into a flat shape and arranged in a layer shape through cold working. According to the copper-zinc alloy product, it is possible to decrease the copper content and to appropriately secure the strength and cold workability by appropriately controlling the ratio of the β-phase.

A removable device for holding or clipping at least two pieces of paper, cardboard, plastic film or other sheets of material together. The paper clip includes a self biasing spring member for providing spring tension to hold an article to a flat substrate such as a piece of paper or papers and may include locking elements for removable engagement and holding of sheets of paper or the like together.

A wire gripping assembly for securing an electrical box or light fixture to a support. The wire gripping assembly includes a wire gripping device having a body with open channels and a through bore, a clip member having legs for sliding engagement within the channels, a cable having an end connector thereon, and a thumbscrew for adjusting the clip member with respect to the body. The thumbscrew includes a head having an outer circumference with serrations to enable hand tightening and an end with a slot for engagement by a screwdriver or similar tool. The wire gripping assembly eases installation of an electrical device to an overhead support by enabling a two-step connection including initial hand tightening using the serrated outer surface of the thumbscrew and subsequent secure tightening by engaging the slot of the thumbscrew with a screwdriver or similar tool.

Embodiments herein provide modified slider bodies with one or more features such as an elongated spring cap, a protrusion on the bottom plate and/or plate coupler of the slider body, and/or vertically offset side rails. These features may minimize introduction of loose fabric, such as the lining of a lined garment, into the tape slot of the slider body, thereby help reduce jamming of the slider body during operation of the slide fastener.

A Self-Aligning Zipper is disclosed that allows for one handed operation by anyone who would, otherwise use a zipper or use of the Self-Aligning Zipper by those with physical and developmental limitations or equipment such, as cold weather gloves or mittens. The proper alignment of each half of the Self-Aligning Zipper is accomplished by way of magnets of opposite polarity along with structural guide elements to ensure proper alignment and operation of the zipper.

A fastening strap and a manufacturing method thereof are provided. The fastening strap includes a first band and a second band. The first band has a first surface and a second surface. The first surface has a plurality of hooks of special configuration. The second band has a third surface and a fourth surface. The third surface is directly adhered to the second surface of the first band, and the fourth surface has a plurality of loops for being mechanically latched by the hooks on the first surface. The second surface and/or the third surface is printed with at least one pattern. After the first band and the second band are adhered together, the pattern can be seen from the first surface of the first band.