1 Brunei Dollar = 10.0919 Estonian Kroon

1 Brunei Dollar = 90.8085 Algerian Dinar

1 Brunei Dollar = 38.9457 Dominican Peso

1 Brunei Dollar = 4.8688 Danish Krone

1 Brunei Dollar = 17.7834 Czech Republic Koruna

1 Brunei Dollar = 402.5707 Costa Rican Colon

1 Brunei Dollar = 2757.1006 Colombian Peso

1 Brunei Dollar = 5.0056 Chinese Yuan Renminbi

1 Brunei Dollar = 584.3256 Chilean Peso

1 Brunei Dollar = 0.6871 Swiss Franc

1 Brunei Dollar = 0.9919 Canadian Dollar

1 Brunei Dollar = 8.5931 Botswana Pula

1 Brunei Dollar = 4.0562 Brazilian Real

1 Brunei Dollar = 4.8793 Bolivian Boliviano

1 Brunei Dollar = 0.2676 Bahraini Dinar

1 Brunei Dollar = 1.2775 Bulgarian Lev

1 Brunei Dollar = 60.1407 Bangladeshi Taka

1 Brunei Dollar = 1.0829 Australian Dollar

1 Brunei Dollar = 47.0351 Argentine Peso

1 Brunei Dollar = 1.2703 Netherlands Antillean Guilder

1 Brunei Dollar = 2.5991 United Arab Emirates Dirham

Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends upon how and where it is used and in part, because even the best IP may work better in one system than another—even in chips developed by the same vendor.  

So, how do you measure IP quality and why it is so complicated?

The answer depends on who is asking. Most of the time, the definition of IP quality depends on your vantage point.  If you are an R&D manager, IP quality means something. If you are a global supply manager, IP quality means something else. If you are an SoC start-up, your measure of quality is quite different from that of an established fabless company. If you are designing IP in-house, then your considerations are very different than being a commercial IP vendor. If you are designing an automotive SoC, then we are in a totally different category. How about as an IP vendor? How do you articulate IP quality metrics to your customers?

This varies greatly by the type of IP, as well. When it comes to interface (hard) IP and controllers, if you are an R&D manager, your goal is to design IP that meets the IP specifications and PPA (power, performance, and area) targets. You need to validate your design via silicon test chips. This applies to all hard PHYs, which must be mapped to a particular foundry process. For controllers that are in RTL form—we called these soft IP—you have to synthesize them into a particular target library in a particular foundry process in order to realize them in a physical form suitable for SoC integration. Of course, your design will need to go through a series of design validation steps via simulation, design verification and passing the necessary DRC checks, etc. In addition, you want to see the test silicon in various process corners to ensure the IP is robust and will perform well under normal process variations in the production wafers.

For someone in IP procurement, the measure of quality will be based on the maturity of the IP. This involves the number of designs that have been taped out using this IP and the history of bug reports and subsequent fixes. You will be looking for quality of the documentation and the technical deliverables. You will also benchmark the supplier’s standard operating procedures for bug reporting and technical support, as well as meeting delivery performance in prior programs. This is in addition to the technical teams doing their technical diligence.

An in-house team that is likely to design IP for a particular SoC project will be using an established design flow and will have legacy knowledge of last generation’s IP. They may be required to design the IP with some reusability in mind for future programs. However, such reusability requirements will not need to be as stringent and as broad as those of commercial IP vendors because there are likely to be established metrics and procedures in place to follow as part of the design team’s standard operating procedures. Many times, new development based on a prior design that has been proven in use will be started, given this stable starting point. All of these criteria help the team achieve a quality outcome more easily.

Then, if designing for an automotive SoC, additional heavy lifting is required.  Aside from ensuring that the IP meets the specifications of the protocol standards and passes the compliance testing, you also must pay attention to meeting functional safety requirements. This means adherence to ISO 26262 requirements and subsequently achieving ASIL certification. Oftentimes, even for IP, you must perform some AEC-Q100-related tests that are relevant to IP, such as ESD, LU, and HTOL.

To read more, please visit: https://semiengineering.com/why-ip-quality-is-so-difficult-to-determine/

Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components and calculation power to accommodate new performance-hungry applications such as machine learning and autonomous driving.  With increased number of SoC components, such as CPUs, GPUs, accelerators and I/O devices, comes increased demand to correctly model interoperability of various components. Traditional simulation of complex systems requires accurate models of all components comprising the system and normally results in very long simulation times. A better way is to create a set of typical traffic profiles which describe behavior of system’s masters and slaves. Such profiles should be abstract to be applied to various protocols and interfaces and be portable to be applied throughout different SoC design and verification cycles.

To address the challenges outlined above, Arm has recently announced availability of the AMBA® Adaptive Traffic Profiles (AMBA ATP) specification which lays foundation of a new synthetic traffic framework. The AMBA ATP specification includes detailed information of various transaction types and timing characteristics of those transactions. The traffic profiles defined in the specification are abstract in nature and thus could be used to generate stimuli for various standard AMBA protocols and in various environments such as RTL-based simulation, FPGA prototyping and final SoC verification. The traffic profiles outlined in the specification include a set of parameters to define timing relationships between transactions as well as timing relationships within individual transactions. Even though the traffic profile represents the behavior of a single agent it could be applied either in a concurrent manner (e.g. write and read traffic profiles running in parallel) or in a sequential manner (e.g. when one traffic completes before the next one start). Moreover, when simulating a reasonably complex system, it is possible to coordinate traffic profiles generated by multiple components. While providing abstract definition of traffic profiles, the AMBA ATP specification focuses on the use of traffic profiles with an AMBA AXI interface, outlining signaling, timing relationships between different transaction phases and between different transactions. The same application principles could be used to map the abstract traffic profiles to other AMBA protocols such as AMBA5 CHI protocol.  

To facilitate adoption of the AMBA Adaptive Traffic Profiles, Cadence has recently announced availability of SystemVerilog UVM ATP Sequence Layer which automatically implements mapping of an abstract ATP traffic to AMBA protocol specific traffic, generated by Cadence AMBA Verification IP. The ATP layer is implemented as a SystemVerilog UVM virtual sequence with the sequence item including all ATP transaction parameters as defined in the specification.

Using the provided sequence infrastructure, users can write tests to define and coordinate traffic profiles for various components in the system. The ATP Layer automatically converts the abstract traffic profile into AMBA protocol-specific traffic, e.g., AMBA5 CHI protocol traffic.

 A sample code below, shows an example of a read profile translated by Cadence ACE Verification IP in ACE protocol traffic.

   `uvm_do_with(ace_atp_vseq,                                            

                       {ace_atp_vseq.agentId == agent_id;                                // ATP agent id

                        ace_atp_vseq.atpDirection == ATP_READ;                    // direction of bursts issued by virtual sequence

                        ace_atp_vseq.startAddress == start_address;                // start of address range being accessed

                        ace_atp_vseq.endAddress == end_address;                  // end of address range being accessed

                        ace_atp_vseq.atpDomain == atp_domain;                      // domain to use for transactions

                        ace_atp_vseq.addressPattern == ATP_SEQUENTIAL;  // address pattern

                        ace_atp_vseq.transactionSize == 64;                             // number of bytes in each burst

                        ace_atp_vseq.dataSize == 4;                                          // number of bytes in each transfer

                        ace_atp_vseq.rate == 150.0/(50.0);                                // requestedBandwidth / clkFrequency

                        ace_atp_vseq.start == ATP_EMPTY;                              // start condition of the ATP FIFO

                        ace_atp_vseq.full == 128;                                               // full level of the ATP FIFO

                        ace_atp_vseq.numOfTransactions == 500;                    // number of bursts issued by this sequence

                        ace_atp_vseq.ARTV == 2;                                              // sub-transaction delay

                        ace_atp_vseq.RBR == 3;                                                // sub-transaction delay

                       });

In addition to the ATP Layer for Cadence Simulation-Based AMBA Verification IP, Cadence supports the ATP functionality in Acceleration-Based AMBA Verification IP. For detailed information about ATP support in Cadence Simulation-Based and Acceleration-Based Verification IP, visit ip.cadence.com.

With more and more SoCs employing sophisticated interconnect IP to link multiple processor cores, caches, memories, and dozens of other IP functions, the designs are enabling a new generation of low-power servers and high-performance mobile devices. The complexity of the interconnects and their advanced configurability contributes to already formidable design and verification challenges which lead to the following questions:

While your interconnect subsystem might have a correct functionality, are you starving your IP functions of the bandwidth they need? Are requests from latency-critical initiators processed on time? How can you ensure that all applications will receive the desired bandwidth in steady-state and corner use-cases?

To answer these questions, Cadence recommends the Performance Verification Methodology to ensure that the system performance meets requirements at the different levels:

1. Performance characterization: The first level of verification aims to verify the path-to-path traffic measuring the performance envelope. It targets integration bugs like clock frequency, buffer sizes, and bridge configuration. It requires to analyze the latency and bandwidth of design’s critical paths.
2. Steady state workloads: The second level of verification aims to verify the master-by-master defined loads using traffic profiles. It identifies the impact on bandwidth when running multi-master traffic with various Quality-of-Service (QoS) settings. It analyzes the DDR sub-system’s efficiency, measures bandwidth and checks whether masters’ QoS requirements are met.
3. Application specific use cases: The last level of verification simulates the use-cases and reaches the application performance corner cases. It analyzes the master-requested bandwidth as well as the DDR sub-system’s efficiency and bandwidth.

Cadence has developed a set of tools to assist customers in performance validation of their SoCs. Cadence Interconnect Workbench simplifies the setup and measurement of performance and verification testbenches and makes debugging of complex system behaviors a snap. The solution works with Cadence Verification IPs and executes on the Cadence Xcelium® Enterprise Simulator or Cadence Palladium® Accellerator/Emulator, with coverage results collected and analyzed in the Cadence vManager  Metric-Driven Signoff Platform.

To verify the performance of the Steady State Workloads, Arm has just released a new AMBA Adaptive Traffic Profile (ATP) specification which describes AMBA abstract traffic attributes and defines the behavior of the different traffic profiles in the system.

With the availability of Cadence Interconnect Workbench and AMBA VIP support of ATP, early adopters of the AMBA ATP specification can begin working immediately, ensuring compliance with the standard, and achieving the fastest path to SoC performance verification closure.

For more information on the AMBA Adaptive Traffic Profile, you can visit Dimitry's blog on AMBA Adaptive Traffic Profiles: Addressing The Challenge. 

More information on Cadence Interconnect Workbench solution is available at Cadence Interconnect Solution webpage.

Thierry

Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs.

Semiconductor designers have long been making test chips to validate test structures, memory bit cells, larger memory blocks, and precision analog circuits like current mirrors, PLLs, temperature sensors, and high-speed I/Os. This has been done at 90nm, 65nm, 40nm, 32nm, 28nm, etc., so having test chips at 16nm, 7nm, or finer geometries should not be a surprise. Still, as costs rise, there is debate about whether those chips are over-used given advancements in tooling, or whether they should be utilized even more, with more advanced diagnostics built into them.

Modern EDA tools are very good. You can simulate and validate almost anything with certain degree of accuracy and correctness. The key to having good and accurate tools and accurate results (for simulation) is the quality of the foundry data provided. The key to having good designs (layouts) is that the DRC deck must be of high quality and accurate and must catch all the things you are not supposed to do in the layout. Most of the challenges in advanced node is in the FEOL where semiconductor physics and lithography play outsize roles. Issues that were not an issue at more mature nodes can manifest themselves as big problems at 7nm or 5nm. Process variation across the wafer and variation across a large die also present problems that were of no consequence in more mature nodes.

The real questions to be asked are as follows:

What is the role of test chips in SoC designs?

1. Do all hard IP require test chips for validation?
2. Are test chips more important at advanced nodes compared to more mature nodes?
3. Is the importance of test chip validation relative to the type of IP protocols?
4. What are the risks if I do not validate in silicon?

In complex SoC designs, there are many high-performance protocols such as LPDDR4/4x PHY, PCIe4 PHY, USB3.0 PHY, 56G/112G SerDes, etc. Each one of these IP are very complex in and by itself. If there is any chance of failure that is not detected prior to SoC (tapeout) integration, the cost of retrofit is huge. This is why the common practice is to validate each one of these complex IP in silicon before committing to use such IP in chip integration. The test chips are used to validate that the IP are properly designed and meet the functional specifications of the protocols. They are also used to validate if sufficient margins are designed into the IP to mitigate variances due to process tolerances. All high-performance hard IP go through this test chip/silicon validation process. Oftentimes, marginality is detected at this stage. In advanced nodes, it is also important to have the test chips built under different process corners. This is intended to simulate process variations in production wafers so as to maximize yields. Advanced protocols such as 112G, GDDR6, HBM2, and PCIe4 are incredibly complex and sensitive to process variations. It is almost impossible to design these circuits and try to guarantee their performance without going through the test chip route.

Besides validating performance of the IP protocols, test silicon is also used to validate robustness of ESD structures, sensitivity to latch up, and performance degradation over wide temperature ranges. All these items are more critical in advanced nodes than more mature modes. Test chips are vehicles to guarantee design integrity in bite-size chunks. It is better to deal with any potential issues in smaller blocks than to try to fix them in the final integrated SoC.

Test chips will continue to play a vital role in helping IP and SoC teams lower the risk of their designs, and assuring optimal quality and performance in the foreseeable future. They are not going away!

To read more, please visit https://semiengineering.com/test-chips-play-larger-role-at-advanced-nodes/

Verification of a USB4 router design is not just about USB4 but also about the inclusion of the three other major protocols namely, USB3, DisplayPort (DP), and PCI Express (PCIe). These protocols can be simultaneously tunneled through a USB4 router. Put in simple terms, such tunneling involves the conversion of the respective native USB3, DP, or PCIe protocol traffic into the USB4 transport layer packets, which are tunneled through a USB4 fabric, and converted back into the respective original native protocol traffic.

It may sound simple but is perhaps not.

There are several aspects in a router that come into picture to carry out this task of conversion of native protocol traffic, route it to the intended destination, and then convert it back to the original form. Some of those are the USB3, DP and PCIe protocol adapters, transport mechanism using routing, flow control, paths, path set-up and teardown, control and configuration, configuration spaces.

That is not all. There are core USB4 specific logical layer intricacies as well, which carry out the tasks of ensuring that all the USB4 ports and links are working as desired to provide up to 40Gbps speed and that the USB4 traffic flows through out the fabric in the intended way. These bring on the table features like High Speed link, ordered sets, lane initialization, lane adapter state machine, low power, lane bonding, RS-FEC, side band channel, sleep and wake, error checking.

All of these put together give rise to a very large verification space against which a USB4 router design should be verified. If we were to break down this space it can be broadly put in the following major dimensions,

• Protocol Adapter Layer
  • USB3 tunneling
  • DP tunneling
  • PCIe tunneling
• Host Interface Adapter Layer
• Transport Layer
  • Flow control
  • Routing
  • Paths
• Configuration layer and control packet protocol
• Configuration spaces
• Logical Layer

The independent verification of these dimensions is not all that would qualify the design as verified. They have to be verified in various combinations of each other too. Overall, all the parts of a USB4 router system need to be working together coherently.

For example, the following diagram depicts the various layers that a USB4 router may comprise of,

A USB4 router or a domain of routers does not work on its own. There is a Connection Manager per domain, which is a software-based entity managing a domain. A router provides the various capabilities for a Connection Manager to carry out its responsibilities of managing a domain.

It would not be an exaggeration to say that the spectrum of verification of a USB4 router ranges from the very minute details of logical layer to the system-level like multiple dependencies as the whole USB4 system is brought up layer by layer, step-by-step.

Cadence has a mature Verification IP solution that can help in the verification of USB4 designs. Cadence has taken an active part in the working group that defined the USB4 specification and has created a comprehensive Verification IP that is being used by multiple members in the last two years.

If you plan to have a USB4 compatible design, you can reduce the risk of adopting a new technology by using our proven and mature USB4 Verification IP. Please contact your Cadence local account team for more details and to get connected.

The PCI-SIG finalized the PCIe 4.0 specification with doubling the data to 16GT/s from 8GT/s in PCIe 3.0 in 2017. Products implementing this technology have begun to hit the market in 2019. Earlier this year, AMD announced it X570 chipset would support the PCIe 4.0 interface and Phison also introduced the world’s first PCIe 4.0 SSD.  With the increasing companies are working on PCIe 4.0 related product development, Cadence, as the key and leading PCIe IP solution vendor in the market, has strived for continuous enhancement of its PCIe 4.0 to be the best in the class IP solution. From our initial PCIe 4.0 solution in 4 years ago (revealed in 2015), we have made many advancements and improvements adding features such as Multi-link with any lane assignment, U.2/U.3 connector, and Automotive support. The variety of applications that PCIe4 finds a home in require extensive robustness and reliability testing over and above the compliance tests mandated by the standard body, i.e., PCI-SIG.

PCIe 4.0 TX Eye-Diagram, Loop-back Test (Long-reach) and RX JTOL Margin Test

Cadence IP team has also implemented additional "stress tests" in conjunction to its already comprehensive IP characterization plan, covering electrical, functional, ESD, Latch-up, HTOL, and yield sorting. Take the Receiver Jitter Tolerance Test (JTOL) for instance. JTOL is a key index to test the quality of the receiver of a system. This test use data generator/analyzer to send data to a SerDes receiver which is then looped back through the transmitter back to the instrument. The data received is compared to the data generated and the errors are counted. The data generator introduce jitter into the transmit data pattern to see how well the receiver functions under non-ideal conditions. While PCI-SIG compliance can be obtained on a single lane implementation, real world scenarios require wider implementations under atypical operating conditions. Cadence’s PCIe 4.0 IP was tested against to additional stressed conditions, such as different combination of multi-lanes operations, “temperature drift” conditions, e.g., bring up the chip at room temperature and check the JTOL at high temperature. 

PCIe 4.0 Sub-system Stress Test Setup

Besides complying with electrical parameters and protocol requirements, real world systems have idiosyncrasies of their own. Cadence IP team also built a versatile “System test” setup in house to perform a system level stress test of its PCIe 4.0 sub-system. The Cadence PCIe 4.0 sub-system is connected to a large number of server and desktop motherboards. This set up is tested with 1000s of cycles of repeated stress under varying operating conditions. Stress tests include speed change from 2.5G all the way to 16G and down, link enable/disable, cold boot, warm boot, entering and exiting low power states, and BER test sweeping presets across different channels. Performing this level of stress test verifies that our IP will operate to spec robustly and reliably when presented with the occasional corner cases in the real world.

More Information

For the demonstration of Cadence PCIe4 PHY Receiver Test and Sub-system Stress Test, see the video:

• PCIe 4.0 Sub-system Stress Test
• PCIe 4.0 PHY Receiver JTOL Test

For more information on Cadence's PCIe IP offerings, see our PCI Express page.

For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website.

Related Posts

• Blog: PCIe Gen4: It’s Official, We’re Compliant
• Blog: PCIe 3.0 Still Shines While PCIe Keeps Evolving
• Blog: The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016

PCI-SIG DevCon 2019 APAC tour has come to Tokyo and Taipei this year. The focus is predominantly around the latest updates for PCIe Gen 5 which its version 1.0 specification was just released this year in May.  A series of presentations provided by PCI-SIG on the day 1 with comprehensive information covering all aspects of Gen 5 specification, including protocol, logical, electrical, compliance updates. On the day 2 (only in Taipei), several member companies shared their view on Testing, PCB analysis and Signal integrity. The exhibit is also another spotlight of this event where the member companies showcased their latest PCIe solutions.

Presentation Track (Taipei), Exhibit (Tokyo), Exhibit (Taipei) 

Cadence, as the market leading PCIe IP vendor, participated APAC tour this year with bringing in its latest PCIe IP solution offering (Gen 5/4) to the region as well as showcasing two live demo setups in the exhibit floor. One setup is the PCIe software development kit (SDK) while the other is the Interop/compliance/debug platform. Both come with the Cadence PCIe Gen 4 hardware setup and its corresponding software kit.

The SDK can be used for Device Driver Development, Firmware Development, and for pre-silicon emulation as well. It supports Xtensa and ARM processor with Linux OS and it also equip with Ethernet interface which can be used for remote debugging. It also supports PCIe stress tests for Speed change, link enable/disable, entry/exist for lower power states, …etc. 

Cadence PCIe 4.0 Software Development Kit

The “System Interop/Compliance/Debug platform” was set up to test with multiple endpoint and System platforms. This system come with integrated Cadence software for basic system debug without the need for analyzer to perform the analysis, such as LTSSM History, TS1/TS2 transmitted/received with time stamp, Link training phases, Capturing Packet errors details, Capturing PHY TX/RX internal state machine details, ...etc.

Cadence PCIe System Interop/Compliance/Debug Platform

The year 2019 is certainly a "fruitful year" for the PCIe as more Gen 4 products are now available in the market, Gen 5 v1.0 specification got officially ratified, and PCI-SIG's revealing of Gen 6 specification development. We were glad to be part of this APAC tour with the chance to further introduce Cadence’s complete and comprehensive PCIe IP solution.

See you all next year in APAC again!

More Information

For more information on Cadence's PCIe IP offerings, see our PCI Express page.

For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website.

Related Posts

• Blog: Did You “Stress Test” Yet? Essential Step to Ensure a Quality PCIe 4.0 Product
• Blog: PCIe Gen4: It’s Official, We’re Compliant
• Blog: PCIe 3.0 Still Shines While PCIe Keeps Evolving
• Blog: The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016

USB4 can simultaneously tunnel USB3, PCIe and DisplayPort native protocol traffic through a hierarchy of USB4 routers. The key to tunneling of these protocols is routing table programmed at each ingress adapter. An entry of a routing table maps an incoming HopID, called Input/Ingress HopID to a corresponding pair of Output/Egress Adapter and Egress/Output HopID.

The responsibility of programming routing tables lies with the Connection Manager. Connection Manager, having the complete view of the hierarchy of the routers, programs the routing tables at all relevant adapter ports. Accordingly, the USB3, PCIe and DisplayPort protocol tunneled packets are routed, and reach their respective intended destinations.

The diagrammatic representation below is an example of tunneling of USB3 protocol traffic from USB4 Host Router to USB4 Peripheral Device Router through a USB4 Hub Router. The path from USB3 Host to USB3 Device is depicted by routing tables indicated at A -> B -> C -> D, and the one from USB3 Device to USB3 Host by routing tables indicated at E -> F -> G -> H . Note that the Input HopID from and Output HopID to all three protocol adapters for USB3, PCIe and DisplayPort Aux traffic, are fixed as 8, and for DisplayPort Main Link traffic are fixed as 9.

Once the native protocol traffic come into the transport layer of a USB4 router, the transport layer of it does not know to which native protocol a tunneled packet belongs to. The only way a transport layer tunneled packet is routed through the hierarchy of the routers is using the HopID values and the information programmed in the routing tables.

The figure below shows an example of tunneling of all the three USB3, PCIe and DisplayPort protocol traffic together. The transport layer tunneled packets of each of these native protocols are transported simultaneously through the routers hierarchy.

 Cadence has a mature Verification IP solution for the verification of USB3, PCIe and DisplayPort tunneling. This solution also employs the industry proven VIPs of each of these native protocols for native USB3, PCIe and DisplayPort traffic.

Verifying lane adapter state machine in a router design is quite an involved task and needs verification from several aspects including that for its link training functionality.

The diagram below shows two lane adapters connected to each other and each going through the link training process. Each training sub-state transition is contingent on conditions for both transmission and reception of relevant ordered sets needed for a transition. Until conditions for both are satisfied an adapter cannot transition to the next training sub-state.

As deduced from the lane adapter state machine section of USB4 specification, the reception condition for the next training sub-state transition is less strict than that of the transmission condition. For ex., for LOCK1 to LOCK2 transition, the reception condition requires only two SLOS symbols in a row being detected, while the transmission condition requires at least four complete SLOS1 ordered sets to be sent.

From the above conditions in the specification, it is a possibility that a lane adapter A may detect the two SLOS or TS ordered sets, being sent by the lane adapter B on the other end, in the very beginning as soon as it starts transmitting its own SLOS or TS ordered sets. On the other hand, it is also a possibility that these SLOS or TS ordered sets are not yet detected by lane adapter A even when it has met the condition of sending minimum number of SLOS or TS ordered sets.

In such a case, lane adapter A, even though it has satisfied the transmission condition cannot transition to the next sub-state because the reception condition is not yet met. Hence lane adapter A must first wait for the required number of ordered sets to be detected by it before it can go to the next sub-state. But this wait cannot be endless as there are timeouts defined in the specification, after which the training process may be re-attempted.

This interlocked way of operation also ensures that state machine of a lane adapter does not go out of sync with that of the other lane adapter. Such type of scenarios can occur whenever lane adapter state machine transitions to the training state from other states.

Cadence has a mature Verification IP solution for the verification of various aspects of the logical layer of a USB4 router design, with verification capabilities provided to do a comprehensive verification of it.

I’m writing this on August 15. It is our Independence Day. A young Kashmiri Muslim told me in Srinagar a few months ago that this is the day on which everyone there tries to stay indoors. This is not because the people support Pakistan, but because they are most suspect on August 15. You are questioned, searched, and locked. If any of the readers have had a chance to view Sanjay Kak’s powerful documentary Jashn-e-Azadi (How We Celebrate Freedom) you’ll see how Sanjay, coming in to Srinagar for a visit around Independence Day, is struck by the fact that the only people present for the ceremony are the cops and members of the armed forces. (That’s Rave Out #1. For Jashn-e-Azadi.)

Last week’s announcement of the Indian Express-CNN/IBN poll, that an overwhelming majority of Kashmiris in the valley want azadi, also underlines the importance of a genuine rethinking on the question of independence rather than empty, nationalist sabre-rattling. (Anyway, that’s Rave Out #2. For Indian Express and CNN/IBN, as well as the good folk at CSDS who designed the poll.)

This is a good day for re-opening the pages of 13 December: A Reader, in which thirteen writers and journalists point out the injustice involved in the quick media-lynching of SAR Geelani and the denial of a fair trial to Afzal Guru. (This would be Rave Out #3, for the book, although wouldn’t it be great if the book weren’t needed?)

Rave Out © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

A couple of evenings ago, my cousin Debika and I were discussing how we’d react if we were told we had just a few months to live. She said she would try and do everything she liked in that time, and surround herself with her family. I said that I’d be inclined to save people I cared for the pain of watching me die—whatever that took. Ironically and unexpectedly, shortly after this conversation, we found ourselves watching François Ozon’s remarkable film Time to Leave.

The film begins with its protagonist, Romain, discovering that he is terminally ill with cancer, and deciding not to bother with treatment. He does not tell his friends or family of his condition. He is rude to his sister, and drives her to tears. He tells his lover, Sasha, that he does not love him, and drives him to move out of their house. This is a transparent lie, but though we see it, Sasha doesn’t. He confides to his grandmother—marvellously played by Jeanne Moreau—because she is like him, and “will die soon.” But even in this winding up, complications ensue.

Melvil Poupaud plays Romain, and is magnificent – understated, yet effortlessly expressive. But it is Ozon’s storytelling that makes this film memorable. It is spare, focussing only on the essential, and revealing its essence. There is not a frame out of place in this heartbreaking film that ends, like Romain, too soon and in great beauty.

Rave Out © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

Pablo Bartholomew’s beautiful photo-show “Outside In” opened in Manhattan a few evenings ago. The exhibition is being held at Bodhi Art in Chelsea. Black-and-white photographs from the seventies and the eighties—reflecting Bartholomew’s engagement with people and places in Delhi, Bombay, and Calcutta.

These are not the pictures that made Bartholomew famous. The undying image of the father brushing the dust from the face of the child he is burying—that was the iconic photograph from the Bhopal tragedy in 1984. It also won for Bartholomew, still in his twenties, the World Press Photo’s Picture of the Year Award.

The images in “Outside In” do not commemorate grim tragedies or celebrate well-publicised public events. Instead, they are documents that offer intimate recall of a period and a milieu. Please click here to look at these photographs.

People who share a context with the photographer will have their own private reading of the scenes. For me, they evoke days when happiness seemed only one chai and a Wills Navy Cut away. There is charm and candor in these scenes. And because the young believe they will live forever, there is nothing defensive or stuck-up or overly self-conscious about their faces and postures.

Even the language of the captions is true to this spirit: “Self-portrait after a trippy night…”; “Nona writing and Alok zonked out…”; “Hanging out with the Maharani Bagh gang….” The exhibition catalogue has a fine essay by Aveek Sen that has also been published in the latest issue of Biblio.

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I could barely recognize Ben Foster in 3:10 to Yuma, but I was blown away just the same by him as in his star making turn from Hostage. What makes Foster so special in Yuma?

Yuma contains two of Hollywood’s finest: Russell Crowe and Christian Bale. Bale is excellent, Crowe a little too relaxed to be cock-sure-dangerous. Both are unable to provide the powder-keg relationship that the movie demands.

Into this void steps Ben Foster. He plays Charlie Prince, sidekick to Crowe’s dangerous and celebrated outlaw Ben Wade. When Wade is captured, Prince is infuriated. He initiates an effort suffused with desperate passion to rescue his boss.

Playing Prince with a mildly effeminate gait, Foster quickly becomes the movie’s beating heart. What struck me in particular was that Foster was able to balance method acting with just plain good acting. He plays his character organically but isn’t above drawing attention with controlled staginess.

Gradually, Foster’s willingness to control a scene blend in with that of Prince’s. Is the character manipulating his circumstances in the movie or is it the actor playing a fine hand? Foster is so entertaining, the answer is immaterial.

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This new film is the latest remake of Devdas, but what is equally interesting is the fact that it is in conversation with films made in the West. Unlike Bhansali’s more spectacular version of the older story, Anurag Kashyap’s Dev.D is a genuine rewriting of Sarat Chandra’s novel. Kashyap doesn’t flinch from depicting the individual’s downward spiral, but he also gives women their own strength. He has set out to right a wrong—or, at least, tell a more realistic, even redemptive, story. If these characters have lost some of the affective depth of the original creations, they have also gained the hard edges of modern lives.

We don’t always feel the pain of Kashyap’s characters, but we are able to more readily recognize them. Take Chandramukhi, or Chanda, who is a school-girl humiliated by the MMS sex-scandal. Her father, protective and patriarchal, says that he has seen the tape and thinks she knew what she was doing. “How could you watch it?” the girl asks angrily. And then, “Did you get off on it?” When was the last time a father was asked such a question on the Hindi screen? With its frankness toward sex and masturbation, Dev.D takes a huge step toward honesty. In fact, more than the obvious tributes to Danny Boyle’s Trainspotting, or the over-extended psychedelic adventure on screen, in fact, as much as the moody style of film-making, the candour of such questions make Dev.D a film that is truly a part of world cinema.

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I loved Nina Paley’s brilliant animated film Sita Sings the Blues. If you’re reading this, stop right now—and watch the film here.

Paley has set the story of the Ramayana to the 1920s jazz vocals of Annette Hanshaw. The epic tale is interwoven with Paley’s account of her husband’s move to India from where he dumps her by e-mail. The Ramayana is presented with the tagline: “The Greatest Break-Up Story Ever Told.”

All of this should make us curious. But there are other reasons for admiring this film:

The film returns us to the message that is made clear by every village-performance of the Ramlila: the epics are for everyone. Also, there is no authoritative narration of an epic. This film is aided by three shadow puppets who, drawing upon memory and unabashedly incomplete knowledge, boldly go where only pundits and philosophers have gone before. The result is a rendition of the epic that is gloriously a part of the everyday.

This idea is taken even further. Paley says that the work came from a shared culture, and it is to a shared culture that it must return: she has put the film on Creative Commons—viewers are invited to distribute, copy, remix the film.

Of course, such art drives the purists and fundamentalists crazy. On the Channel 13 website, “Durgadevi” and “Shridhar” rant about the evil done to Hinduism. It is as if Paley had lit her tail (tale!) and set our houses on fire!

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Sample clues

5 across: The US president’s bird (3,5,3)

11 down: Group once known as the Quarrymen (7)

10 across: Cavalry sword (5)

19 across: Masonic ritual (5,6)

1 down: Pioneer of Ostpolitik (6)

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Sample clues

14 across: FDR’s baby (3,4)

1 down: A glitch in the Matrix? (4,2)

4 down: Slanted character (6)

5 down: New Year’s venue in New York (5,6)

16 down: Atmosphere of melancholy (5)

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Sample clues

6 across: Alejandro González Iñárritu’s breakthrough film (6,6)

19 across: Soft leather shoe (8)

7 down: Randroids, for example (12)

12 down: First American World Chess Champion (7)

17 down: Circle of influence (5)

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Sample clues

5 across: Robbie Robertson song about Richard Manuel (6,5)

2 down: F5 on a keyboard (7)

10 across: Lionel Richie hit (5)

3 down: ALTAIR, for example (5)

16 down: The problem with Florida 2000 (5)

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Sample clues

9 across: Van Morrison classic from Moondance (7)

6 down: Order beginning with ‘A’ (12)

6 across: Fatal weakness (8,4)

19 across: Rolling Stones classic (12)

4 down: Massacre tool (8)

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