Power and Ground rings are exposed rings of metal surrounding a die that supply power/ground to the die and create a low-impedance path for the current flow. These rings ensure stable power distribution and reduce noise. Allegro X Package Designer Plus has a utility called Power/Ground Ring Generator which lets you define and place one or more shapes in the form of a ring around a die.

 To run the PWR/GND Generator Wizard, go to Route > Power/Ground Ring Generator or type "pring wizard" in the APD command window to invoke the Wizard.

This Wizard lets you define and place one or more shapes in the form of a ring around a die. The Power/Ground Ring Wizard creates up to 12 rings (shapes) at a time. If you require more rings, you can run the Power/Ground Ring Wizard as many times as needed. This command displays a wizard in which you can specify:

• The number of rings to be generated
• The creation of the first ring as a die flag (Die flag is the boundary of the die like the power ring.)
  • If you create a die flag and the first ring is the same net as the flag, you can enter a negative distance to overlap the ring and the die flag.
• Multiple options for placement of the rings with respect to:
  • Origination point
  • Distance from the edge of the die
  • Distance from the nearest die pin on each die side
• The reference designator of the die with which the rings will be used
• The distance between rings
• The width of each ring
• The corner types on each ring (arc, chamfer, and right-angle)
• An assigned net name for each ring
• A label for each ring

The rings are basic in nature. For other shape geometries or split rings, choose Shape > Polygon or Shape > Compose/Decompose Shape from the menu in the design window.

Depending on the options selected, the Power/Ground Ring Wizard UI changes, representing how the rings will be created. Verify the Wizard settings to ensure that the rings are created as intended.

1. When the Power/Ground Ring Wizard appears, set the number of rings to 2, accept the other defaults, and click Next. You can set Create first ring as die flag to create a basic die flag.

         2. Define Ring 1 and the net associated with it.

              a) Browse and choose Vss in the Net Names dialog box.

            b) Click OK.

            c) Specify the label as VSS.

            d) Click Next.

             The first ring should appear in your design. It is associated with the proper net; in this case, VSS.

2. For the second ring, choose the net as Vdd and specify the label as VDD.
3. Click Next.
4. Click Finish in the Result Verification screen to complete the process.

The completed rings appear as shown below.

Now, when you click on Power and Ground Die Pin and add wirebonds, you will see that the wirebonds are placed directly on the Power and Ground rings.

The Cadence Palladium Emulation Platform is a hardware system that implements the design, accelerating its execution and verification. Itoffers the highest performance and fastest bring-up times for pre-silicon validation of billion-gate designs, using a custom processor built by Cadence.

This Palladium Introduction course is based on the Palladium 23.03 ISR4 version and covers the following modules:

• Introduction
• Palladium flow
• Running a design on the Palladium system

This course starts with an “Introduction” module that explains Palladium and other verification platforms to show its place in the big picture. It also compares Palladium with Protium and simulation and discusses its usage and limitations.

The “Palladium Flow” module includes two stages at a high level, which are Compile and Run. Then, it covers these stages in detail. First, it covers the ICE compile flow and IXCOM compile flow steps in detail. Then it explains Run, which is common for both ICE and IXCOM modes.

The third module, “Running Design on the Palladium System,” covers all the items required for running your design on the Palladium system, including:

• Software stack requirements
• Basic concepts required to understand the flow
• Compute machine requirements

In addition, this course contains labs for both the ICE and IXCOM flows with detailed steps to exercise the features provided by the Palladium system. The lab explains a practical example of multiple counters and exercising their signals for force, monitor, and deposit features, along with frequency calculation using a real-time clock. The course is available on the Cadence support page:

There is also a Digital Badge available. You will find the Badge exam opportunity when you enroll in the Online training or after you have taken the training as "live" training.

For questions and inquiries, or issues with registration, reach out to us at Cadence Training. Want to stay up to date on webinars and courses? Subscribe to Cadence Training emails. To view our complete training offerings, visit the Cadence Training website.

Related Training Bytes

• Palladium: What Are Verification Platforms
• Palladium: What Is Processor Based Emulation
• Palladium: Comparing Emulation (Z2) and Prototyping (X2)
• Palladium: What Are ICE and IXCOM Compile Flow
• Palladium: How to Process a Design to Run on Palladium
• Palladium: XCOM Compile Flow (TB+RTL to Palladium Database)
• Palladium: ICE Compile Flow (RTL to Palladium Database)
• Palladium: Legacy ICE Compile Flow
• Palladium: Cadence Software Releases for Palladium and Protium Flow
• Palladium: Setting of PATHs for Using Palladium
• Palladium: Z2 Hardware Structure (Blade and Boards)
• Palladium: What Is Sourceless and Loadless nets
• Palladium: Design Clocks
• Palladium: Step Count and Step Clock
• Palladium: Steps for Running the Design on Palladium Z2

Related Courses

• Verilog Language and Application Training
• SystemVerilog for Design and Verification
• Xcelium Simulator

Related Blogs

• Training Insights – A New Free Online Course on the Protium System for Beginner and Advanced Users
• It’s the Digital Era; Why Not Showcase Your Brand Through a Digital Badge!
• Training Insights - Free Online Courses on Cadence Learning and Support Portal

Cadence PCIe/CXL VIP support for Partial Header Encryption in Integrity and Data Encryption.(read more)

The application of real-time data processing or responsiveness is crucial, such as in high-performance computing, data centers, or applications requiring low-latency data transfers. It enables efficient use of PCIe bandwidth and resources by intelligently managing memory write operations based on system dynamics and workload priorities. By effectively leveraging Deferrable Memory Write [DMWr], Devices can achieve optimized performance and responsiveness, aligning with the evolving demands of modern computing applications.

What Is Deferrable Memory Write?

Deferrable Memory Write (DMWr) ECN introduced this new memory transaction type, which was later officially incorporated in PCIe 5.0 to CXL2.0. This enhanced type of memory transaction is Deferrable Memory Write [DMWr], which flows as another type of existing Read/Write memory transaction; the major difference of this Deferrable Memory Write, where the Requester attempts to write to a given location in Memory Space using the non-posted DMWr TLP Type, it Postponing their completion of memory write transactions to improve overall system efficiency and performance, those memory write operation can be delay or deferred until other priority task complete.

The Deferrable Memory Write (DMWr) requires the Completer to return an acknowledgment to the Requester and provides a mechanism for the recipient to defer (temporarily refuse to service) the Request.

DMWr provides a mechanism for Endpoints and hosts to choose to carry out or defer incoming DMWr Requests. This mechanism can be used by Endpoints and Hosts to simplify the design of flow control, reduce latency, and improve throughput. The Deferrable Memory writes TLP format in Figure A.

(Fig A) Deferrable Memory writes TLP format.

Example Scenario

Here's how the DMWr works with a simplified example: Imagine a system with an endpoint device (Device A) and a host CPU (Device B). Device B wants to write data to Device A's memory, but due to varying reasons such as system bus congestion or prioritization of other transactions, Device A can defer the completion of the memory write request. Just follow these steps:

1. Initiation of Memory Write: Device B initiates a memory write transaction to Device A. This involves sending the memory write request along with the data payload over the PCIe physical layer link.
2. Acknowledgment and Deferral: Upon receiving the memory write request, Device A acknowledges the transaction but may decide to defer its completion. Device A sends an acknowledgment (ACK) back to Device B, indicating it has received the data and intends to complete the write operation but not immediately.
3. Deferred Completion: Device A defers the completion of the memory write operation to a later, more opportune time. This deferral allows Device A to prioritize other transactions or optimize the use of system resources, such as memory bandwidth or processor availability.
4. Completion and Response: At a later point, Device A completes the deferred memory write operation and sends a completion indication back to Device B. This completion typically includes any status updates or additional information related to the transaction.

Usage or Importance of DMWr

Deferrable Memory Write usage provides the improvement in the following aspects:

• Reduced Latency: By deferring less critical memory write operations, more critical transactions can be processed with lower latency, improving overall system responsiveness.
• Improved Efficiency: Optimizes the utilization of system resources such as memory bandwidth and CPU cycles, enhancing the efficiency of data transfers within the PCIe architecture.
• Enhanced Performance: Allows devices to manage and prioritize transactions dynamically, potentially increasing overall system throughput and reducing contention.

Challenges in the Implementation of DMWr Transactions

The implementation of deferrable memory writes (DMWr) introduces several advancements and challenges in terms of usage and verification:

1. Timing and Synchronization: DMWr allows transactions to be deferred, complicating timing requirements or completing them within acceptable timing windows to avoid protocol violations. Ensuring proper synchronization between devices becomes critical to prevent data loss or corruption.
2. Protocol Compliance: Verification must ensure compliance with ECN PCIe 6.0 and CXL specifications regarding when and how DMWr transactions can be initiated and completed.
3. Performance Optimization: While DMWr can improve overall system performance by reducing latency, verifying its impact on system performance and ensuring it meets expected benchmarks is crucial.
4. Error Handling: Handling errors related to deferred transactions adds complexity. Verifying error detection and recovery mechanisms under various scenarios (e.g., timeout during deferral) is essential.

Verification Challenges of DMWr Transactions

The challenges to verifying the DMWr transaction consist of all checks with respect to Function, Timing, Protocol compliance, improvement, Error scenario, and security usage on purpose, as well as Data integrity at the PCIe and CXL.

1. Functional Verification: Verifying the correct implementation of DMWr at both ends of the PCIe link (transmitter and receiver) to ensure proper functionality and adherence to specifications.
2. Timing Verification: Validating timing constraints associated with deferring writes and ensuring transactions are completed within specified windows without violating protocol rules.
3. Protocol Compliance Verification: Checking that DMWr transactions adhere to PCIe and CXL protocol rules, including ordering rules and any restrictions on deferral based on the transaction type.
4. Performance Verification: Assessing the impact of DMWr on overall system performance, including latency reduction and bandwidth utilization, through simulation and testing.
5. Error Scenario Verification: Creating and testing scenarios to verify error handling mechanisms related to DMWr, such as timeouts, retries, and recovery procedures.
6. Security Considerations: Assessing potential security vulnerabilities related to DMWr, such as data integrity risks during deferred transactions or exposure to timing-based attacks.

Major verification challenges and approaches are timing and synchronization verification in the context of implementing deferrable memory writes (DMWr), which is crucial due to the inherent complexities introduced by deferred transactions. Here are the key issues and approaches to address them:

Timing and Synchronization Issues

1. Transaction Completion Timing:
   • Issue: Ensuring deferred transactions are completed within the specified time window without violating protocol timing constraints.
   • Approach: Design an internal timer and checker to model worst-case scenarios where transactions are deferred and verify that they are complete within allowable latency limits. This involves simulating various traffic loads and conditions to assess timing under different scenarios.
2. Ordering and Dependencies:
   • Issue: Verifying that transactions deferred using DMWr maintain the correct ordering and dependencies relative to non-deferred transactions.
   • Approach: Implement test scenarios that include mixed traffic of DMWr and non-DMWr transactions. Verify through simulation or emulation that dependencies and ordering requirements are correctly maintained across the PCIe link.
3. Interrupt Handling and Response Times:
   • Issue: Verify the handling of interrupts and ensure timely responses from devices involved in DMWr transactions.
   • Approach: Implement test cases that simulate interrupt generation during DMWr transactions. Measure and verify the response times to interrupts to ensure they meet system latency requirements.

In conclusion, while deferrable memory writes in PCIe and CXL offer significant performance benefits, their implementation and verification present several challenges related to timing, protocol compliance, performance optimization, and error handling. Addressing these challenges requires rigorous testing and testbench of traffic, advanced verification methodologies, and a thorough understanding of PCIe specifications and also the motivation behind introducing this Deferrable Write is effectively used in the CXL further. Outcomes of Deferrable Memory Write verify that the performance benefits of DMWr (reduced latency, improved throughput) are achieved without compromising timing integrity or violating protocol specifications.

In summary, PCIe and CXL are complex protocols with many verification challenges. You must understand many new Spec changes and consider the robust verification plan for the new features and backward compatible tests impacted by new features. Cadence's PCIe 6.0 Verification IP is fully compliant with the latest PCIe Express 6.0 specifications and provides an effective and efficient way to verify the components interfacing with the PCIe 6.0 interface. Cadence VIP for PCIe 6.0 provides exhaustive verification of PCIe-based IP and SoCs, and we are working with Early Adopter customers to speed up every verification stage.

More Information

• For more info on how Cadence PCIe Verification IP and TripleCheck VIP enable users to confidently verify PCIe 6.0, see our VIP for PCI Express, VIP for Compute Express Link, and TripleCheck for PCI Express
• See the PCI-SIG website for more details on PCIe in general and the different PCI standards.

The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2024.1 release is now available for download at Cadence Downloads . For the list of CCRs fixed in this release, see the README.txt file in the installation hierarchy. SIGRITY/SYSANLS 2024.1 Here is a list of some of the key updates in the SIGRITY/SYSANLS 2024.1 release: For more details about these and all the other new and enhanced features introduced in this release , refer to the following document: Sigrity Release Overview and Common Tools What's New . Supported Platforms and Operating Systems Platform and Architecture X86_64 (lnx86) Windows (64 bit) Development OS RHEL 8.4 Windows Server 2022 Supported OS RHEL 8.4 and above RHEL 9 SLES 15 (SP3 and above) Windows 10 Windows 11 Windows Server 2019 Windows Server 2022 Systems Analysis 2024.1 Clarity 3D Solver Clarity 3D Layout Structure Optimization Workflow : A new workflow, Clarity 3D Layout Structure Optimization Workflow, has been added to Clarity 3D Layout. This workflow integrates Allegro PCB Designer with Clarity 3D Layout for high-speed structure optimization. Component Geometry Model Editor : The new Clarity 3D Layout editor lets you set up ports, solder bumps/balls/extrusions, and two-terminal and multi-terminal circuits using a single GUI. Coaxial Open Port Option Added to Port Setup Wizard : The Coaxial Open Port option lets you create ports for each target net pin and reference net pin in Clarity 3D Layout. The nearby reference net pins are then used as a reference for each target net pin, reducing the number of ports needed. In addition, the ports of unused reference net pins are shorted to the ground. Parametric Import Option Added : Two new options, Parametric Import and Default Import , have been added to the Tools – Launch Clarity3DWorkbench menu. The Parametric Import option lets you import the design along with its parameters into Clarity 3D Workbench. The Default Import option lets you ignore the parameters when importing the design into Clarity 3D Workbench. Component Library Added to Generate 3D Components : Clarity 3D Workbench now includes a new component library that lets you use predefined 3D component templates or add existing 3D components to create 3D designs and simulation models. AI-Powered Content Search Capability : Clarity 3D Workbench and Clarity 3D Transient Solver now support an AI-powered capability for searching the content and displaying relevant information. Expression Parser to Handle Undefined Parameters : Clarity 3D Workbench and Clarity 3D Transient Solver support writing expressions or equations containing undefined parameters in the Property window to describe a simulation variable. The improved expression parser automatically detects any undefined parameter in an expression and prompts users to specify their values. This capability lets you define a model or a simulation variable as a function instead of specifying static values. For detailed information, refer to Clarity 3D Layout User Guide and Clarity 3D Workbench User Guide on the Cadence Support portal. Clarity 3D Transient Solver Mesh Processing Improved to Simulate Large Use Cases : Clarity 3D Transient Solver leverages a new meshing algorithm that enhances overall mesh processing, specifically for large designs and use cases. The new algorithm dramatically improves the mesh quality, minimum mesh size, number of mesh key points, total mesh number, and memory usage. Advanced Material Processing Engine : The material processing capability has been enhanced to handle thin outer metal, which previously resulted in open and short issues in some designs. In addition, the material processing engine offers improved mode extraction for particular use cases, including waveguide and coaxial designs. Characteristic Impedance Calculation Improved : The solver engine now uses a new analytical calculation method to calculate the characteristic impedance of coaxial designs with improved accuracy. For detailed information, refer to Clarity 3D Transient Solver User Guide on the Cadence Support portal. Celsius Studio Celsius Interchange Model Introduced : Celsius Studio now supports Celsius Interchange Model generation, which is a 3D model derived from detailed physical designs for multi-physics and multi-scale analysis. This Celsius Interchange Model file ( .cim ) serves as a design information carrier across Celsius Studio tools, enabling a variety of simulation and analysis tasks . Celsius 3DIC Thermal Workflow Improvements : The Thermal Simulation workflows in Celsius 3DIC have been significantly enhanced. Key improvements include: Advanced Power Setup with Transient Power Function and Multi Mode options Enhanced GUI for the Mesh Control and Simulation Control tabs Improved meshing capabilities Celsius Interchange Model ( .cim ) generation Material library support for block and connections Import of Heat Transfer Coefficients (HTCs) from a CFD file Bump creation through the Bump Array Wizard Layer Stackup CSV file generation Celsius 3DIC Warpage and Stress Workflow Enhancements : The Warpage and Stress workflow in Celsius 3DIC has undergone significant improvements, such as: Improved multi-stage warpage simulation flow for 3DIC packaging process Enhanced GUI for the Mesh Control , Simulation Control , and Stress Boundary Conditions tabs Support for large deformations and temperature profiles Bump creation through the Bump Array Wizard New constraint types Enhanced meshing capabilities Geometric Nonlinearity Support in Warpage and Stress Analysis : Large deformation analysis is now supported in warpage and stress studies. This study uses the Total Lagrangian approach to model geometric nonlinearities in simulation, which allows accurate prediction of final deformations. Thermal Network Extraction and Simulation : In the solid extraction flow in Celsius 3D Workbench, you can now import area-based power map files to create terminals. For designs with multiple blocks, this capability allows automatic terminal creation, eliminating the need to manually create and set up 2D sheets individually. Additionally, thermal throttling feature is now supported in Celsius Thermal Network. This makes it ideal for preliminary analyses or when a quick estimation is required. It runs significantly faster than 3D models, allowing for quicker iterations and more efficient decision-making. For detailed information, refer to the Celsius 3DIC User Guide , Celsius Layout User Guide and Celsius 3D Workbench User Guide on the Cadence Support portal. Sigrity 2024.1 Layout Workbench Improved Graphical User Interface : A new option, Use Improved User Interface , has been added in the Themes page of the Options dialog box in the Layout Workbench GUI. In the new GUI, the toolbar icons and menu options have been enhanced and rearranged. For detailed information, refer to Layout Workbench User Guide on the Cadence Support portal. Broadband SPICE Python Script Integration with Command Line for Simulation Tasks : Broadband SPICE lets you run Python scripts directly from the command line for performing simulation and analysis. The new -py and *.py options make it easier to integrate Python scripts with the command-line operations. This update streamlines the process of automating and customizing simulations from the command line, which makes your simulation tasks faster and easier. For detailed information, refer to Broadband SPICE User Guide on the Cadence Support portal. Celsius PowerDC Block Power Assignment (BPA) File Format Support : PowerDC now supports the BPA file format. Similar to the Pin Location (PLOC) file, the BPA file is a current assignment file that defines the total current of a power grid cell, which is then equally distributed across the power pins within the cell. This provides better control over the power distribution. Ability to Run Multiple IR Drop Cases Sequentially : You can now select multiple result sinks from the Current-Limited IR Drop flow and run IR Drop analysis for them sequentially. PowerDC automatically runs the simulations in sequence after you select multiple result sinks. This saves time by automating the process. Enhanced Support for Mixed Conversion Devices : PowerDC now supports mixing different conversion devices, such as switching regulators and linear regulators within a single DC-DC/LDO instance. This enhancement offers added flexibility by letting you configure each instance in your design according to your specific needs. For detailed information, refer to PowerDC User Guide on the Cadence Support portal. PowerSI Monte Carlo Method Added : A new option, Monte Carlo Method, has been added in the Optimality dialog box. This option lets you create multiple random samples to depict variations in the input parameters and assess the output. Channel Check Optimization Added : The S-Parameter Assessment workflow in PowerSI now supports Channel Check Optimization . It uses the AI-driven Multidisciplinary Analysis and Optimization (MDAO) technology that lets you optimize your design quickly and efficiently with no accuracy loss. For detailed information, refer to PowerSI User Guide on the Cadence Support portal. SPEEDEM Multi-threaded Matrix Solver Support Added : The Enable Multi-threaded Matrix Solver check box has been added that lets you accelerate the simulation speed for high-performance computing. This check box provides two options, Automatic and Always, to include the -lhpc4 or -lhpc5 parameter, respectively, in the SPEEDEM Simulator (SPDSIM) before running the simulation. For detailed information, refer to the SPEEDEM User Guide on the Cadence Support portal. XtractIM Options to Skip or Calculate Special DC-R Simulation Results : The Skip DC_R of Each Path and Only DC_R of Each Path options have been added to the Setup menu. Skip DC_R of Each Path : This option lets you skip the calculation of the DC-R result during the simulation. Other results, such as SPICE T-model , RL_C of Each Path , Coupling of Each Path , etc., are still calculated. Only DC_R of Each Path : This option lets you calculate the DC-R result only during the simulation. Other results, such as SPICE T-model , RL_C of Each Path , Coupling of Each Path , etc., are not calculated. Color Assignment for Pin Matching : The MCP Auto Connection window includes the Display Color Editor , which lets you assign a color for pin matching. It helps you easily identify the matching pins in the left and right sections of the MCP Auto Connection window . Ability to Save Simulations Individually : The Save each simulation individually check box has been added to the Tools - Options - Edit Options - Simulation (Basic) - General form. Select this check box and run the simulation to generate a simulation results folder containing files and logs with a timestamp for each simulation. Reuse of SPD File Settings : The XtractIM setup check box lets you import an existing package setup to reuse the configurations and settings from one .spd file to another. For detailed information, refer to XtractIM User Guide on the Cadence Support portal. Documentation Enhancements Cloud-Based Help System Upgraded The cloud-based help system, Doc Assistant, has been upgraded to version 24.10, which contains several new features and enhancements over the previous 2.03 version. Sigrity Release Team Please send your questions and feedback to sigrity_rmt@cadence.com .

Celebrated for their unparalleled engineering expertise and pioneering mindset, McLaren stands at the forefront of innovation. Theirs is a story of engineering excellence, a symphony of speed driven by the relentless pursuit of aerodynamic perfection. In 2022, Cadence was named an Official Technology Partner of the McLaren Formula 1 Team. The multi-year partnership between McLaren and Cadence has helped redefine the boundaries of what’s possible in Formula 1 aerodynamics. Shaving off a fraction of a second per lap can make all the difference in a podium finish, and track conditions bring layers of complexity to the design process. That’s where Cadence steps in with Fidelity CFD Software. The Cadence Fidelity CFD software is a comprehensive suite of computational fluid dynamics (CFD) solutions. Access to this solution allows the McLaren F1 team to accelerate their CFD workflow, enabling them to assess designs faster and more precisely. It also allows them to investigate airflows and tackle design projects that require advanced compute power and precision. With Fidelity Flow’s solver capabilities and Python-driven automation, Cadence’s CFD software aids the advancement of aerodynamic simulations that go into McLaren’s F1 cars. With a customized, high-quality, multi-block meshing strategy and optimized workflow, Fidelity CFD makes design exploration more automated, thereby helping establish a strong foundation for McLaren’s future success on the track. Lando Norris, F1 driver for McLaren, said, “As a driver, I saw the impact of every decision made in the design room in every simulation run. The work on aerodynamics directly translates to the confidence I have on track, the grip in every turn, and the speed on every straight. This partnership, this technology, is what will give us the edge. It's not just about battling opponents; it's about mastering the airflow around the car in every driving condition on every track.” If you’re interested in learning more about the importance of CFD in McLaren’s racing success, be sure to attend our upcoming webinar, “CFD and Experimental Aerodynamics in McLaren F1 Engineering.” Christian Schramm, McLaren’s director of advanced projects, and Cadence’s Benjamin Leroy will be the main speakers for the event. Register today to secure your spot! For more insights on the Formula 1 car design process, take a look at the case study, “ McLaren Formula 1 Car Aerodynamics Simulation with Cadence Fidelity CFD Software .” Learn more about how McLaren and Cadence are engineering success . “Designed with Cadence” is a series of videos that showcases creative products and technologies that are accelerating industry innovation using Cadence tools and solutions. For more Designed with Cadence videos, check out the Cadence website and YouTube channel .

Each November, we are reminded of the bravery and dedication of those who have served our country. At Cadence, we thank our Veteran employees for their patriotism by reaffirming our commitment to honoring their sacrifices and recognizing their contributions to our business success. Our diverse and inclusive culture is strengthened by the unique perspective of our Veteran employees, and we are proud to support the Veterans Inclusion Group as a space for community members and their allies to connect. In celebration of Veterans Day, we were excited to catch up with Johnathan Edmonds, Veterans Inclusion Group Lead and Design Engineering Director, for a heartfelt chat on his journey through military service to leadership within Cadence. Throughout the conversation, he shared the importance of creating space for Veterans, the skills they offer, and his aspirations for what the Veterans Inclusion Group will achieve in the years ahead. Oh yeah, and he flies planes, too! Join us as we dive into what makes this holiday special for so many across the nation and how we can respectfully commemorate it together. Johnathan, you’re a retired Air Force Reservist, pilot, and now a Design Engineering Director. Can you tell us about your journey from the military to your current role at Cadence? I started my military and electronics journey in the Navy. I enlisted at 18 and served for six years as an aviation electronics technician. During this time, I was able to learn about and repair electronics on planes. This set me up for success, and when I was honorably discharged, I attended Virginia Tech to study computer engineering. Once I graduated, I continued my career as an engineer, but I still wanted to be a military pilot. From my past experience, I knew the reserves were an option where I could learn to fly and still have a civilian career. Not only was I lucky enough to get selected to go to pilot training, but after I returned from flight school, my luck grew, and I was hired at Cadence. Cadence has supported me throughout my military career, which has been a great benefit, as many companies don’t support reservists. The best thing about serving and being employed at Cadence is how I could blend my skill sets to further the Air Force’s mission and achieve great things in engineering. As the first lead of Cadence’s Veterans Inclusion Group, you played an integral part in growing our culture and building community at the company since launching the group four years ago. What inspired you to take on the role of Inclusion Group Lead? I was inspired by three things: camaraderie, service, and outreach. I wanted to see if we could achieve a similar sense of community through the Veterans Inclusion Group as we had during our service life. I also wanted to see how we could better serve our Veterans here at Cadence. I wanted to explore any benefits that could be expanded, roles that could be developed by Vets, and, lastly, I wanted to serve a broader community. COVID-19 put a damper on some of the community support, but we are getting back on track with Veteran employment programs and volunteer efforts like Carry the Load and Gold Star Families. Why is it important to have this space dedicated to Veteran employees? There are many reasons! Networking, for one, creates a stronger, more unified Cadence culture. Two, Vets face a variety of issues not generally understood by those who have not served, such as PTSD, where to get help for disabilities, how to get an old medical record, etc. As I mentioned, I’m also passionate about connecting Veterans with employment and job opportunities. It is so nice to work for a company that actively recruits Vets. We have our own “language,” if you will, so it’s nice to have a space to talk in the language that we are familiar with. What have been some of your favorite moments leading this group over the past few years? Are there any “wins” that you would like to recognize? We have a lot of wins. Events held during COVID-19 and getting past COVID-19, donating to worthwhile causes, and hosting guest speakers are all fantastic milestones and accomplishments. That said, the biggest win is the hiring of new Veteran employees. Mark Murphy, Corporate VP of Sales Operations, and I have both welcomed Vets to our team during this time, and it is such a joy to watch what someone can do when given the opportunity to succeed in the right environment. As you are set to transition out of the lead role next year, what do you hope to see the Veterans Inclusion Group accomplish next? My hope is that the Veterans Inclusion Group partners with other companies, expanding our reach externally and exploring new opportunities to engage Veterans outside of Cadence. Johnathan (left) speaks on an inclusion group panel, along with David Sallard (center), lead of Cadence's Black Inclusion Group and Sr. Principal Application Engineer; Christina Jamerson (on screen), lead of Cadence's Abilities Inclusion Group and Demand Generation Director; and Dianne Rambke (right), lead of Cadence's Latinx Inclusion Group and Marketing Communications Director. What are the important ways that people can signal inclusion and respectfully honor Veterans at work? What are the most meaningful or impactful actions employees everywhere can take to support Veteran coworkers? I think there is one answer to both questions. I recommend that people engage with their companies’ employee resource groups (ERGs) and have conversations with them. Opening up the lines of communication will lead to new paths in their journeys. What are you looking forward to in 2025, both personally and professionally? In 2025, professionally, I am looking forward to taking mixed-signal systems and verification to another level by including emulation, automatic model generation, and seeing which boundaries we can push in our SerDes and Chiplets products. Personally, I am looking forward to making my SXS street legal so I can drive places without getting a ticket, seeing my children participate in sports, church, and school, and taking my wife on vacation to Europe or somewhere else we can unplug. Learn more about Cadence’s Inclusion Groups, diverse culture, and commitment to belonging.

Peripheral Component Interconnect Express (PCIe) is a high-speed interface standard widely used for connecting processors, memory, and peripherals. With the increasing reliance on PCIe to handle sensitive data and critical high-speed data transfer, ensuring data integrity and encryption during verification is the most essential goal. As we know, in the field of verification, randomization is a key technique that drives robust PCIe verification. It introduces unpredictability to simulate real-world conditions and uncover hidden bugs from the design. This blog examines the significance of randomization in PCIe IDE verification, focusing on how it ensures data integrity and encryption reliability, while also highlighting the unique challenges it presents. For more relevant details and understanding on PCIe IDE you can refer to Introducing PCIe's Integrity and Data Encryption Feature . The Importance of Data Integrity and Data Encryption in PCIe Devices Data Integrity : Ensures that the transmitted data arrives unchanged from source to destination. Even minor corruption in data packets can compromise system reliability, making integrity a critical aspect of PCIe verification. Data Encryption : Protects sensitive data from unauthorized access during transmission. Encryption in PCIe follows a standard to secure information while operating at high speeds. Maintaining both data integrity and data encryption at PCIe’s high-speed data transfer rate of 64GT/s in PCIe 6.0 and 128GT/s in PCIe 7.0 is essential for all end point devices. However, validating these mechanisms requires comprehensive testing and verification methodologies, which is where randomization plays a very crucial role. You can refer to Why IDE Security Technology for PCIe and CXL? for more details on this. Randomization in PCIe Verification Randomization refers to the generation of test scenarios with unpredictable inputs and conditions to expose corner cases. In PCIe verification, this technique helps us to ensure that all possible behaviors are tested, including rare or unexpected situations that could cause data corruption or encryption failures that may cause serious hindrances later. So, for PCIe IDE verification, we are considering the randomization that helps us verify behavior more efficiently. Randomization for Data Integrity Verification Here are some approaches of randomized verifications that mimic real-world traffic conditions, uncovering subtle integrity issues that might not surface in normal verification methods. 1. Randomized Packet Injection: This technique randomized data packets and injected into the communication stream between devices. Here we Inject random, malformed, or out-of-sequence packets into the PCIe link and mix valid and invalid IDE-encrypted packets to check the system’s ability to detect and reject unauthorized or invalid packets. Checking if encryption/decryption occurs correctly across packets. On verifying, we check if the system logs proper errors or alerts when encountering invalid packets. It ensures coverage of different data paths and robust protocol check. This technique helps assess the resilience of the IDE feature in PCIe in below terms: (i) Data corruption: Detecting if the system can maintain data integrity. (ii) Encryption failures: Testing the robustness of the encryption under random data injection. (iii) Packet ordering errors: Ensuring reordering does not affect data delivery. 2. Random Errors and Fault Injection: It involves simulating random bit flips, PCRC errors, or protocol violations to help validate the robustness of error detection and correction mechanisms of PCIe. These techniques help assess how well the PCIe IDE implementation: (i) Detects and responds to unexpected errors. (ii) Maintains secure communication under stress. (iii) Follows the PCIe error recovery and reporting mechanisms (AER – Advanced Error Reporting). (iv) Ensures encryption and decryption states stay synchronized across endpoints. 3. Traffic Pattern Randomization: Randomizing the sequence, size, and timing of data packets helps test how the device maintains data integrity under heavy, unpredictable traffic loads. Randomization for Data Encryption Verification Encryption adds complexity to verification, as encrypted data streams are not readable for traditional checks. Randomization becomes essential to test how encryption behaves under different scenarios. Randomization in data encryption verification ensures that vulnerabilities, such as key reuse or predictable patterns, are identified and mitigated. 1. Random Encryption Keys and Payloads: Randomly varying keys and payloads help validate the correctness of encryption without hardcoding assumptions. This ensures that encryption logic behaves correctly across all possible inputs. 2. Randomized Initialization Vectors (IVs): Many encryption protocols require a unique IV for each transaction. Randomized IVs ensure that encryption does not repeat patterns. To understand the IDE Key management flow, we can follow the below diagram that illustrates a detailed example key programming flow using the IDE_KM protocol. Figure 1: IDE_KM Example As Figure 1 shows, the functionality of the IDE_KM protocol involves Start of IDE_KM Session, Device Capability Discovery, Key Request from the Host, Key Programming to PCIe Device, and Key Acknowledgment. First, the Host starts the IDE_KM session by detecting the presence of the PCIe devices; if the device supports the IDE protocol, the system continues with the key programming process. Then a query occurs to discover the device’s encryption capabilities; it ensures whether the device supports dynamic key updates or static keys. Then the host sends a request to the Key Management Entity to obtain a key suitable for the devices. Once the key is obtained, the host programs the key into the IDE Controller on the PCIe endpoint. Both the host and the device now share the same key to encrypt and authenticate traffic. The device acknowledges that it has received and successfully installed the encryption key and the acknowledgment message is sent back to the host. Once both the host and the PCIe endpoint are configured with the key, a secure communication channel is established. From this point, all data transmitted over the PCIe link is encrypted to maintain confidentiality and integrity. IDE_KM plays a crucial role in distributing keys in a secure manner and maintaining encryption and integrity for PCIe transactions. This key programming flow ensures that a secure communication channel is established between the host and the PCIe device. Hence, the Randomized key approach ensures that the encryption does not repeat patterns. 3. Randomization PHE: Partial Header Encryption (PHE) is an additional mechanism added to Integrity and Data Encryption (IDE) in PCIe 6.0. PHE validation using a variety of traffic; incorporating randomization in APIs provided for validating PHE feature can add more robust Encryption to the data. Partial Header Encryption in Integrity and Data Encryption for PCIe has more detailed information on this. Figure 2: High-Level Flow for Partial Header Encryption 4. Randomization on IDE Address Association Register values: IDE Address Association Register 1/2/3 are supposed to be configured considering the memory address range of IDE partner ports. The fields of IDE address registers are split multiple values such as Memory Base Lower, Memory Limit Lower, Memory Base Upper, and Memory Limit Upper. IDE implementation can have multiple register blocks considering addresses with 32 or 64, different registers sizes, 0-255 selective streams, 0-15 address blocks, etc. This Randomization verification can help verify all the corner cases. Please refer to Figure 2. Figure 3: IDE Address Association Register 5. Random Faults During Encryption: Injecting random faults (e.g., dropped packets or timing mismatches) ensures the system can handle disruptions and prevent data leakage. Challenges of IDE Randomization and its Solution Randomization introduces a vast number of scenarios, making it computationally intensive to simulate every possibility. Constrained randomization limits random inputs to valid ranges while still covering edge cases. Again, using coverage-driven verification to ensure critical scenarios are tested without excessive redundancy. Verifying encrypted data with random inputs increases complexity. Encryption masks data, making it hard to verify outputs without compromising security. Here we can implement various IDE checks on the IDE callback to analyze encrypted traffic without decrypting it. Randomization can trigger unexpected failures, which are often difficult to reproduce. By using seed-based randomization, a specific seed generates a repeatable random sequence. This helps in reproducing and analyzing the behavior more precisely. Conclusion Randomization is a powerful technique in PCIe verification, ensuring robust validation of both data integrity and data encryption. It helps us to uncover subtle bugs and edge cases that a non-randomized testing might miss. In Cadence PCIe VIP, we support full-fledged IDE Verification with rigorous randomized verification that ensures data integrity. Robust and reliable encryption mechanisms ensure secure and efficient data communication. However, randomization also brings various challenges, and to overcome them we adopt a combination of constrained randomization, seed-based testing, and coverage-driven verification. As PCIe continues to evolve with higher speeds and focuses on high security demands, our Cadence PCIe VIP ensures it is in line with industry demand and verify high-performance systems that safeguard data in real-world environments with excellence. For more information, you can refer to Verification of Integrity and Data Encryption(IDE) for PCIe Devices and Industry's First Adopted VIP for PCIe 7.0 . More Information: For more info on how Cadence PCIe Verification IP and TripleCheck VIP enables users to confidently verify IDE, see our VIP for PCI Express , VIP for Compute Express Link for and TripleCheck for PCI Express For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website .

Hello,

I'm using OrCad 17.2 and in the company I'm wokring at there was a change in the database folder (from driver F to G for example) and it effects the option of synchronise using the Part Manager. and changing manually each part in the Desgin Cahce can be a pain.

Is there any way I can make a TCL script that will run and replace a part cahce with other? Better if I can call from a table to read, and write from other collum.

I would really be happy for an example.

Thanks for the help.

Hello Folks,

Problem statement first: How does one properly setup tensorflow for running on a DSVM using a remote Docker environment? Can this be done in aml_config/*.runconfig?

I receive the following message and I would like to be able to utilize the increased speeds of the extended FMA operations.

tensorflow/core/platform/cpu_feature_guard.cc:140] Your CPU supports instructions that this TensorFlow binary was not compiled to use: AVX2 FMA

Background: I utilize a local docker environment managed through Azure ML Workbench for initial testing and code validation so that I'm not running an expensive DSVM constantly. Once I assess that my code is to my liking, I then run it on a remote docker instance on an Azure DSVM.

I want a consistent conda environment across my compute environments, so this works out extremely well. However, I cannot figure out how to control the tensorflow build to optimize for the hardware at hand (i.e. my local docker on macOS vs. remote docker on Ubuntu DSVM)

use the DBO function DboLib_RepalceCache to do the job of "Replace cache" 

in order to easy the job ,  type the code below . the code is a wrapper of the function metioned above

set lStatus [DboState]
set lSession $::DboSession_s_pDboSession
DboSession -this $lSession
set lDesignsIter [$lSession NewDesignsIter $lStatus]
set lDesign [$lDesignsIter NextDesign $lStatus]
set lNullObj NULL

set oldLibName [DboTclHelper_sMakeCString "E:\PROJECT_WORKLIB.OLB"]
set newLibName [DboTclHelper_sMakeCString "E:\MCU_PARTS_LIB.OLB"]

#DboLib_ReplaceCache wrapper
proc ReplaceCacheByName {partName} {
    global oldLibName
    global newLibName
    global lDesign
    set lPartStr [DboTclHelper_sMakeCString $partName]
    #set lNewStr [DboTclHelper_sMakeCString $newName]
    $lDesign ReplaceCache $lPartStr $oldLibName $lPartStr $newLibName 0 1
}

then use the tcl command like below to do the real job :

ReplaceCacheByName "CL10B104KB8NNNC_C12"

This is the 22nd installment of The Rationalist, my column for the Times of India.

Trade wars are on the rise, and it’s enough to get any nationalist all het up and excited. Earlier this week, Narendra Modi’s government announced that it would start imposing tariffs on 28 US products starting today. This is a response to similar treatment towards us from the US.

There is one thing I would invite you to consider: Trump and Modi are not engaged in a war with each other. Instead, they are waging war on their own people.

Let’s unpack that a bit. Part of the reason Trump came to power is that he provided simple and wrong answers for people’s problems. He responded to the growing jobs crisis in middle America with two explanations: one, foreigners are coming and taking your jobs; two, your jobs are being shipped overseas.

Both explanations are wrong but intuitive, and they worked for Trump. (He is stupid enough that he probably did not create these narratives for votes but actually believes them.) The first of those leads to the demonising of immigrants. The second leads to a demonising of trade. Trump has acted on his rhetoric after becoming president, and a modern US version of our old ‘Indira is India’ slogan might well be, “Trump is Tariff. Tariff is Trump.”

Contrary to the fulminations of the economically illiterate, all tariffs are bad, without exception. Let me illustrate this with an example. Say there is a fictional product called Brump. A local Brump costs Rs 100. Foreign manufacturers appear and offer better Brumps at a cheaper price, say Rs 90. Consumers shift to foreign Brumps.

Manufacturers of local Brumps get angry, and form an interest group. They lobby the government – or bribe it with campaign contributions – to impose a tariff on import of Brumps. The government puts a 20-rupee tariff. The foreign Brumps now cost Rs 110, and people start buying local Brumps again. This is a good thing, right? Local businesses have been helped, and local jobs have been saved.

But this is only the seen effect. The unseen effect of this tariff is that millions of Brump buyers would have saved Rs 10-per-Brump if there were no tariffs. This money would have gone out into the economy, been part of new demand, generated more jobs. Everyone would have been better off, and the overall standard of living would have been higher.

That brings to me to an essential truth about tariffs. Every tariff is a tax on your own people. And every intervention in markets amounts to a distribution of wealth from the people at large to specific interest groups. (In other words, from the poor to the rich.) The costs of this are dispersed and invisible – what is Rs 10 to any of us? – and the benefits are large and worth fighting for: Local manufacturers of Brumps can make crores extra. Much modern politics amounts to manufacturers of Brumps buying politicians to redistribute money from us to them.

There are second-order effects of protectionism as well. When the US imposes tariffs on other countries, those countries may respond by imposing tariffs back. Raw materials for many goods made locally are imported, and as these become expensive, so do those goods. That quintessential American product, the iPhone, uses parts from 43 countries. As local products rise in price because of expensive foreign parts, prices rise, demand goes down, jobs are lost, and everyone is worse off.

Trump keeps talking about how he wants to ‘win’ at trade, but trade is not a zero-sum game. The most misunderstood term in our times is probably ‘trade-deficit’. A country has a trade deficit when it imports more than what it exports, and Trump thinks of that as a bad thing. It is not. I run a trade deficit with my domestic help and my local grocery store. I buy more from them than they do from me. That is fine, because we all benefit. It is a win-win game.

Similarly, trade between countries is really trade between the people of both countries – and people trade with each other because they are both better off. To interfere in that process is to reduce the value created in their lives. It is immoral. To modify a slogan often identified with libertarians like me, ‘Tariffs are Theft.’

These trade wars, thus, carry a touch of the absurd. Any leader who imposes tariffs is imposing a tax on his own people. Just see the chain of events: Trump taxes the American people. In retaliation, Modi taxes the Indian people. Trump raises taxes. Modi raises taxes. Nationalists in both countries cheer. Interests groups in both countries laugh their way to the bank.

What kind of idiocy is this? How long will this lose-lose game continue?

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

This is the 23rd installment of The Rationalist, my column for the Times of India.

I had a strange dream last night. I dreamt that the government had passed a law that made using laptops illegal. I would have to write this column by hand. I would also have to leave my home in Mumbai to deliver it in person to my editor in Delhi. I woke up trembling and angry – and realised how Indian farmers feel every single day of their lives.

My column today is a tale of two satyagrahas. Both involve farmers, technology and the freedom of choice. One of them began this month – but first, let us go back to the turn of the millennium.

As the 1990s came to an end, cotton farmers across India were in distress. Pests known as bollworms were ravaging crops across the country. Farmers had to use increasing amounts of pesticide to keep them at bay. The costs of the pesticide and the amount of labour involved made it unviable – and often, the crops would fail anyway.

Then, technology came to the rescue. The farmers heard of Bt Cotton, a genetically modified type of cotton that kept these pests away, and was being used around the world. But they were illegal in India, even though no bad effects had ever been recorded. Well, who cares about ‘illegal’ when it is a matter of life and death?

Farmers in Gujarat got hold of Bt Cotton seeds from the black market and planted them. You’ll never guess what happened next. As 2002 began, all cotton crops in Gujarat failed – except the 10,000 hectares that had Bt Cotton. The government did not care about the failed crops. They cared about the ‘illegal’ ones. They ordered all the Bt Cotton crops to be destroyed.

It was time for a satyagraha – and not just in Gujarat. The late Sharad Joshi, leader of the Shetkari Sanghatana in Maharashtra, took around 10,000 farmers to Gujarat to stand with their fellows there. They sat in the fields of Bt Cotton and basically said, ‘Over our dead bodies.’ ¬Joshi’s point was simple: all other citizens of India have access to the latest technology from all over. They are all empowered with choice. Why should farmers be held back?

The satyagraha was successful. The ban on Bt Cotton was lifted.

There are three things I would like to point out here. One, the lifting of the ban transformed cotton farming in India. Over 90% of Indian farmers now use Bt Cotton. India has become the world’s largest producer of cotton, moving ahead of China. According to agriculture expert Ashok Gulati, India has gained US$ 67 billion in the years since from higher exports and import savings because of Bt Cotton. Most importantly, cotton farmers’ incomes have doubled.

Two, GMO crops have become standard across the world. Around 190 million hectares of GMO crops have been planted worldwide, and GMO foods are accepted in 67 countries. The humanitarian benefits have been massive: Golden Rice, a variety of rice packed with minerals and vitamins, has prevented blindness in countless new-born kids since it was introduced in the Philippines.

Three, despite the fear-mongering of some NGOs, whose existence depends on alarmism, the science behind GMO is settled. No harmful side effects have been noted in all these years, and millions of lives impacted positively. A couple of years ago, over 100 Nobel Laureates signed a petition asserting that GMO foods were safe, and blasting anti-science NGOs that stood in the way of progress. There is scientific consensus on this.

The science may be settled, but the politics is not. The government still bans some types of GMO seeds, such as Bt Brinjal, which was developed by an Indian company called Mahyco, and used successfully in Bangladesh. More crucially, a variety called HT Bt Cotton, which fights weeds, is also banned. Weeding takes up to 15% of a farmer’s time, and often makes farming unviable. Farmers across the world use this variant – 60% of global cotton crops are HT Bt. Indian farmers are so desperate for it that they choose to break the law and buy expensive seeds from the black market – but the government is cracking down. A farmer in Haryana had his crop destroyed by the government in May.

On June 10 this year, a farmer named Lalit Bahale in the Akola District of Maharashtra kicked off a satyagraha by planting banned seeds of HT Bt Cotton and Bt Brinjal. He was soon joined by thousands of farmers. Far from our urban eyes, a heroic fight has begun. Our farmers, already victimised and oppressed by a predatory government in countless ways, are fighting for their right to take charge of their lives.

As this brave struggle unfolds, I am left with a troubling question: All those satyagrahas of the past by our great freedom fighters, what were they for, if all they got us was independence and not freedom?

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

This is the 24th installment of The Rationalist, my column for the Times of India.

Back in the last decade, I was a cricket journalist for a few years. Then, around 12 years ago, I quit. I was jaded as hell. Every game seemed like déjà vu, nothing new, just another round on the treadmill. Although I would remember her fondly, I thought me and cricket were done.

And then I fell in love again. Cricket has changed in the last few years in glorious ways. There have been new ways of thinking about the game. There have been new ways of playing the game. Every season, new kinds of drama form, new nuances spring up into sight. This is true even of what had once seemed the dullest form of the game, one-day cricket. We are entering into a brave new world, and the team leading us there is England. No matter what happens in the World Cup final today – a single game involves a huge amount of luck – this England side are extraordinary. They are the bridge between eras, leading us into a Golden Age of Cricket.

I know that sounds hyperbolic, so let me stun you further by saying that I give the IPL credit for this. And now, having woken up you up with such a jolt on this lovely Sunday morning, let me explain.

Twenty20 cricket changed the game in two fundamental ways. Both ended up changing one-day cricket. The first was strategy.

When the first T20 games took place, teams applied an ODI template to innings-building: pinch-hit, build, slog. But this was not an optimal approach. In ODIs, teams have 11 players over 50 overs. In T20s, they have 11 players over 20 overs. The equation between resources and constraints is different. This means that the cost of a wicket goes down, and the cost of a dot ball goes up. Critically, it means that the value of aggression rises. A team need not follow the ODI template. In some instances, attacking for all 20 overs – or as I call it, ‘frontloading’ – may be optimal.

West Indies won the T20 World Cup in 2016 by doing just this, and England played similarly. And some sides began to realise was that they had been underestimating the value of aggression in one-day cricket as well.

The second fundamental way in which T20 cricket changed cricket was in terms of skills. The IPL and other leagues brought big money into the game. This changed incentives for budding cricketers. Relatively few people break into Test or ODI cricket, and play for their countries. A much wider pool can aspire to play T20 cricket – which also provides much more money. So it makes sense to spend the hundreds of hours you are in the nets honing T20 skills rather than Test match skills. Go to any nets practice, and you will find many more kids practising innovative aggressive strokes than playing the forward defensive.

As a result, batsmen today have a wider array of attacking strokes than earlier generations. Because every run counts more in T20 cricket, the standard of fielding has also shot up. And bowlers have also reacted to this by expanding their arsenal of tricks. Everyone has had to lift their game.

In one-day cricket, thus, two things have happened. One, there is better strategic understanding about the value of aggression. Two, batsmen are better equipped to act on the aggressive imperative. The game has continued to evolve.

Bowlers have reacted to this with greater aggression on their part, and this ongoing dialogue has been fascinating. The cricket writer Gideon Haigh once told me on my podcast that the 2015 World Cup featured a battle between T20 batting and Test match bowling.

This England team is the high watermark so far. Their aggression does not come from slogging. They bat with a combination of intent and skills that allows them to coast at 6-an-over, without needing to take too many risks. In normal conditions, thus, they can coast to 300 – any hitting they do beyond that is the bonus that takes them to 350 or 400. It’s a whole new level, illustrated by the fact that at one point a few days ago, they had seven consecutive scores of 300 to their name. Look at their scores over the last few years, in fact, and it is clear that this is the greatest batting side in the history of one-day cricket – by a margin.

There have been stumbles in this World Cup, but in the bigger picture, those are outliers. If England have a bad day in the final and New Zealand play their A-game, England might even lose today. But if Captain Morgan’s men play their A-game, they will coast to victory. New Zealand does not have those gears. No other team in the world does – for now.

But one day, they will all have to learn to play like this.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

Read this blog to know how you can easily create and insert connect modules using Spectre AMS Designer with the Verilog-AMS standard language defined by Accellera. (read more)

Hi All

I am looking for the functions which are different about OrCAD Professional and Allegro tier.

is there any resource?

regard

I'm not able to export a CIS Standard BOM to a Microsoft 365 Excel (business subscription, version 2111).
Selecting the "Export BOM report to Excel" option opens a new Excel window, but OrCAD (17.4-2019 S023) won't fill it with any data...

I tried it on a different PC with Microsoft Office Professional Plus 2019 Excel (strangely the version number is the same: 2111) and with OrCAD 17.4-2019 S016 and it worked flawlessly.

Does anybody experiencing the same issue?
Does the Excel variant, the OrCAD version or the PC itself causing this?
Thanks for any help!

Hello,

A mybe silly question came to my mind: When routing sense lines, is it better to hav them as close as possible to DUT or afer the decoupling capacitors ?

Force in red, sense in purple.

Best way is 1 or 2 ?

Thanks in advance and Merry Christmas to everybody !

Hi

In the environment I'm currently working, axes are shown for schematic, symbol, and layout views.For schematics and symbols, I'd prefer a dim gray, such that the axes are just visible but not dominant. For the layout, I'd prefer a brighter color. Is there a way to realize this? So far when I change the color of the 'axis' layer in the display resource editor, the axes in all three views get changed together:

Thanks very much for your input!

I need to add a new CDF parameter called "mag" to symbols in a given library using skill script in which the symbol size can be controlled and call back it each time this library is used so that all the symbols are updated.

Dear community

We would like to have more minimalistic and customized sheet borders for our schematics. I used this guide to create a starting point. Essentially, I made a copy of the US_8ths library and modified the Title symbol to look something like that:

Problem 1

The variable ilInst~>libName points to the library of the sheet border symbols, not to the library of the schematic. How do I need to modify this field in order to see the library name of the schematic where the border is instantiated?

Problem 2

The function CCSgetCreator() was taken from here. This solution does not seem to work with our management toll (we use VersIC); the function always returns nil as value. What is the simplest way to display the name of the user that created the schematic? A custom field that could be filled manually would also do the job for us; it doesn't need to be something that automatically fetches data from a database system.

Thanks for any input.

Hello everyone,

I hope you're all doing well. I’ve set up two testbenches (TB1 and TB2) for my Design Under Test (DUT) using Cadence IC6.1.8-64b.500.21 tools, as shown in the attached figure. The DUT has multiple views available: schematic, Calibre, Maestro, and Symbol, and each testbench uses the same DUT in different scenarios. Currently, I have to manually switch between these views, but I would like to streamline this process.

My goal is to use a single config view that allows me to switch between the schematic and the extracted (Calibre) views. Ideally, I would like to have a configuration file where making changes once would update both testbenches (TB1 and TB2) automatically. In other words, when I modify one config, both testbenches should reflect this update for a single simulation run.

I would really appreciate it if you could guide me on the following:

1. How to create a config view for my DUT that can be used to easily switch between the schematic and extracted views, impacting both TB1 and TB2.
2. Where to specify view priorities or other settings to control which view is used during simulation.
3. Best practices for using a config file in this scenario, so that it ensures consistency across multiple testbenches.

Please refer to the attached figure to get a better understanding of the setup I’m using, where both TB1 and TB2 include the same DUT with multiple available views.

Thank you so much for your time and assistance!

Hello,

I am aware of command script .svcf file that saves signals and loads them in while opening Simvision.

I am wondering, if there is a way for saving signals while we are in an interactive session and loading them next time when we open Simvision interactively.

Any ideas on how to do this?

Thank you in advance.

Swetha. C

I'm working on the code coverage. Doing a metrics analysis by default we see overall average grade and overall covered. But when i do a block analysis on an instance i see overall covered grade, code covered grade, block covered grade, statement covered grade, expression covered grade, toggle covered grade.

As I dont know the difference I started to read the IMC user guide and came to know there are 3 things we come across while doing a code coverage local, covered, average

From my understanding

local - child instances metrics doesnt reach the parent level. For example, we have an instance Q and its sub instances like Q.a, Q.b. Block Local grade of Q can be 100% even when its instances Q.a and Q.b a block local grades isnt at 100%.

In the attached image there is formula 

The key difference between average and covered is the weights.

Average : Mathematically taking the above scenario where Q.a, and Q.b has 10 blocks each. Q.a has covered 8 blocks and q.b has covered 2 blocks. Now if we take the normal average it should be total covered/ totatl number = 8+2/10+10 yielding 50%. But when we add weights saying Q.a is 70% and Q.b is 30% the new number would be (8*0.7+2*0.3) / (10*0.7+10*0.3) resulting 62%. Because of the weights we see 12% bump.

Covered: there is no role of weights.

Among these 3 metrics i've changed my default view to this in the image to get more realistic picture when i do analyze metrics. Do you guys agree with the approach?

We are trying to run compilation, elab and sim with command xrun -r -u alu, where alu is one of the units to execute. we are getting the following errors.

1) xmsim: *E,DLMKDF: Unable to add default DEFINE std       /home/xxxx/Cad/xcelium/tools/inca/files/STD.
    xmsim: *E,DLMKDF: Unable to add default DEFINE synopsys  /home/xxxx/Cad/xcelium/tools/inca/files/SYNOPSYS

2) xmsim: *W,DLNOHV: Unable to find an 'hdl.var' file to load in.

What is the purpose of hdl.var

3) xmsim: *F,NOSNAP: Snapshot 'alu' does not exist in the libraries.

I cannot see in log files, which libraries is it referring to??

Any one request you to help on how to debug these.

Hi

I have tried using "add net constraints" command to place one-cold constraints on a tristate enable bus. In the command line we need to specify the "net pathname" on which the constraints are to be enforced.

The bus here is 20-bit. How should the net pathname be specified to make this 20-bit bus signals one_hot or one_cold.

The bus was declared as follows:
ten_bus [19:0]

The command I used was

add net constraints one_hot /ren_bus[19]

What would the above command mean?
Should we not specify all the nets' pathnames on the bus?
Is it sufficient to specify the pathname of one net on the bus?
I could not get much info regarding the functionality of this command. I would be obliged if anyone can throw some light.

Thanks
Prasad.

Join this insightful on-demand webinar event "SI/PI Simulation and Measurement Correlation Forum" available through Signal Integrity Journal that features industry expert presentations ranging from chip to package to complex board designs.(read more)

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The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2022.1 HF2 release is now available for download at Cadence Downloads. For the list of CCRs fixed in the 2022.1 HF2 release, see the README.txt file in the installation hierarchy.(read more)

Microwaves & RF's David Maliniak interviews Sherry Hess of Cadence about recently announced products of Optimality and OnCloud.(read more)

Hello,

I am trying to design an RF mixer for a TX.
Assume my input IF signal is at 1 GHz, my LO at 2 GHz and I want my RF at 3 GHz, and assume that the mixer fully works after testing it with HB.
How to simply set the envelope analysis to check the EVM ?
I read through the documentation but I couldn't get it (I couldn't fully understand the settings of the source, probe, analysis.)
Which source and probe to use? I want custom modulation with custom bandwidth and center frequency.
Is there some examples for the ENVLP analysis ?

I am using IC23.1 and spectre 20.1.354.

Che(read more)

The ICADVM20.1 ISR26 and IC6.1.8 ISR26 production releases are now available for download.(read more)

This blog introduces you to an efficient way to debug interface elements or connect modules in a mixed-signal simulation.(read more)

This blog describes how to efficiently use Virtuoso Visualization and Analysis XL.(read more)

The ICADVM20.1 ISR27 and IC6.1.8 ISR27 production releases are now available for download.(read more)

Hello everyone!

Have you ever used the axlDllOpen function for Allegro 16.6?

It doesn't work for me. Please give me your solution.
Thank you.

HoangKhoi

Dear Community,

I have created a PCB layout with multiple high-speed nets, I want to check the SI like how signals are reflected and taken to each other.

I have the OrCAD X Professional, how to check the reflection and crosstalk using the OrCAD X Professional software version 24.1.

I want to create a topology flow to the PCB layout and perform the reflection and crosstalk.

Regards,

Rohit Rohan

Dear Community,

In OrCAD X Profession, the workspace feature enables the users to store the libraries (Schematic Symbol, Footprint and PSpice Models) and Designs (Schematic and PCB layout) in the cloud workspace.

But storing these libraries and design are stored in servers in the USA, Europe, Asia and Japan Servers.

I don't want to store my designs in any of these servers instead I want to create the workspace in my local PC and store all my libraries and designs in the local workspace.

Is this possible, if possible then can anyone provide the steps/procedure or videos of how to do it?

Regards,

Rohit Rohan

The traditional methods of power analysis lag by various shortcomings and challenges:

• Getting an accurate measure of RTL power consumption during design exploration
• Getting consistent power through the design progress from RTL to P&R.
• System-level verification tools are disconnected from the implementation tools that translate RTL to gates and wires.

The Cadence Joules RTL Power Solution closes this gap by delivering time-based RTL power analysis with system-level runtimes, capacity, and high-quality estimates of gates and wires based on production implementation technology. The Cadence Joules RTL Power Solution is an RTL power analysis tool that provides a unified engine to compute gate netlist power and estimate RTL power. The Joules solution delivers 20X faster time-based RTL power analysis and can analyze multi-million instance designs overnight, with impressive accuracy within 15% of signoff power.

Moreover, it integrates seamlessly with numerous Cadence platforms, eliminating compatibility and correlation issues! In addition, the Joules RTL Power Solution GUI (Graphical User Interface) helps you analyze/debug the power estimation/results using several GUI capabilities.

Want to take a tour of this power estimation world? Gear up to attend the training class created just for you to dive deep into the entire flow and explore this exciting power estimation method/flow with hands-on labs in two days!

Training

In the Joules Power Calculator Training course, you will identify solutions and features for RTL power using Cadence Joules RTL Power Solution. You will set up and run the RTL power flow with Joules RTL Power Solution and identify Joules's Graphical User Interface (GUI) capabilities. The training also explores how you can estimate power using vectorless power, stimulus flow, RTL Stim to Gate flow, and replay flow, and also interfaces Joules with Cadence's Palladium Emulation Platform. You will estimate power at the chip level and understand how to navigate the design and data mining using Joules.

The training also covers power exploration features and how to analyze ideal power and ODC-driven sequential clock gating. You will identify low-activity registers at the clock gate. You will also identify techniques to analyze power, generate various reports, and analyze results through Joules GUI. The training covers multiple strategies to debug low stimulus annotation and how you can better correlate RTL power with signoff. You also identify Genus-Joules Integration. In addition, we ensure that your learning journey is smooth with hands-on labs covering various design scenarios.

Lab Videos

To start you on your exciting journey as an RTL power analysis expert, we have created a series of short channel lab videos on our Customer Support site: Lab Demo: Setting Up and Running Basic RTL Power Flow in Joules RTL Power Solution (Video). You can refer to each lab module's instructions in demo format. This will help accelerate your tool ramp-up and help you perform the lab steps more quickly if you are stuck. You might be a beginner in the RTL power analysis world, but we can help you sail through it smoothly.

What's Next?

Grab your badge after finishing the training and flaunt your expertise!

Related Training

• Genus Low-Power Synthesis Flow with IEEE 1801
• Low-Power Synthesis Flow with Genus Stylus Common UI

Related Blogs

• Do You Want to Flaunt Your Expertise? Grab the Digital Badge Today!
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• Let's Replay the Process of Power Estimation with the Power of 'x'
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• What's Inside Joules Graphical User Interface
• Joules – Power Exploration Capabilities

Power efficiency is a critical factor in the fast-evolving world of semiconductor design.

The IEEE 1801 standard, also known as UPF (Unified Power Format), was developed by the IEEE to address the intricate challenges associated with power management in contemporary semiconductor designs. This standard offers a uniform framework for defining power domains, power states, and power intent, ensuring consistency across diverse tools and phases of the design process. By utilizing UPF, you can precisely model and regulate power consumption, a critical aspect for battery-operated devices, high-performance computing, and energy-efficient designs.

The key concepts of IEEE 1801 are:

1. Power domains
2. Power states
3. Power gating and isolation
4. Power switches
5. Level shifters, isolation, and retention cells
6. Macro model

Based on these building blocks, you write the power intent of the design.

The power intent for the design includes identifying/implementing low-power strategies that provide a clear description of the power architecture of a design.

The power definitions can effectively manage power consumption and ensure the chip meets its power and performance requirements.

You can start by creating the Power Supply Network, which defines how power is supplied to the design's various power domains and logic cells.

What's the next step to build the file? How do you understand the various concepts related to IEEE 1801? How do you complete the rest of the power intent file?

Relax!

Gear up to attend the training class created just for you to dive deep into the entire format and explore this exciting power specification method/format with hands-on labs in one day!

Training

Fundamentals of IEEE 1801 Low-Power Specification Format Training

This course is a complete tutorial for understanding the fundamentals of IEEE 1801 low-power specification format concepts. You learn about IEEE 1801 power supply networks, ground ports and nets, creating and connecting supply ports/nets, power domain, power switch, power states, defining isolation and level shifter strategies, hierarchical IEEE 1801, and various versions of the IEEE 1801. You also explore how power intent information can be used for a design across various flow stages, such as functional verification, synthesis, logic equivalency checking, place-and-route, test, timing signoff, power integrity, and so forth, using Cadence^® tools.

Labs

We ensure that your learning journey is smooth with hands-on labs covering various design scenarios.

Lab Videos

Now, the exciting part is that to help you further, we have created engaging videos of the training labs. You can refer to the lab module's instructions in demo format at https://support.cadence.com.

Lab Demo: Checking Power Supply Network in IEEE 1801 format and Running IEEE 1801 Quality Checks using Conformal Low Power

Lab Demo: Checking Power Intent for The Macro Connections in IEEE 1801 Format And Running IEEE 1801 Quality Checks using Conformal Low Power 

Online Class

Here is the course link.

Get ready for the most thrilling experience with Accelerated Learning!

The more you know, the faster you go!

Grab the cycle  or hike it, based on your existing knowledge.

Take the quiz and increase your learning pace!!

What's Next?

Grab your Badge after finishing the training and flaunt the expertise you have built up. 😊

Ready to take a tour of this power specification world? Let's help you enroll in this course.

We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information. If you want to ensure you are always the first to know about anything new in training, you can use the SUBSCRIBE button on the landing page to sign up for our regular training newsletters.

Related Short Training Bytes/Videos

Enhance the learning experience with short videos:

Genus Synthesis Solution: Video Library

 Joules RTL Power Solution: Video Library

Related Training

 Low-Power Synthesis Flow with Genus Synthesis Solution

Genus Low-Power Synthesis Flow with IEEE 1801

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In the era of Artificial Intelligence, front-end designers need a magical key to empower them with technology that enables fully optimized RTL for implementation handoff and provides RTL designers with capabilities to accurately assist in the implementation convergence process.

The magic lies with Cadence Joules RTL Design Studio, an expert system that leverages generative AI for RTL design exploration, triages possible causes of violations, and additional insights that empower designers to understand how to address issues in their RTL, leading to smarter and more efficient chip design.

This unlocks the immense debugging and design analysis capabilities from a single, unified cockpit, enabling fully optimized RTL design prior to implementation handoff for the front-end designers and addresses all aspects of physical design by adding visibility into power, performance, area, and congestion (PPAC)

One critical component is the clock tree, which distributes the clock signal to all sequential elements, such as flip-flops and latches. Designers need the right techniques in the beginning stage to optimize the clock tree structure, ensuring that their designs meet the required timing specifications, reduce power consumption, maintain signal integrity, and increase reliability.

 This incredible feature is part of the Joules RTL Design Studio.

How do you efficiently explore the clock tree structure to optimize the results using Joules RTL Design Studio?

Joules Studio allows viewing a simplified version of the clock structure. This feature is primarily designed to help display clock frequency scaling through clock dividers. You can customize colors, symbols, and design elements using an input file. Additionally, you can cross-probe the custom clock tree structure to other widgets and the main schematic view in Joules Studio.

Moreover, with the clock tree preference features of the ideal clock tree wizard in Joules Studio GUI, you can highlight clock path, generate clocks and master clock, set case analysis, fold and unfold instances, undo and redo, set sense and disable timing, color preference, etc.

You can binge on these features through the channel videos posted on the support portal, which covers the Joules RTL Design Studio GUI Clock Tree Structure and Features of Ideal Clock Tree Wizard.

You can refer to the videos on Cadence Online Support (Cadence login required).

​Video Links:
Viewing Custom Clock Tree Structure in Joules RTL Design Studio (Video) 

Exploring Clock Tree Preference Widget of Ideal Clock Tree Wizard in Joules RTL Design Studio (Video) 

Want to learn more?

Explore the one-stop solution Joules RTL Design Studio Product Page on Cadence Online Support (Cadence login required).

Related Resources 

Related Training Bytes:

Understanding Prototype Design Flow in Joules RTL Design Studio (Video)

Running Prototype Implementation Flow in Joules RTL Design Studio (Video)

Understanding Analyze Timing By Hierarchy In Joules RTL Design Studio (Video)

Related Courses:

• Joules Power Calculator

Want to Enroll in this Course?

We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information.

Please don't forget to obtain your Digital Badge after completing the training.

Related Blogs:

Let's Discover the Secret to Enhance Design's PPAC in a Single Cockpit! - Digital Design - Cadence Blogs - Cadence Community

Joules RTL Design Studio: Accelerating Fully Optimized RTL - Digital Design - Cadence Blogs - Cadence Community

Let's Replay the Process of Power Estimation with the Power of 'x'! - Digital Design - Cadence Blogs - Cadence Community

Is Design Power Estimation Lowering Your Power? Delegate and Relax! - Digital Design - Cadence Blogs - Cadence Community

Cyprus is ranked first in fDi’s Island Economies of the Future rankings, followed by the Dominican Republic and Sri Lanka. Cathy Mullan and Naomi Davies detail the results.

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Serbia’s technology cluster is gaining momentum and attracting FDI, for both its software and hardware expertise.